forked from KolibriOS/kolibrios
575 lines
17 KiB
C
575 lines
17 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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//#include <linux/seq_file.h>
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//#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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/* rv515 depends on : */
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void r100_hdp_reset(struct radeon_device *rdev);
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int r100_cp_reset(struct radeon_device *rdev);
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int r100_rb2d_reset(struct radeon_device *rdev);
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int r100_gui_wait_for_idle(struct radeon_device *rdev);
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int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
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int rv370_pcie_gart_enable(struct radeon_device *rdev);
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void rv370_pcie_gart_disable(struct radeon_device *rdev);
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void r420_pipes_init(struct radeon_device *rdev);
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void rs600_mc_disable_clients(struct radeon_device *rdev);
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void rs600_disable_vga(struct radeon_device *rdev);
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/* This files gather functions specifics to:
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* rv515
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*
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* Some of these functions might be used by newer ASICs.
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*/
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int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
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int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
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void rv515_gpu_init(struct radeon_device *rdev);
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int rv515_mc_wait_for_idle(struct radeon_device *rdev);
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#if 0
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/*
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* MC
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*/
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int rv515_mc_init(struct radeon_device *rdev)
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{
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uint32_t tmp;
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int r;
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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if (rv515_debugfs_pipes_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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if (rv515_debugfs_ga_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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rv515_gpu_init(rdev);
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rv370_pcie_gart_disable(rdev);
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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printk(KERN_WARNING "[drm] Disabling AGP\n");
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rdev->flags &= ~RADEON_IS_AGP;
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rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
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} else {
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rdev->mc.gtt_location = rdev->mc.agp_base;
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}
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}
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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/* Program GPU memory space */
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rs600_mc_disable_clients(rdev);
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if (rv515_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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/* Write VRAM size in case we are limiting it */
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WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
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tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
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WREG32(0x134, tmp);
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tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
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tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
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tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
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WREG32_MC(RV515_MC_FB_LOCATION, tmp);
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WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
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WREG32(0x310, rdev->mc.vram_location);
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if (rdev->flags & RADEON_IS_AGP) {
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tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
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tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
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tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
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WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
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WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
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WREG32_MC(RV515_MC_AGP_BASE_2, 0);
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} else {
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WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
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WREG32_MC(RV515_MC_AGP_BASE, 0);
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WREG32_MC(RV515_MC_AGP_BASE_2, 0);
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}
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return 0;
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}
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void rv515_mc_fini(struct radeon_device *rdev)
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{
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rv370_pcie_gart_disable(rdev);
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radeon_gart_table_vram_free(rdev);
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radeon_gart_fini(rdev);
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}
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/*
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* Global GPU functions
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*/
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void rv515_ring_start(struct radeon_device *rdev)
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{
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unsigned gb_tile_config;
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int r;
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/* Sub pixel 1/12 so we can have 4K rendering according to doc */
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gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
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switch (rdev->num_gb_pipes) {
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case 2:
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gb_tile_config |= R300_PIPE_COUNT_R300;
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break;
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case 3:
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gb_tile_config |= R300_PIPE_COUNT_R420_3P;
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break;
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case 4:
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gb_tile_config |= R300_PIPE_COUNT_R420;
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break;
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case 1:
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default:
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gb_tile_config |= R300_PIPE_COUNT_RV350;
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break;
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}
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r = radeon_ring_lock(rdev, 64);
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if (r) {
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return;
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}
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radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
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radeon_ring_write(rdev,
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RADEON_ISYNC_ANY2D_IDLE3D |
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RADEON_ISYNC_ANY3D_IDLE2D |
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RADEON_ISYNC_WAIT_IDLEGUI |
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RADEON_ISYNC_CPSCRATCH_IDLEGUI);
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radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
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radeon_ring_write(rdev, gb_tile_config);
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radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
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radeon_ring_write(rdev,
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RADEON_WAIT_2D_IDLECLEAN |
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RADEON_WAIT_3D_IDLECLEAN);
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radeon_ring_write(rdev, PACKET0(0x170C, 0));
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radeon_ring_write(rdev, 1 << 31);
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radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET0(0x42C8, 0));
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radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
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radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
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radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
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radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
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radeon_ring_write(rdev,
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RADEON_WAIT_2D_IDLECLEAN |
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RADEON_WAIT_3D_IDLECLEAN);
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radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
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radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
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radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
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radeon_ring_write(rdev,
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((6 << R300_MS_X0_SHIFT) |
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(6 << R300_MS_Y0_SHIFT) |
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(6 << R300_MS_X1_SHIFT) |
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(6 << R300_MS_Y1_SHIFT) |
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(6 << R300_MS_X2_SHIFT) |
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(6 << R300_MS_Y2_SHIFT) |
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(6 << R300_MSBD0_Y_SHIFT) |
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(6 << R300_MSBD0_X_SHIFT)));
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radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
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radeon_ring_write(rdev,
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((6 << R300_MS_X3_SHIFT) |
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(6 << R300_MS_Y3_SHIFT) |
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(6 << R300_MS_X4_SHIFT) |
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(6 << R300_MS_Y4_SHIFT) |
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(6 << R300_MS_X5_SHIFT) |
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(6 << R300_MS_Y5_SHIFT) |
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(6 << R300_MSBD1_SHIFT)));
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radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
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radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
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radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
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radeon_ring_write(rdev,
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R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
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radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
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radeon_ring_write(rdev,
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R300_GEOMETRY_ROUND_NEAREST |
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R300_COLOR_ROUND_NEAREST);
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radeon_ring_write(rdev, PACKET0(0x20C8, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_unlock_commit(rdev);
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}
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void rv515_errata(struct radeon_device *rdev)
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{
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rdev->pll_errata = 0;
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}
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int rv515_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32_MC(RV515_MC_STATUS);
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if (tmp & RV515_MC_STATUS_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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}
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return -1;
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}
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void rv515_gpu_init(struct radeon_device *rdev)
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{
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unsigned pipe_select_current, gb_pipe_select, tmp;
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r100_hdp_reset(rdev);
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r100_rb2d_reset(rdev);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"reseting GPU. Bad things might happen.\n");
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}
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rs600_disable_vga(rdev);
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r420_pipes_init(rdev);
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gb_pipe_select = RREG32(0x402C);
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tmp = RREG32(0x170C);
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pipe_select_current = (tmp >> 2) & 3;
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tmp = (1 << pipe_select_current) |
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(((gb_pipe_select >> 8) & 0xF) << 4);
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WREG32_PLL(0x000D, tmp);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"reseting GPU. Bad things might happen.\n");
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}
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if (rv515_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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#endif
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int rv515_ga_reset(struct radeon_device *rdev)
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{
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uint32_t tmp;
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bool reinit_cp;
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int i;
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dbgprintf("%s\n\r",__FUNCTION__);
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reinit_cp = rdev->cp.ready;
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rdev->cp.ready = false;
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for (i = 0; i < rdev->usec_timeout; i++) {
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WREG32(RADEON_CP_CSQ_MODE, 0);
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WREG32(RADEON_CP_CSQ_CNTL, 0);
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WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
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(void)RREG32(RADEON_RBBM_SOFT_RESET);
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udelay(200);
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WREG32(RADEON_RBBM_SOFT_RESET, 0);
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/* Wait to prevent race in RBBM_STATUS */
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mdelay(1);
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tmp = RREG32(RADEON_RBBM_STATUS);
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if (tmp & ((1 << 20) | (1 << 26))) {
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DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
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/* GA still busy soft reset it */
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WREG32(0x429C, 0x200);
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WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
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WREG32(0x43E0, 0);
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WREG32(0x43E4, 0);
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WREG32(0x24AC, 0);
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}
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/* Wait to prevent race in RBBM_STATUS */
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mdelay(1);
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tmp = RREG32(RADEON_RBBM_STATUS);
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if (!(tmp & ((1 << 20) | (1 << 26)))) {
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break;
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}
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = RREG32(RADEON_RBBM_STATUS);
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if (!(tmp & ((1 << 20) | (1 << 26)))) {
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DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
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tmp);
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DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
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DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
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DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
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if (reinit_cp) {
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return r100_cp_init(rdev, rdev->cp.ring_size);
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}
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return 0;
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}
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DRM_UDELAY(1);
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}
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tmp = RREG32(RADEON_RBBM_STATUS);
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DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
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return -1;
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}
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int rv515_gpu_reset(struct radeon_device *rdev)
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{
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uint32_t status;
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dbgprintf("%s\n\r",__FUNCTION__);
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/* reset order likely matter */
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status = RREG32(RADEON_RBBM_STATUS);
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/* reset HDP */
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r100_hdp_reset(rdev);
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/* reset rb2d */
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if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
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r100_rb2d_reset(rdev);
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}
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/* reset GA */
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if (status & ((1 << 20) | (1 << 26))) {
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rv515_ga_reset(rdev);
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}
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/* reset CP */
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status = RREG32(RADEON_RBBM_STATUS);
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if (status & (1 << 16)) {
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r100_cp_reset(rdev);
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}
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/* Check if GPU is idle */
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status = RREG32(RADEON_RBBM_STATUS);
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if (status & (1 << 31)) {
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DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
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return -1;
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}
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DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
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return 0;
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}
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#if 0
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/*
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* VRAM info
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*/
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static void rv515_vram_get_type(struct radeon_device *rdev)
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{
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uint32_t tmp;
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rdev->mc.vram_width = 128;
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rdev->mc.vram_is_ddr = true;
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tmp = RREG32_MC(RV515_MC_CNTL);
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tmp &= RV515_MEM_NUM_CHANNELS_MASK;
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switch (tmp) {
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case 0:
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rdev->mc.vram_width = 64;
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break;
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case 1:
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rdev->mc.vram_width = 128;
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break;
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default:
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rdev->mc.vram_width = 128;
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break;
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}
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}
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void rv515_vram_info(struct radeon_device *rdev)
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{
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rv515_vram_get_type(rdev);
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rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
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rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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}
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#endif
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/*
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* Indirect registers accessor
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*/
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uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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uint32_t r;
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WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
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r = RREG32(R520_MC_IND_DATA);
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WREG32(R520_MC_IND_INDEX, 0);
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return r;
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}
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void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
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WREG32(R520_MC_IND_DATA, (v));
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WREG32(R520_MC_IND_INDEX, 0);
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}
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|
|
uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
uint32_t r;
|
|
|
|
WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
|
|
(void)RREG32(RADEON_PCIE_INDEX);
|
|
r = RREG32(RADEON_PCIE_DATA);
|
|
return r;
|
|
}
|
|
|
|
void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
|
|
(void)RREG32(RADEON_PCIE_INDEX);
|
|
WREG32(RADEON_PCIE_DATA, (v));
|
|
(void)RREG32(RADEON_PCIE_DATA);
|
|
}
|
|
|
|
#if 0
|
|
/*
|
|
* Debugfs info
|
|
*/
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
uint32_t tmp;
|
|
|
|
tmp = RREG32(R400_GB_PIPE_SELECT);
|
|
seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
|
|
tmp = RREG32(R500_SU_REG_DEST);
|
|
seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
|
|
tmp = RREG32(R300_GB_TILE_CONFIG);
|
|
seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
|
|
tmp = RREG32(R300_DST_PIPE_CONFIG);
|
|
seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
|
|
return 0;
|
|
}
|
|
|
|
static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
uint32_t tmp;
|
|
|
|
tmp = RREG32(0x2140);
|
|
seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
|
|
radeon_gpu_reset(rdev);
|
|
tmp = RREG32(0x425C);
|
|
seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list rv515_pipes_info_list[] = {
|
|
{"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
|
|
};
|
|
|
|
static struct drm_info_list rv515_ga_info_list[] = {
|
|
{"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
|
|
};
|
|
#endif
|
|
|
|
int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Asic initialization
|
|
*/
|
|
static const unsigned r500_reg_safe_bm[159] = {
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
|
|
0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
|
|
0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
|
|
0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
|
|
0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
|
|
0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
|
|
0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
0x0003FC01, 0x3FFFFCF8, 0xFE800B19,
|
|
};
|
|
|
|
|
|
|
|
int rv515_init(struct radeon_device *rdev)
|
|
{
|
|
dbgprintf("%s\n\r",__FUNCTION__);
|
|
|
|
rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
|
|
rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
|
|
return 0;
|
|
}
|