forked from KolibriOS/kolibrios
523 lines
17 KiB
PHP
523 lines
17 KiB
PHP
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2005-01-11 10:30 ******* Source: AT90S4433.xml ***********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "4433def.inc"
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;* Title : Register/Bit Definitions for the AT90S4433
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;* Date : 2005-01-11
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;* Version : 2.14
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;* Support E-mail : avr@atmel.com
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;* Target MCU : AT90S4433
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _4433DEF_INC_
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#define _4433DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device AT90S4433
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#pragma AVRPART ADMIN PART_NAME AT90S4433
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x92
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.equ SIGNATURE_002 = 0x03
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#pragma AVRPART CORE CORE_VERSION V1
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SP = 0x3d
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.equ GIMSK = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK = 0x39
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.equ TIFR = 0x38
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0 = 0x33
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.equ TCNT0 = 0x32
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.equ TCCR1A = 0x2f
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.equ TCCR1B = 0x2e
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.equ TCNT1H = 0x2d
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.equ TCNT1L = 0x2c
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.equ OCR1H = 0x2b
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.equ OCR1L = 0x2a
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.equ ICR1H = 0x27
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.equ ICR1L = 0x26
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.equ WDTCR = 0x21
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.equ EEAR = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ PORTC = 0x15
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.equ DDRC = 0x14
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.equ PINC = 0x13
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.equ PORTD = 0x12
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.equ DDRD = 0x11
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.equ PIND = 0x10
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.equ SPDR = 0x0f
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.equ SPSR = 0x0e
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.equ SPCR = 0x0d
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.equ UDR = 0x0c
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.equ UCSRA = 0x0b
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.equ UCSRB = 0x0a
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.equ UBRR = 0x09
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.equ ACSR = 0x08
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.equ ADMUX = 0x07
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.equ ADCSR = 0x06
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.equ ADCH = 0x05
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.equ ADCL = 0x04
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.equ UBRRHI = 0x03
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; ***** BIT DEFINITIONS **************************************************
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ; Analog Comparator Input Capture Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ AINBG = 6 ; Analog Comparator Bandgap Select
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.equ ACD = 7 ; Analog Comparator Disable
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; ***** AD_CONVERTER *****************
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; ADMUX - The ADC multiplexer Selection Register
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.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
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.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
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.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
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.equ ADCBG = 6 ; ADC Bandgap Select
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; ADCSR - The ADC Control and Status register
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.equ ADPS0 = 0 ; ADC Prescaler Select Bits
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.equ ADPS1 = 1 ; ADC Prescaler Select Bits
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.equ ADPS2 = 2 ; ADC Prescaler Select Bits
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.equ ADIE = 3 ; ADC Interrupt Enable
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.equ ADIF = 4 ; ADC Interrupt Flag
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.equ ADFR = 5 ; ADC Free Running Select
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.equ ADSC = 6 ; ADC Start Conversion
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.equ ADEN = 7 ; ADC Enable
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; ADCH - ADC Data Register High Byte
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.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
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.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
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; ADCL - ADC Data Register Low Byte
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.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
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.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
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.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
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.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
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.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
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.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
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.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
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.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
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; ***** UART *************************
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; UDR - UART I/O Data Register
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.equ UDR0 = 0 ; UART I/O Data Register bit 0
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.equ UDR1 = 1 ; UART I/O Data Register bit 1
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.equ UDR2 = 2 ; UART I/O Data Register bit 2
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.equ UDR3 = 3 ; UART I/O Data Register bit 3
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.equ UDR4 = 4 ; UART I/O Data Register bit 4
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.equ UDR5 = 5 ; UART I/O Data Register bit 5
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.equ UDR6 = 6 ; UART I/O Data Register bit 6
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.equ UDR7 = 7 ; UART I/O Data Register bit 7
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; UCSRA - UART Control and Status register A
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.equ MPCM = 0 ; Mulit-processor Communication Mode
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.equ DOR = 3 ; Data overRun
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.equ FE = 4 ; Framing Error
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.equ UDRE = 5 ; UART Data Register Empty
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.equ TXC = 6 ; UART Transmitt Complete
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.equ RXC = 7 ; UART Receive Complete
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; UCSRB - UART Control an Status register B
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.equ TXB8 = 0 ; Transmit Data Bit 8
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.equ RXB8 = 1 ; Receive Data Bit 8
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.equ CHR9 = 2 ; 9-bit Characters
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.equ TXEN = 3 ; Transmitter Enable
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.equ RXEN = 4 ; Receiver Enable
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.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
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.equ TXCIE = 6 ; TX Complete Interrupt Enable
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.equ RXCIE = 7 ; RX Complete Interrupt Enable
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; UBRRHI - UART Baud Rate Register High Byte
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.equ UBRRHI0 = 0 ; UART Baud Rate Register High Byte bit 0
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.equ UBRRHI1 = 1 ; UART Baud Rate Register High Byte bit 1
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.equ UBRRHI2 = 2 ; UART Baud Rate Register High Byte bit 2
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.equ UBRRHI3 = 3 ; UART Baud Rate Register High Byte bit 3
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; UBRR - UART Baud Rate Register
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.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
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.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
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.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
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.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
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.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
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.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
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.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
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.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
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; ***** SPI **************************
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; SPDR - SPI Data Register
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.equ SPDR0 = 0 ; SPI Data Register bit 0
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.equ SPDR1 = 1 ; SPI Data Register bit 1
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.equ SPDR2 = 2 ; SPI Data Register bit 2
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.equ SPDR3 = 3 ; SPI Data Register bit 3
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.equ SPDR4 = 4 ; SPI Data Register bit 4
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.equ SPDR5 = 5 ; SPI Data Register bit 5
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.equ SPDR6 = 6 ; SPI Data Register bit 6
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.equ SPDR7 = 7 ; SPI Data Register bit 7
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; SPSR - SPI Status Register
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.equ WCOL = 6 ; Write Collision Flag
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.equ SPIF = 7 ; SPI Interrupt Flag
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; SPCR - SPI Control Register
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.equ SPR0 = 0 ; SPI Clock Rate Select 0
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.equ SPR1 = 1 ; SPI Clock Rate Select 1
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.equ CPHA = 2 ; Clock Phase
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.equ CPOL = 3 ; Clock polarity
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.equ MSTR = 4 ; Master/Slave Select
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.equ DORD = 5 ; Data Order
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.equ SPE = 6 ; SPI Enable
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.equ SPIE = 7 ; SPI Interrupt Enable
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; SP - Stack Pointer
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.equ SP0 = 0 ; Stack pointer bit 0
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.equ SP1 = 1 ; Stack pointer bit 1
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.equ SP2 = 2 ; Stack pointer bit 2
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.equ SP3 = 3 ; Stack pointer bit 3
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.equ SP4 = 4 ; Stack pointer bit 4
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.equ SP5 = 5 ; Stack pointer bit 5
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.equ SP6 = 6 ; Stack pointer bit 6
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.equ SP7 = 7 ; Stack pointer bit 7
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; MCUCR - MCU Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
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.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
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.equ SM = 4 ; Sleep Mode Select
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.equ SE = 5 ; Sleep Enable
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; MCUSR -
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.equ PORF = 0 ; Power-on Reset Flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ BORF = 2 ; Brown-Out Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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; ***** EXTERNAL_INTERRUPT ***********
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; GIMSK - General Interrupt Mask Register
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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.equ INT1 = 7 ; External Interrupt Request 1 Enable
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; GIFR - General Interrupt Flag register
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.equ INTF0 = 6 ; External Interrupt Flag 0
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.equ INTF1 = 7 ; External Interrupt Flag 1
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; ***** EEPROM ***********************
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; EEAR - EEPROM Read/Write Access
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.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
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.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEWE = 1 ; EEPROM Write Enable
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.equ EEMWE = 2 ; EEPROM Master Write Enable
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.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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; ***** PORTB ************************
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; PORTB - Data Register, Port B
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.equ PORTB0 = 0 ;
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ;
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ;
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ;
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ;
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ;
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.equ PB5 = 5 ; For compatibility
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; DDRB - Data Direction Register, Port B
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.equ DDB0 = 0 ;
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.equ DDB1 = 1 ;
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.equ DDB2 = 2 ;
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.equ DDB3 = 3 ;
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.equ DDB4 = 4 ;
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.equ DDB5 = 5 ;
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; PINB - Input Pins, Port B
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.equ PINB0 = 0 ;
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.equ PINB1 = 1 ;
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.equ PINB2 = 2 ;
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.equ PINB3 = 3 ;
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.equ PINB4 = 4 ;
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.equ PINB5 = 5 ;
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; ***** PORTC ************************
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; PORTC - Port C Data Register
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.equ PORTC0 = 0 ; Port C Data Register bit 0
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.equ PC0 = 0 ; For compatibility
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.equ PORTC1 = 1 ; Port C Data Register bit 1
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.equ PC1 = 1 ; For compatibility
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.equ PORTC2 = 2 ; Port C Data Register bit 2
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.equ PC2 = 2 ; For compatibility
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.equ PORTC3 = 3 ; Port C Data Register bit 3
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.equ PC3 = 3 ; For compatibility
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.equ PORTC4 = 4 ; Port C Data Register bit 4
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.equ PC4 = 4 ; For compatibility
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.equ PORTC5 = 5 ; Port C Data Register bit 5
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||
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.equ PC5 = 5 ; For compatibility
|
||
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||
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|
; DDRC - Port C Data Direction Register
|
||
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|
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
||
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|
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
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||
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|
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
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||
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|
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
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||
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|
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
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||
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|
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
||
|
|
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||
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|
; PINC - Port C Input Pins
|
||
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|
.equ PINC0 = 0 ; Port C Input Pins bit 0
|
||
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|
.equ PINC1 = 1 ; Port C Input Pins bit 1
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||
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|
.equ PINC2 = 2 ; Port C Input Pins bit 2
|
||
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|
.equ PINC3 = 3 ; Port C Input Pins bit 3
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||
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.equ PINC4 = 4 ; Port C Input Pins bit 4
|
||
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|
.equ PINC5 = 5 ; Port C Input Pins bit 5
|
||
|
|
|
||
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|
|
||
|
|
; ***** PORTD ************************
|
||
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|
; PORTD - Port D Data Register
|
||
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|
.equ PORTD0 = 0 ; Port D Data Register bit 0
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||
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|
.equ PD0 = 0 ; For compatibility
|
||
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.equ PORTD1 = 1 ; Port D Data Register bit 1
|
||
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.equ PD1 = 1 ; For compatibility
|
||
|
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.equ PORTD2 = 2 ; Port D Data Register bit 2
|
||
|
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.equ PD2 = 2 ; For compatibility
|
||
|
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.equ PORTD3 = 3 ; Port D Data Register bit 3
|
||
|
|
.equ PD3 = 3 ; For compatibility
|
||
|
|
.equ PORTD4 = 4 ; Port D Data Register bit 4
|
||
|
|
.equ PD4 = 4 ; For compatibility
|
||
|
|
.equ PORTD5 = 5 ; Port D Data Register bit 5
|
||
|
|
.equ PD5 = 5 ; For compatibility
|
||
|
|
.equ PORTD6 = 6 ; Port D Data Register bit 6
|
||
|
|
.equ PD6 = 6 ; For compatibility
|
||
|
|
.equ PORTD7 = 7 ; Port D Data Register bit 7
|
||
|
|
.equ PD7 = 7 ; For compatibility
|
||
|
|
|
||
|
|
; DDRD - Port D Data Direction Register
|
||
|
|
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
|
||
|
|
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
|
||
|
|
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
|
||
|
|
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
|
||
|
|
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
|
||
|
|
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
|
||
|
|
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
|
||
|
|
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
|
||
|
|
|
||
|
|
; PIND - Port D Input Pins
|
||
|
|
.equ PIND0 = 0 ; Port D Input Pins bit 0
|
||
|
|
.equ PIND1 = 1 ; Port D Input Pins bit 1
|
||
|
|
.equ PIND2 = 2 ; Port D Input Pins bit 2
|
||
|
|
.equ PIND3 = 3 ; Port D Input Pins bit 3
|
||
|
|
.equ PIND4 = 4 ; Port D Input Pins bit 4
|
||
|
|
.equ PIND5 = 5 ; Port D Input Pins bit 5
|
||
|
|
.equ PIND6 = 6 ; Port D Input Pins bit 6
|
||
|
|
.equ PIND7 = 7 ; Port D Input Pins bit 7
|
||
|
|
|
||
|
|
|
||
|
|
; ***** TIMER_COUNTER_0 **************
|
||
|
|
; TIMSK - Timer/Counter Interrupt Mask Register
|
||
|
|
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
||
|
|
|
||
|
|
; TIFR - Timer/Counter Interrupt Flag register
|
||
|
|
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
||
|
|
|
||
|
|
; TCCR0 - Timer/Counter0 Control Register
|
||
|
|
.equ CS00 = 0 ; Clock Select0 bit 0
|
||
|
|
.equ CS01 = 1 ; Clock Select0 bit 1
|
||
|
|
.equ CS02 = 2 ; Clock Select0 bit 2
|
||
|
|
|
||
|
|
; TCNT0 - Timer Counter 0
|
||
|
|
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
|
||
|
|
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
|
||
|
|
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
|
||
|
|
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
|
||
|
|
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
|
||
|
|
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
|
||
|
|
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
|
||
|
|
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
|
||
|
|
|
||
|
|
|
||
|
|
; ***** TIMER_COUNTER_1 **************
|
||
|
|
; TIMSK - Timer/Counter Interrupt Mask Register
|
||
|
|
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
|
||
|
|
.equ OCIE1 = 6 ; Timer/Counter1 Output Compare Match Interrupt Enable
|
||
|
|
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
|
||
|
|
|
||
|
|
; TIFR - Timer/Counter Interrupt Flag register
|
||
|
|
.equ ICF1 = 3 ; Input Capture Flag 1
|
||
|
|
.equ OCF1 = 6 ; Output Compare Flag 1
|
||
|
|
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
|
||
|
|
|
||
|
|
; TCCR1A - Timer/Counter1 Control Register A
|
||
|
|
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
|
||
|
|
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
|
||
|
|
.equ COM10 = 6 ; Compare Ouput Mode 1, bit 0
|
||
|
|
.equ COM11 = 7 ; Compare Output Mode 1, bit 1
|
||
|
|
|
||
|
|
; TCCR1B - Timer/Counter1 Control Register B
|
||
|
|
.equ CS10 = 0 ; Clock Select1 bit 0
|
||
|
|
.equ CS11 = 1 ; Clock Select1 bit 1
|
||
|
|
.equ CS12 = 2 ; Clock Select1 bit 2
|
||
|
|
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
|
||
|
|
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||
|
|
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||
|
|
|
||
|
|
|
||
|
|
; ***** WATCHDOG *********************
|
||
|
|
; WDTCR - Watchdog Timer Control Register
|
||
|
|
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||
|
|
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||
|
|
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||
|
|
.equ WDE = 3 ; Watch Dog Enable
|
||
|
|
.equ WDTOE = 4 ; RW
|
||
|
|
.equ WDDE = WDTOE ; For compatibility
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** LOCKSBITS ********************************************************
|
||
|
|
.equ LB1 = 0 ; Lockbit
|
||
|
|
.equ LB2 = 1 ; Lockbit
|
||
|
|
|
||
|
|
|
||
|
|
; ***** FUSES ************************************************************
|
||
|
|
; LOW fuse bits
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||
|
|
.def XH = r27
|
||
|
|
.def XL = r26
|
||
|
|
.def YH = r29
|
||
|
|
.def YL = r28
|
||
|
|
.def ZH = r31
|
||
|
|
.def ZL = r30
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||
|
|
.equ FLASHEND = 0x07ff ; Note: Word address
|
||
|
|
.equ IOEND = 0x003f
|
||
|
|
.equ SRAM_START = 0x0060
|
||
|
|
.equ SRAM_SIZE = 128
|
||
|
|
.equ RAMEND = 0x00df
|
||
|
|
.equ XRAMEND = 0x0000
|
||
|
|
.equ E2END = 0x00ff
|
||
|
|
.equ EEPROMEND = 0x00ff
|
||
|
|
.equ EEADRBITS = 8
|
||
|
|
#pragma AVRPART MEMORY PROG_FLASH 4096
|
||
|
|
#pragma AVRPART MEMORY EEPROM 256
|
||
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
||
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** INTERRUPT VECTORS ************************************************
|
||
|
|
.equ INT0addr = 0x0001 ; External Interrupt 0
|
||
|
|
.equ INT1addr = 0x0002 ; External Interrupt 1
|
||
|
|
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event
|
||
|
|
.equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match
|
||
|
|
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
||
|
|
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
||
|
|
.equ SPIaddr = 0x0007 ; Serial Transfer Complete
|
||
|
|
.equ URXCaddr = 0x0008 ; UART, Rx Complete
|
||
|
|
.equ UDREaddr = 0x0009 ; UART Data Register Empty
|
||
|
|
.equ UTXCaddr = 0x000a ; UART, Tx Complete
|
||
|
|
.equ ADCCaddr = 0x000b ; ADC Conversion Complete
|
||
|
|
.equ ERDYaddr = 0x000c ; EEPROM Ready
|
||
|
|
.equ ACIaddr = 0x000d ; Analog Comparator
|
||
|
|
|
||
|
|
.equ INT_VECTORS_SIZE = 14 ; size in words
|
||
|
|
|
||
|
|
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
||
|
|
|
||
|
|
#endif /* _4433DEF_INC_ */
|
||
|
|
|
||
|
|
; ***** END OF FILE ******************************************************
|