2014-01-23 18:47:35 +01:00
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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struct PCI_header
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2014-08-29 17:09:56 +02:00
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vendor_id dw ? ; 0x00
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device_id dw ? ; 0x02
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command dw ? ; 0x04
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status dw ? ; 0x06
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revision_id db ? ; 0x08
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prog_if db ? ; 0x09
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subclass db ? ; 0x0A
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class_code db ? ; 0x0B
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cache_line_size db ? ; 0x0C
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latency_timer db ? ; 0x0D
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header_type db ? ; 0x0E
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bist db ? ; 0x0F
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2014-01-23 18:47:35 +01:00
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ends
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struct PCI_header00 PCI_header
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2014-08-29 17:09:56 +02:00
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base_addr_0 dd ? ; 0x10
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base_addr_1 dd ? ; 0x14
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base_addr_2 dd ? ; 0x18
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base_addr_3 dd ? ; 0x1C
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base_addr_4 dd ? ; 0x20
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base_addr_5 dd ? ; 0x24
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cardbus_cis_ptr dd ? ; 0x28
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subsys_vendor dw ? ; 0x2C
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subsys_id dw ? ; 0x2E
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exp_rom_addr dd ? ; 0x30
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cap_ptr db ? ; 0x34
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rb 7 ; reserved
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interrupt_line db ? ; 0x3C
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interrupt_pin db ? ; 0x3D
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min_grant db ? ; 0x3E
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max_latency db ? ; 0x3F
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ends
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struct PCI_header01 PCI_header
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base_addr_0 dd ? ; 0x10
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base_addr_1 dd ? ; 0x14
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prim_bus_nr db ? ; 0x18
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sec_bus_nr db ? ; 0x19
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sub_bus_nr db ? ; 0x1A
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sec_lat_tmr db ? ; 0x1B
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io_base db ? ; 0x1C
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io_limit db ? ; 0x1D
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sec_status dw ? ; 0x1E
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mem_base dw ? ; 0x20
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mem_limit dw ? ; 0x22
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pref_mem_base dw ? ; 0x24
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pref_mem_limit dw ? ; 0x26
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pref_base_up dd ? ; 0x28
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pref_limit_up dd ? ; 0x2C
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io_base_up dw ? ; 0x30
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io_limit_up dw ? ; 0x32
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cap_ptr db ? ; 0x34
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rb 3 ; reserved
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exp_rom_addr dd ? ; 0x38
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interrupt_line db ? ; 0x3C
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interrupt_pin db ? ; 0x3E
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bridge_ctrl dw ? ; 0x3F
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ends
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struct PCI_header02 PCI_header
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base_addr dd ? ; 0x10
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cap_list_offs db ? ; 0x14
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rb 1 ; reserved
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sec_stat dw ? ; 0x16
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pci_bus_nr db ? ; 0x18
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cardbus_bus_nr db ? ; 0x19
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sub_bus_nr db ? ; 0x1A
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cardbus_lat_tmr db ? ; 0x1B
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mbar_0 dd ? ; 0x1C
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mlimit_0 dd ? ; 0x20
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mbar_1 dd ? ; 0x24
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mlimit_1 dd ? ; 0x28
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iobar_0 dd ? ; 0x2C
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iolimit_0 dd ? ; 0x30
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iobar_1 dd ? ; 0x34
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iolimit_1 dd ? ; 0x38
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interrupt_line db ? ; 0x3C
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interrupt_pin db ? ; 0x3D
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bridge_ctrl dw ? ; 0x3E
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subs_did dw ? ; 0x40
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subs_vid dw ? ; 0x42
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legacy_bar dd ? ; 0x44
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2014-01-23 18:47:35 +01:00
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ends
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; Base address bits
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PCI_BASE_ADDRESS_SPACE_IO = 0x01
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PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
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PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0
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; command bits
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PCI_CMD_PIO = 1 ; bit0: io space control
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PCI_CMD_MMIO = 2 ; bit1: memory space control
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PCI_CMD_MASTER = 4 ; bit2: device acts as a PCI master
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if used PCI_find_io
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proc PCI_find_io stdcall bus, dev
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push esi
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xor eax, eax
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2014-01-26 20:50:44 +01:00
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mov esi, PCI_header00.base_addr_0
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2014-01-23 18:47:35 +01:00
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.check:
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invoke PciRead32, [bus], [dev], esi
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test eax, PCI_BASE_ADDRESS_IO_MASK
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jz .inc
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test eax, PCI_BASE_ADDRESS_SPACE_IO
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jz .inc
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and eax, PCI_BASE_ADDRESS_IO_MASK
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pop esi
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ret
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.inc:
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add esi, 4
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2014-01-26 20:50:44 +01:00
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cmp esi, PCI_header00.base_addr_5
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2014-01-23 18:47:35 +01:00
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jbe .check
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pop esi
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xor eax, eax
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ret
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endp
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end if
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if used PCI_find_mmio32
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proc PCI_find_mmio32 stdcall bus, dev
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push esi
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mov esi, PCI_header00.base_addr_0
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.check:
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invoke PciRead32, [bus], [dev], esi
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test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address?
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jnz .inc
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test eax, 100b ; 64 bit?
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jnz .inc
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and eax, not 1111b
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pop esi
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ret
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.inc:
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add esi, 4
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cmp esi, PCI_header00.base_addr_5
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jbe .check
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xor eax, eax
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pop esi
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ret
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endp
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end if
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