drm: 3.17-rc5

git-svn-id: svn://kolibrios.org@5128 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge) 2014-09-17 10:10:28 +00:00
parent 1415fa22e9
commit 347bbd1570
10 changed files with 94 additions and 50 deletions

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@ -1182,12 +1182,17 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_power_domains_init_hw(dev_priv); intel_power_domains_init_hw(dev_priv);
/*
* We enable some interrupt sources in our postinstall hooks, so mark
* interrupts as enabled _before_ actually enabling them to avoid
* special cases in our ordering checks.
*/
dev_priv->pm._irqs_disabled = false;
ret = drm_irq_install(dev, dev->pdev->irq); ret = drm_irq_install(dev, dev->pdev->irq);
if (ret) if (ret)
goto cleanup_gem_stolen; goto cleanup_gem_stolen;
dev_priv->pm._irqs_disabled = false;
/* Important: The output setup functions called by modeset_init need /* Important: The output setup functions called by modeset_init need
* working irqs for e.g. gmbus and dp aux transfers. */ * working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev); intel_modeset_init(dev);

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@ -195,6 +195,7 @@ enum hpd_pin {
if ((1 << (domain)) & (mask)) if ((1 << (domain)) & (mask))
struct drm_i915_private; struct drm_i915_private;
struct i915_mm_struct;
struct i915_mmu_object; struct i915_mmu_object;
enum intel_dpll_id { enum intel_dpll_id {
@ -1511,9 +1512,8 @@ struct drm_i915_private {
struct i915_gtt gtt; /* VM representing the global address space */ struct i915_gtt gtt; /* VM representing the global address space */
struct i915_gem_mm mm; struct i915_gem_mm mm;
#if defined(CONFIG_MMU_NOTIFIER) DECLARE_HASHTABLE(mm_structs, 7);
DECLARE_HASHTABLE(mmu_notifiers, 7); struct mutex mm_lock;
#endif
/* Kernel Modesetting */ /* Kernel Modesetting */
@ -1819,8 +1819,8 @@ struct drm_i915_gem_object {
unsigned workers :4; unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15 #define I915_GEM_USERPTR_MAX_WORKERS 15
struct mm_struct *mm; struct i915_mm_struct *mm;
struct i915_mmu_object *mn; struct i915_mmu_object *mmu_object;
struct work_struct *work; struct work_struct *work;
} userptr; } userptr;
}; };

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@ -334,16 +334,20 @@
#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define BLT_WRITE_A (2<<20)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) #define BLT_WRITE_RGB (1<<20)
#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
#define BLT_DEPTH_8 (0<<24) #define BLT_DEPTH_8 (0<<24)
#define BLT_DEPTH_16_565 (1<<24) #define BLT_DEPTH_16_565 (1<<24)
#define BLT_DEPTH_16_1555 (2<<24) #define BLT_DEPTH_16_1555 (2<<24)
#define BLT_DEPTH_32 (3<<24) #define BLT_DEPTH_32 (3<<24)
#define BLT_ROP_GXCOPY (0xcc<<16) #define BLT_ROP_SRC_COPY (0xcc<<16)
#define BLT_ROP_COLOR_COPY (0xf0<<16)
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)

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@ -675,6 +675,13 @@ static int init_render_ring(struct intel_engine_cs *ring)
static void render_ring_cleanup(struct intel_engine_cs *ring) static void render_ring_cleanup(struct intel_engine_cs *ring)
{ {
struct drm_device *dev = ring->dev; struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
if (dev_priv->semaphore_obj) {
i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
dev_priv->semaphore_obj = NULL;
}
if (ring->scratch.obj == NULL) if (ring->scratch.obj == NULL)
return; return;
@ -1353,14 +1360,56 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
/* Just userspace ABI convention to limit the wa batch bo to a resonable size */ /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
#define I830_BATCH_LIMIT (256*1024) #define I830_BATCH_LIMIT (256*1024)
#define I830_TLB_ENTRIES (2)
#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
static int static int
i830_dispatch_execbuffer(struct intel_engine_cs *ring, i830_dispatch_execbuffer(struct intel_engine_cs *ring,
u64 offset, u32 len, u64 offset, u32 len,
unsigned flags) unsigned flags)
{ {
u32 cs_offset = ring->scratch.gtt_offset;
int ret; int ret;
if (flags & I915_DISPATCH_PINNED) { ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
/* Evict the invalid PTE TLBs */
intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
intel_ring_emit(ring, cs_offset);
intel_ring_emit(ring, 0xdeadbeef);
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
if ((flags & I915_DISPATCH_PINNED) == 0) {
if (len > I830_BATCH_LIMIT)
return -ENOSPC;
ret = intel_ring_begin(ring, 6 + 2);
if (ret)
return ret;
/* Blit the batch (which has now all relocs applied) to the
* stable batch scratch bo area (so that the CS never
* stumbles over its tlb invalidation bug) ...
*/
intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024);
intel_ring_emit(ring, cs_offset);
intel_ring_emit(ring, 4096);
intel_ring_emit(ring, offset);
intel_ring_emit(ring, MI_FLUSH);
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
/* ... and execute it. */
offset = cs_offset;
}
ret = intel_ring_begin(ring, 4); ret = intel_ring_begin(ring, 4);
if (ret) if (ret)
return ret; return ret;
@ -1370,36 +1419,6 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
intel_ring_emit(ring, offset + len - 8); intel_ring_emit(ring, offset + len - 8);
intel_ring_emit(ring, MI_NOOP); intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring); intel_ring_advance(ring);
} else {
u32 cs_offset = ring->scratch.gtt_offset;
if (len > I830_BATCH_LIMIT)
return -ENOSPC;
ret = intel_ring_begin(ring, 9+3);
if (ret)
return ret;
/* Blit the batch (which has now all relocs applied) to the stable batch
* scratch bo area (so that the CS never stumbles over its tlb
* invalidation bug) ... */
intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
intel_ring_emit(ring, cs_offset);
intel_ring_emit(ring, 0);
intel_ring_emit(ring, 4096);
intel_ring_emit(ring, offset);
intel_ring_emit(ring, MI_FLUSH);
/* ... and execute it. */
intel_ring_emit(ring, MI_BATCH_BUFFER);
intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
intel_ring_emit(ring, cs_offset + len - 8);
intel_ring_advance(ring);
}
return 0; return 0;
} }
@ -2179,7 +2198,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
/* Workaround batchbuffer to combat CS tlb bug. */ /* Workaround batchbuffer to combat CS tlb bug. */
if (HAS_BROKEN_CS_TLB(dev)) { if (HAS_BROKEN_CS_TLB(dev)) {
obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT); obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
if (obj == NULL) { if (obj == NULL) {
DRM_ERROR("Failed to allocate batch bo\n"); DRM_ERROR("Failed to allocate batch bo\n");
return -ENOMEM; return -ENOMEM;

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@ -186,7 +186,7 @@ u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
if( GetService("DISPLAY") != 0 ) if( GetService("DISPLAY") != 0 )
return 0; return 0;
printf("\ni915 v3.17-rc3 build %s %s\nusage: i915 [options]\n" printf("\ni915 v3.17-rc5 build %s %s\nusage: i915 [options]\n"
"-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n", "-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n",
__DATE__, __TIME__); __DATE__, __TIME__);
printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n" printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n"

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@ -405,16 +405,13 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
u8 msg[DP_DPCD_SIZE]; u8 msg[DP_DPCD_SIZE];
int ret; int ret;
char dpcd_hex_dump[DP_DPCD_SIZE * 3];
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
DP_DPCD_SIZE); DP_DPCD_SIZE);
if (ret > 0) { if (ret > 0) {
memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd), DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); dig_connector->dpcd);
DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
radeon_dp_probe_oui(radeon_connector); radeon_dp_probe_oui(radeon_connector);

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@ -134,7 +134,7 @@ u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
if( GetService("DISPLAY") != 0 ) if( GetService("DISPLAY") != 0 )
return 0; return 0;
printf("Radeon v3.17-rc3 cmdline %s\n", cmdline); printf("Radeon v3.17-rc5 cmdline %s\n", cmdline);
if( cmdline && *cmdline ) if( cmdline && *cmdline )
parse_cmdline(cmdline, &usermode, log, &radeon_modeset); parse_cmdline(cmdline, &usermode, log, &radeon_modeset);

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@ -2769,8 +2769,8 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
radeon_ring_write(ring, lower_32_bits(addr)); radeon_ring_write(ring, lower_32_bits(addr));
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
/* PFP_SYNC_ME packet only exists on 7xx+ */ /* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
if (emit_wait && (rdev->family >= CHIP_RV770)) { if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
/* Prevent the PFP from running ahead of the semaphore wait */ /* Prevent the PFP from running ahead of the semaphore wait */
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
radeon_ring_write(ring, 0x0); radeon_ring_write(ring, 0x0);

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@ -447,6 +447,13 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
} }
} }
/* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
if ((dev->pdev->device == 0x9805) &&
(dev->pdev->subsystem_vendor == 0x1734) &&
(dev->pdev->subsystem_device == 0x11bd)) {
if (*connector_type == DRM_MODE_CONNECTOR_VGA)
return false;
}
return true; return true;
} }
@ -2281,19 +2288,31 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
(controller->ucFanParameters & (controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
rdev->pm.int_thermal_type = THERMAL_TYPE_KV; rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
} else if ((controller->ucType == } else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
(controller->ucType == DRM_INFO("External GPIO thermal controller %s fan control\n",
ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || (controller->ucFanParameters &
(controller->ucType == ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
DRM_INFO("Special thermal controller config\n"); } else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
} else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
pp_lib_thermal_controller_names[controller->ucType], pp_lib_thermal_controller_names[controller->ucType],
controller->ucI2cAddress >> 1, controller->ucI2cAddress >> 1,
(controller->ucFanParameters & (controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
if (rdev->pm.i2c_bus) { if (rdev->pm.i2c_bus) {

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@ -34,7 +34,7 @@
int radeon_semaphore_create(struct radeon_device *rdev, int radeon_semaphore_create(struct radeon_device *rdev,
struct radeon_semaphore **semaphore) struct radeon_semaphore **semaphore)
{ {
uint32_t *cpu_addr; uint64_t *cpu_addr;
int i, r; int i, r;
*semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL); *semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL);