From 68230a94d8d2d0c4b697c6d9fc2db1f1d3fc26f3 Mon Sep 17 00:00:00 2001
From: hidnplayr <hidnplayr@kolibrios.org>
Date: Thu, 9 Aug 2012 20:27:09 +0000
Subject: [PATCH] Fixed bug in RTL8169 driver

git-svn-id: svn://kolibrios.org@2918 a494cfbc-eb01-0410-851d-a64ba20cac60
---
 kernel/branches/net/drivers/RTL8169.asm | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/kernel/branches/net/drivers/RTL8169.asm b/kernel/branches/net/drivers/RTL8169.asm
index fcd73c3ae6..381d0fbae3 100644
--- a/kernel/branches/net/drivers/RTL8169.asm
+++ b/kernel/branches/net/drivers/RTL8169.asm
@@ -305,7 +305,7 @@ macro   WRITE_GMII_REG  RegAddr, value {
         end if
         out     dx, eax
 
-        call    PHY_WAIT
+        call    PHY_WAIT_WRITE
 }
 
 macro   READ_GMII_REG  RegAddr {
@@ -316,7 +316,7 @@ local   .error, .done
         mov     eax, RegAddr shl 16
         out     dx, eax
 
-        call    PHY_WAIT
+        call    PHY_WAIT_READ
         jz      .error
 
         in      eax, dx
@@ -329,7 +329,25 @@ local   .error, .done
 }
 
 align 4
-PHY_WAIT:       ; io addr must already be set to REG_PHYAR
+PHY_WAIT_READ:       ; io addr must already be set to REG_PHYAR
+
+        udelay  1        ;;;1000
+
+        push    ecx
+        mov     ecx, 2000
+        ; Check if the RTL8169 has completed writing/reading to the specified MII register
+    @@:
+        in      eax, dx
+        test    eax, 0x80000000
+        jnz     .exit
+        udelay  1        ;;;100
+        loop    @b
+  .exit:
+        pop     ecx
+        ret
+
+align 4
+PHY_WAIT_WRITE:       ; io addr must already be set to REG_PHYAR
 
         udelay  1        ;;;1000