forked from KolibriOS/kolibrios
PCIe config bugs fixed
git-svn-id: svn://kolibrios.org@1560 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Artem Jerdev (art_zh)
parent
08ea0b5f68
commit
849a203279
@ -11,15 +11,16 @@
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision: 1554 $
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align 4
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;=============================================================================
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;
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; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
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;
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;=============================================================================
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align 4
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;------------------------------------------
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; params: al = nbconfig register#
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@ -33,6 +34,7 @@ rs7xx_nbconfig_read_pci:
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add dl, 4
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in eax, dx
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ret
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align 4
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rs7xx_nbconfig_flush_pci:
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mov eax, 0x0B0 ; a scratch reg
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@ -40,6 +42,7 @@ rs7xx_nbconfig_flush_pci:
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out dx, eax
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ret
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align 4
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rs7xx_nbconfig_write_pci:
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and eax, 0x0FC ; leave register# only
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@ -60,10 +63,9 @@ rs7xx_nbconfig_write_pci:
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;
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;***************************************************************************
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align 4
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rs7xx_pcie_init:
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; mov al, 0x7C ; NB_IOC_CFG_CNTL
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; mov ebx, 0x20000000
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; call rs7xx_nbconfig_write_pci
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mov al, 0x7C ; NB_IOC_CFG_CNTL
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call rs7xx_nbconfig_read_pci
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mov ebx, eax
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@ -98,47 +100,50 @@ rs7xx_pcie_init:
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call rs7xx_nbconfig_flush_pci
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mov eax, ebx
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and eax, 0xFFE00000 ; valid bits [31..21]
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jnz @f ; NB BAR3 may be invisible!
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call pci_ext_config ; try to get pcie ecfg address indirectly
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@@:
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or eax, eax
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jz .rs7xx_pcie_fail
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jz .rs7xx_pcie_blocked ; NB BAR3 may be invisible!
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; try to get pcie ecfg address indirectly
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.addr_found:
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mov [mmio_pcie_cfg_addr], eax ; physical address (lower 32 bits)
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add [mmio_pcie_cfg_lim], eax
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; -- map the whole PCIe config space;
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or eax, (PG_SHARED + PG_LARGE + PG_UW) ; by the way, UW is unsafe!
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mov ecx, PCIe_CONFIG_SPACE ; linear address
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mov ebx, ecx
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shr ebx, 20
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add ebx, sys_pgdir ; PgDir entry @
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xor dx, dx ; PDEs counter
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mov dl, byte[mmio_pcie_cfg_pdes] ; 1 page = 4M in address space
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cmp dl, (USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304
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jb @f
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mov dl, ((USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304) - 1
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mov byte[mmio_pcie_cfg_pdes], dl
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@@:
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mov dword[ebx], eax ; map 4 buses
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xor dx, dx ; PDEs counter
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@@:
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mov dword[ebx], eax ; map 4 buses
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invlpg [ecx] ; next PgDir entry
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add bx, 4 ; new PDE
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add eax, 0x400000 ; +4M phys.
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add ecx, 0x400000 ; +4M lin.
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inc dx
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cmp dx, [mmio_pcie_cfg_pdes] ; all mapped yet?
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jnz @b
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cmp dl, byte[mmio_pcie_cfg_pdes]
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jnc .pcie_cfg_mapped
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inc dl
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jmp @b
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.pcie_cfg_mapped:
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mov esi, boot_pcie_ok
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call boot_log
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ret ; <<<<<<<<<<< OK >>>>>>>>>>>
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ret ; <<< OK >>>
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.rs7xx_pcie_fail:
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mov esi, boot_rs7xx_fail
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call boot_log
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ret
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.rs7xx_pcie_blocked:
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mov esi, boot_rs7xx_blkd
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call boot_log
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call pci_ext_config
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jmp .addr_found
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ret
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@ -8,11 +8,11 @@
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;; ;;
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;; Extended PCI express services ;;
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;; ;;
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;; art_zh <artem@jerdev.co.uk> ;;
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;; art_zh <artem@jerdev.co.uk> ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision: 1463 $
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$Revision: 1554 $
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;***************************************************************************
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; Function
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@ -22,30 +22,31 @@ $Revision: 1463 $
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; PCIe extended (memory-mapped) config space detection
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;
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; WARNINGs:
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; 1) Very Experimental!
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; 2) direct HT-detection (no ACPI or BIOS service used)
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; 3) Only AMD/HT processors currently supported
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; 1) Very Experimental!
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; 2) direct HT-detection (no ACPI or BIOS service used)
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; 3) Only AMD/HT processors currently supported
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;
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;***************************************************************************
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align 4
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mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here
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mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here
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mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address
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mmio_pcie_cfg_pdes dw 0 ; number of PDEs to map the space
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PCIe_bus_range dw 0 ; the Bus range: power-of-2 Megabytes
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mmio_pcie_cfg_pdes dw 1 ; number of PDEs to map the space
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PCIe_bus_range dw 2 ; the Bus range: power-of-2 Megabytes
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align 4
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pci_ext_config:
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mov ebx, [mmio_pcie_cfg_addr]
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or ebx,ebx
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mov eax, [mmio_pcie_cfg_addr]
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mov ebx, eax
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or ebx, ebx
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jz @f
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or ebx, 0x7FFFFFFF ; required by PCI-SIG standards
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or ebx, 0x7FFFFFFF ; required by PCI-SIG standards
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jnz .pcie_failed
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add ebx, 0x0FFFFC
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cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct?
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ja .pcie_failed
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jmp .pcie_cfg_mapped
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ret ; return the address forced
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@@:
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mov ebx, [cpu_vendor]
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cmp ebx, dword [AMD_str]
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@ -55,17 +56,17 @@ pci_ext_config:
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.check_HT_mmio:
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mov cx, bx
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mov ax, 0x0002 ; bus = 0, 1dword to read
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call pci_read_reg
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call pci_read_reg
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mov bx, cx
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sub bl, 4
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and al, 0x80 ; check the NP bit
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and al, 0x80 ; check the NP bit
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jz .no_pcie_cfg
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shl eax, 8 ; bus:[27..20], dev:[19:15]
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or eax, 0x00007FFC ; fun:[14..12], reg:[11:2]
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; mov [mmio_pcie_cfg_lim], eax
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or eax, 0x00007FFC ; fun:[14..12], reg:[11:2]
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; mov [mmio_pcie_cfg_lim], eax
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mov cl, bl
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mov ax, 0x0002 ; bus = 0, 1dword to read
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call pci_read_reg
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call pci_read_reg
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mov bx, cx
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test al, 0x03 ; MMIO Base RW enabled?
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jz .no_pcie_cfg
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@ -73,29 +74,21 @@ pci_ext_config:
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jnz .no_pcie_cfg
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xor al, al
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shl eax, 8
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test eax, 0x000F0000 ; MMIO Base must be bus0-aligned
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test eax, 0x000F0000 ; MMIO Base must be bus0-aligned
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jnz .no_pcie_cfg
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mov [mmio_pcie_cfg_addr], eax
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; add eax, 0x000FFFFC
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; sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus
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; ja .no_pcie_cfg
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; -- it looks like a true PCIe config space;
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; -- it looks like a true PCIe config space;
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.pcie_cfg_mapped:
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mov esi, boot_pcie_ok
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call boot_log
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ret ; <<<<<<<<<<< OK >>>>>>>>>>>
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.no_pcie_cfg:
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xor eax, eax
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mov [mmio_pcie_cfg_addr], eax
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mov [mmio_pcie_cfg_lim], eax
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add bl, 12
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cmp bl, 0xC0 ; MMIO regs lay below this offset
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jb .check_HT_mmio
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.pcie_failed:
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mov esi, boot_pcie_fail
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call boot_log
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@ -128,10 +128,6 @@ pci_make_config_cmd:
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align 4
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pci_read_reg:
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cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
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je pci_read_reg_2
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; mechanism 1
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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@ -174,66 +170,6 @@ pci_fin_read1:
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mov dx,0xcf8
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out dx,eax
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pop eax
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pop esi
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ret
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pci_read_reg_2:
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test bh,128 ;mech#2 only supports 16 devices per bus
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jnz pci_read_reg_err
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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push eax
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;store current state of config space
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mov dx,0xcf8
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in al,dx
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mov ah,al
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mov dl,0xfa
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in al,dx
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xchg eax,[esp]
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; out 0xcfa,bus
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mov al,ah
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out dx,al
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; out 0xcf8,0x80
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mov dl,0xf8
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mov al,0x80
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out dx,al
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; compute addr
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shr bh,3 ; func is ignored in mechanism 2
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or bh,0xc0
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mov dx,bx
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or esi,esi
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jz pci_read_byte2
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cmp esi,1
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jz pci_read_word2
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cmp esi,2
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jz pci_read_dword2
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jmp pci_fin_read2
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pci_read_byte2:
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in al,dx
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jmp pci_fin_read2
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pci_read_word2:
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in ax,dx
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jmp pci_fin_read2
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pci_read_dword2:
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in eax,dx
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; jmp pci_fin_read2
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pci_fin_read2:
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; restore configuration space
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xchg eax,[esp]
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mov dx,0xcfa
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out dx,al
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mov dl,0xf8
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mov al,ah
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out dx,al
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pop eax
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pop esi
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ret
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@ -259,10 +195,6 @@ pci_read_reg_err:
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align 4
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pci_write_reg:
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cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
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je pci_write_reg_2
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; mechanism 1
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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@ -301,74 +233,11 @@ pci_write_dword1:
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out dx,eax
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jmp pci_fin_write1
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pci_fin_write1:
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; restore configuration control
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pop eax
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mov dl,0xf8
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out dx,eax
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xor eax,eax
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pop esi
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ret
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pci_write_reg_2:
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test bh,128 ;mech#2 only supports 16 devices per bus
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jnz pci_write_reg_err
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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push eax
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;store current state of config space
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mov dx,0xcf8
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in al,dx
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mov ah,al
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mov dl,0xfa
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in al,dx
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xchg eax,[esp]
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; out 0xcfa,bus
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mov al,ah
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out dx,al
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; out 0xcf8,0x80
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mov dl,0xf8
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mov al,0x80
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out dx,al
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; compute addr
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shr bh,3 ; func is ignored in mechanism 2
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or bh,0xc0
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mov dx,bx
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; write register
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mov eax,ecx
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or esi,esi
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jz pci_write_byte2
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cmp esi,1
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jz pci_write_word2
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cmp esi,2
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jz pci_write_dword2
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jmp pci_fin_write2
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pci_write_byte2:
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out dx,al
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jmp pci_fin_write2
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pci_write_word2:
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out dx,ax
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jmp pci_fin_write2
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pci_write_dword2:
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out dx,eax
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jmp pci_fin_write2
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pci_fin_write2:
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; restore configuration space
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pop eax
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mov dx,0xcfa
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out dx,al
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mov dl,0xf8
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mov al,ah
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out dx,al
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xor eax,eax
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pop esi
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ret
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@ -429,10 +298,10 @@ pci_mmio_init:
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pci_mmio_map:
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and edx,0x0ffff
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cmp ah, 0xDA
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jz .dma_map
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jz .dma_map
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cmp ah,6
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jc .bar_0_5
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jz .bar_rom
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jc .bar_0_5
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jz .bar_rom
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mov eax,-2
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ret
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@ -67,6 +67,7 @@ keymap_alt:
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; boot_pal_vga db 'Setting VGA 640x480 palette',0
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boot_failed db 'Failed to start first app',0
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boot_mtrr db 'Setting MTRR',0
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boot_uDMA_ok db 'Set user DMA OK',0
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boot_pcie_ok db 'PCIe config set OK',0
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boot_pcie_fail db 'PCIe config XXX failed XXX',0
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boot_rs7xx_fail db 'RS7xx config XXX failed XXX',0
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@ -677,9 +677,9 @@ end if
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; RESERVE SYSTEM IRQ'S JA PORT'S
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mov esi,boot_resirqports
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call boot_log
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call reserve_irqs_ports
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; mov esi,boot_resirqports
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; call boot_log
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; call reserve_irqs_ports
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; SET UP OS TASK
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@ -828,6 +828,8 @@ end if
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no_st_network:
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call init_userDMA ; <<<<<<<<< ============== core/memory.inc =================
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mov esi, boot_uDMA_ok
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call boot_log
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; call pci_ext_config ; <<<<<<<<< bus/pci/pcie.inc
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;-------------------------------------------------------------------------------
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call rs7xx_pcie_init ; <<<<<<<<< bus/ht.inc
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