diff --git a/programs/system/drivers/ati2d/accel_2d.h b/programs/system/drivers/ati2d/accel_2d.h new file mode 100644 index 0000000000..47f21a3591 --- /dev/null +++ b/programs/system/drivers/ati2d/accel_2d.h @@ -0,0 +1,95 @@ + +#define FILL_RECT 1 +#define DRAW_RECT 2 +#define LINE_2P 3 + +typedef unsigned int color_t; +typedef unsigned int u32_t; + +typedef struct +{ + int x; + int y; + int w; + int h; + u32 color; +}draw_t; + +typedef struct +{ + int x; + int y; + int w; + int h; + + color_t bkcolor; + color_t fcolor; + + u32_t bmp0; + u32_t bmp1; +}fill_t; + +typedef struct +{ + int x0; + int y0; + int x1; + int y1; + u32 color; +}line2p_t; + +int LineClip( int *x1, int *y1, int *x2, int *y2 ); +int BlockClip( int *x1, int *y1, int *x2, int* y2); + +int DrawRect(draw_t * draw); +int FillRect(fill_t * fill); + +int Line2P(line2p_t *draw); + + +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_P 0x00f00000 + +#define RADEON_CP_PACKET3 0xC0000000 + +# define RADEON_CNTL_PAINT 0x00009100 +# define RADEON_CNTL_PAINT_POLYLINE 0x00009500 +# define RADEON_CNTL_PAINT_MULTI 0x00009A00 + +#define CP_PACKET3( pkt, n ) \ + (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) + +#define BEGIN_RING( n ) do { \ + ring = rhd.ring_base; \ + write = rhd.ring_wp; \ +} while (0) + +#define OUT_RING( x ) do { \ + ring[write++] = (x); \ +} while (0) + +#define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); + +#define COMMIT_RING() do { \ + rhd.ring_wp = write & 0x1FFF; \ + /* Flush writes to ring */ \ + DRM_MEMORYBARRIER(); \ + /*GET_RING_HEAD( dev_priv ); */ \ + OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ + /* read from PCI bus to ensure correct posting */ \ + INREG( RADEON_CP_RB_RPTR ); \ +} while (0) + diff --git a/programs/system/drivers/ati2d/accel_2d.inc b/programs/system/drivers/ati2d/accel_2d.inc new file mode 100644 index 0000000000..fbf83114e6 --- /dev/null +++ b/programs/system/drivers/ati2d/accel_2d.inc @@ -0,0 +1,175 @@ + +#define BRUSH_MONO (0<<4) + +int DrawRect(draw_t* draw) +{ + int x0, y0, x1, y1; + + x0 = draw->x; + y0 = draw->y; + + x1 = x0+draw->w-1; + y1 = y0+draw->h-1; + +// dbgprintf("draw rect x0:%d, y0:%d, x1:%d, y1:%d, color: %x\n", +// x0, y0, x1, y1, draw->color); + + if( ! BlockClip( &x0, &y0, &x1, &y1)) + { + u32 *ring, write; + int w, h; + u32 ifl; + + w = x1-x0+1; + h = y1-y0+1; + + ifl = safe_cli(); + + BEGIN_RING(); + OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); + + + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + RADEON_GMC_DST_32BPP | + RADEON_GMC_SRC_DATATYPE_COLOR | + (1 << 28)+(1 << 30) | R5XX_ROP3_P); + + OUT_RING(rhd.dst_pitch_offset); + OUT_RING(draw->color); + OUT_RING((y0<<16)|x0); + OUT_RING((w<<16)|h); + COMMIT_RING(); + +/* +#if 1 + +#else + + R5xxFIFOWait(7); + + OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | R5XX_ROP3_P | + R5XX_GMC_BRUSH_SOLID_COLOR | + R5XX_GMC_SRC_DATATYPE_COLOR); + + OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); + OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); + OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); + OUTREG(R5XX_DST_PITCH_OFFSET, rhd.dst_pitch_offset); + OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); + OUTREG( R5XX_DST_WIDTH_HEIGHT,(w<<16)|h); +#endif +*/ + safe_sti(ifl); + } ; + return 0; +} + +int FillRect(fill_t *fill) +{ + int x0, y0, x1, y1; + + x0 = fill->x; + y0 = fill->y; + + x1 = x0+fill->w-1; + y1 = y0+fill->h-1; + +// dbgprintf("fill rect x0:%d, y0:%d, x1:%d, y1:%d\n", +// x0, y0, x1, y1); + + if( ! BlockClip( &x0, &y0, &x1, &y1)) + { + u32 *ring, write; + u32 ifl; + + ifl = safe_cli(); + + BEGIN_RING(); + OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT, 7)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + BRUSH_MONO | + RADEON_GMC_DST_32BPP | + RADEON_GMC_SRC_DATATYPE_COLOR | + (1 << 28)+(1 << 30) | R5XX_ROP3_P); + + OUT_RING(rhd.dst_pitch_offset); + OUT_RING(fill->bkcolor); + OUT_RING(fill->fcolor); + + OUT_RING(fill->bmp0); + OUT_RING(fill->bmp1); + + // OUT_RING(0xCCCC3333); + // OUT_RING(0xCCCC3333); + // OUT_RING(~0x11884422); + // OUT_RING(~0x11884422); + +// OUT_RING(0x88112244); +// OUT_RING(0x88112244); + + OUT_RING((y0<<16)|x0); + OUT_RING((y1<<16)|x1); + COMMIT_RING(); + + safe_sti(ifl); + }; + return 0; +} + + + +int Line2P(line2p_t *draw) +{ + + int x0, y0, x1, y1; + + x0 = draw->x0; + y0 = draw->y0; + + x1 = draw->x1; + y1 = draw->y1; + + if ( !LineClip( &x0, &y0, &x1, &y1 )) + { + u32 ifl; + u32 *ring, write; + + ifl = safe_cli(); + + BEGIN_RING(); + OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_POLYLINE, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + RADEON_GMC_DST_32BPP | + RADEON_GMC_SRC_DATATYPE_COLOR | + (1 << 28)+(1 << 30) | R5XX_ROP3_P); + + OUT_RING(rhd.dst_pitch_offset); + OUT_RING(draw->color); + OUT_RING((y0<<16)|x0); + OUT_RING((y1<<16)|x1); + COMMIT_RING(); + + +/* + R5xxFIFOWait(7); + + OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | R5XX_ROP3_P | + R5XX_GMC_BRUSH_SOLID_COLOR | + R5XX_GMC_SRC_DATATYPE_COLOR); + + OUTREG(R5XX_DST_LINE_PATCOUNT, 0x55 << R5XX_BRES_CNTL_SHIFT); + + OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); + OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); + OUTREG(R5XX_DST_PITCH_OFFSET, rhd.dst_pitch_offset); + + OUTREG(R5XX_DST_LINE_START,(y0<<16)|x0); + OUTREG(R5XX_DST_LINE_END,(y1<<16)|x1); +*/ + safe_sti(ifl); + + }; + return 0; +} diff --git a/programs/system/drivers/ati2d/ati2d.c b/programs/system/drivers/ati2d/ati2d.c new file mode 100644 index 0000000000..5cc2051864 --- /dev/null +++ b/programs/system/drivers/ati2d/ati2d.c @@ -0,0 +1,373 @@ + +//ld -T ld.x -s --shared --image-base 0 --file-alignment 32 -o test.exe test.obj core.lib + +#include "common.h" +#include "ati2d.h" +#include "accel_2d.h" + +RHD_t rhd; + +static clip_t clip; + +void STDCALL (*SelectHwCursor)(cursor_t*)__asm__("SelectHwCursor"); +void STDCALL (*SetHwCursor)(cursor_t*,int x,int y)__asm__("SetHwCursor"); +void STDCALL (*HwCursorRestore)(int x, int y)__asm("HwCursorRestore"); +cursor_t* IMPORT (*HwCursorCreate)(void)__asm("HwCursorCreate"); //params eax, ebx, ecx + +void (__stdcall *old_select)(cursor_t*); +void (__stdcall *old_set)(cursor_t*,int x,int y); +void (__stdcall *old_restore)(int x, int y); +cursor_t* (*old_create)(void); +cursor_t* __create_cursor(void); + + +u32 __stdcall drvEntry(int action) +{ + RHDPtr rhdPtr; + u32 retval; + + int i; + + if(action != 1) + return 0; + + if(!dbg_open("/hd0/2/ati2d.log")) + { + printf("Can't open /rd/1/drivers/ati2d.log\nExit\n"); + return 0; + } + + if((rhdPtr=FindPciDevice())==NULL) + { + dbgprintf("Device not found\n"); + return 0; + }; + + for(i=0;i<6;i++) + { + if(rhd.memBase[i]) + dbgprintf("Memory base_%d 0x%x size 0x%x\n", + i,rhd.memBase[i],(1<input; + outp = io->output; + + switch(io->io_code) + { + case SRV_GETVERSION: + if(io->out_size==4) + { + *(u32*)io->output = API_VERSION; + return 0; + } + break; + + default: + return ERR_PARAM; + }; + return ERR_PARAM; +} + + +int _stdcall srv_2d(ioctl_t *io) +{ + u32 *inp; + u32 *outp; + + inp = io->input; + outp = io->output; + + switch(io->io_code) + { + case SRV_GETVERSION: + if(io->out_size==4) + { + *outp = API_VERSION; + return 0; + } + break; + + case DRAW_RECT: + if(io->inp_size==5) + return DrawRect((draw_t*)inp); + break; + + case LINE_2P: + if(io->inp_size==5) + return Line2P((line2p_t*)inp); + break; + + case FILL_RECT: + if(io->inp_size==8) + return FillRect((fill_t*)inp); + break; + + default: + return ERR_PARAM; + }; + return ERR_PARAM; +} + + +#include "init.c" +#include "pci.c" +#include "ati_mem.c" +#include "cursor.inc" + +#include "r500.inc" +#include "accel_2d.inc" + +#define CLIP_TOP 1 +#define CLIP_BOTTOM 2 +#define CLIP_RIGHT 4 +#define CLIP_LEFT 8 + + +char _L1OutCode( int x, int y ) +/*================================= + + Verify that a point is inside or outside the active viewport. */ +{ + char flag; + + flag = 0; + if( x < clip.xmin ) { + flag |= CLIP_LEFT; + } else if( x > clip.xmax ) { + flag |= CLIP_RIGHT; + } + if( y < clip.ymin ) { + flag |= CLIP_TOP; + } else if( y > clip.ymax ) { + flag |= CLIP_BOTTOM; + } + return( flag ); +} + + +static void line_inter( int * x1, int* y1, int x2, int y2, int x ) +/*=========================================================================== + + Find the intersection of a line with a boundary of the viewport. + (x1, y1) is outside and ( x2, y2 ) is inside the viewport. + NOTE : the signs of denom and ( x - *x1 ) cancel out during division + so make both of them positive before rounding. */ +{ + int numer; + int denom; + + denom = abs( x2 - *x1 ); + numer = 2L * (long)( y2 - *y1 ) * abs( x - *x1 ); + if( numer > 0 ) { + numer += denom; /* round to closest pixel */ + } else { + numer -= denom; + } + *y1 += numer / ( denom << 1 ); + *x1 = x; +} + + +int LineClip( int *x1, int *y1, int *x2, int *y2 ) +/*============================================================= + + Clips the line with end points (x1,y1) and (x2,y2) to the active + viewport using the Cohen-Sutherland clipping algorithm. Return the + clipped coordinates and a decision drawing flag. */ +{ + char flag1; + char flag2; + + flag1 = _L1OutCode( *x1, *y1 ); + flag2 = _L1OutCode( *x2, *y2 ); + for( ;; ) { + if( flag1 & flag2 ) break; /* trivially outside */ + if( flag1 == flag2 ) break; /* completely inside */ + if( flag1 == 0 ) { /* first point inside */ + if( flag2 & CLIP_TOP ) { + line_inter( y2, x2, *y1, *x1, clip.ymin ); + } else if( flag2 & CLIP_BOTTOM ) { + line_inter( y2, x2, *y1, *x1, clip.ymax ); + } else if( flag2 & CLIP_RIGHT ) { + line_inter( x2, y2, *x1, *y1, clip.xmax ); + } else if( flag2 & CLIP_LEFT ) { + line_inter( x2, y2, *x1, *y1, clip.xmin ); + } + flag2 = _L1OutCode( *x2, *y2 ); + } else { /* second point inside */ + if( flag1 & CLIP_TOP ) { + line_inter( y1, x1, *y2, *x2, clip.ymin ); + } else if( flag1 & CLIP_BOTTOM ) { + line_inter( y1, x1, *y2, *x2, clip.ymax ); + } else if( flag1 & CLIP_RIGHT ) { + line_inter( x1, y1, *x2, *y2, clip.xmax ); + } else if( flag1 & CLIP_LEFT ) { + line_inter( x1, y1, *x2, *y2, clip.xmin ); + } + flag1 = _L1OutCode( *x1, *y1 ); + } + } + return( flag1 & flag2 ); +} + + +static void block_inter( int *x, int *y, int flag ) +/*====================================================== + + Find the intersection of a block with a boundary of the viewport. */ +{ + if( flag & CLIP_TOP ) { + *y = clip.ymin; + } else if( flag & CLIP_BOTTOM ) { + *y = clip.ymax; + } else if( flag & CLIP_RIGHT ) { + *x = clip.xmax; + } else if( flag & CLIP_LEFT ) { + *x = clip.xmin; + } +} + + +int BlockClip( int *x1, int *y1, int *x2, int* y2 ) +/*============================================================== + + Clip a block with opposite corners (x1,y1) and (x2,y2) to the + active viewport based on the Cohen-Sutherland algorithm for line + clipping. Return the clipped coordinates and a decision drawing + flag ( 0 draw : 1 don't draw ). */ +{ + char flag1; + char flag2; + + flag1 = _L1OutCode( *x1, *y1 ); + flag2 = _L1OutCode( *x2, *y2 ); + for( ;; ) { + if( flag1 & flag2 ) break; /* trivially outside */ + if( flag1 == flag2 ) break; /* completely inside */ + if( flag1 == 0 ) { + block_inter( x2, y2, flag2 ); + flag2 = _L1OutCode( *x2, *y2 ); + } else { + block_inter( x1, y1, flag1 ); + flag1 = _L1OutCode( *x1, *y1 ); + } + } + return( flag1 & flag2 ); +} + +#if 0 +typedef struct +{ + int left; + int top; + int right; + int bottom; +}rect_t; + +typedef struct _window +{ + struct _window *fd; + struct _window *bk; + + rect_t pos; + int width; + int height; + + int level; +}win_t, *WINPTR; + + +WINPTR top = NULL; +WINPTR bottom = NULL; + +WINPTR alloc_window() +{ + WINPTR pwin = malloc(sizeof(win_t)); + + return pwin; +}; + + +WINPTR create_win(int l, int t, int w, int h, int level) +{ + WINPTR pwin = alloc_window(); + + pwin->pos.left = l; + pwin->pos.top = t; + pwin->pos.right = l+w-1; + pwin->pos.bottom = t+h-1; + pwin->width = w; + pwin->height = h; + + pwin->level = level; + + return pwin; +}; + +void insert_window(WINPTR pwin) +{ + WINPTR p = top; + + if(p) + { + if(pwin->level <= p->level) + { + pwin->fd = p; + pwin->bk = p->bk; + pwin->bk->fd = pwin; + p->bk = pwin; + } + else + p = p->fd; + } + else + top = pwin; +} + +#endif diff --git a/programs/system/drivers/ati2d/ati2d.h b/programs/system/drivers/ati2d/ati2d.h new file mode 100644 index 0000000000..db198acc3a --- /dev/null +++ b/programs/system/drivers/ati2d/ati2d.h @@ -0,0 +1,236 @@ +#include "pci.h" +#include "rhd_regs.h" + +enum RHD_CHIPSETS { + RHD_UNKNOWN = 0, + /* R500 */ + RHD_RV505, + RHD_RV515, + RHD_RV516, + RHD_R520, + RHD_RV530, + RHD_RV535, + RHD_RV550, + RHD_RV560, + RHD_RV570, + RHD_R580, + /* R500 Mobility */ + RHD_M52, + RHD_M54, + RHD_M56, + RHD_M58, + RHD_M62, + RHD_M64, + RHD_M66, + RHD_M68, + RHD_M71, + /* R500 integrated */ + RHD_RS600, + RHD_RS690, + RHD_RS740, + /* R600 */ + RHD_R600, + RHD_RV610, + RHD_RV630, + /* R600 Mobility */ + RHD_M72, + RHD_M74, + RHD_M76, + /* RV670 came into existence after RV6x0 and M7x */ + RHD_RV670, + RHD_R680, + RHD_RV620, + RHD_M82, + RHD_RV635, + RHD_M86, + RHD_CHIP_END +}; + +enum RHD_FAMILIES { + RHD_FAMILY_UNKNOWN = 0, + RHD_FAMILY_RV515, + RHD_FAMILY_R520, + RHD_FAMILY_RV530, + RHD_FAMILY_RV560, + RHD_FAMILY_RV570, + RHD_FAMILY_R580, + RHD_FAMILY_RS690, + RHD_FAMILY_R600, + RHD_FAMILY_RV610, + RHD_FAMILY_RV630, + RHD_FAMILY_RV670, + RHD_FAMILY_RV620, + RHD_FAMILY_RV635 +}; + +#define RHD_FB_BAR 0 +#define RHD_MMIO_BAR 2 + +#define RHD_MEM_GART 1 +#define RHD_MEM_FB 2 + +typedef struct RHDRec +{ + CARD32 MMIOBase; + CARD32 MMIOMapSize; + CARD32 videoRam; + + CARD32 FbBase; /* map base of fb */ + CARD32 PhisBase; + CARD32 FbIntAddress; /* card internal address of FB */ + CARD32 FbMapSize; + + CARD32 FbFreeStart; + CARD32 FbFreeSize; + + /* visible part of the framebuffer */ + unsigned int FbScanoutStart; + unsigned int FbScanoutSize; + + enum RHD_CHIPSETS ChipSet; + char *ChipName; + + Bool IsIGP; + + CARD32 bus; + CARD32 devfn; + + PCITAG PciTag; + CARD16 PciDeviceID; + + CARD16 subvendor_id; + CARD16 subdevice_id; + + CARD32 memBase[6]; + CARD32 ioBase[6]; + CARD32 memtype[6]; + CARD32 memsize[6]; + + struct mem_block *fb_heap; + struct mem_block *gart_heap; + + CARD32 displayWidth; + CARD32 displayHeight; + + CARD32 __xmin; + CARD32 __ymin; + CARD32 __xmax; + CARD32 __ymax; + + CARD32 gui_control; + CARD32 dst_pitch_offset; + CARD32 surface_cntl; + + u32 *ring_base; + u32 ring_rp; + u32 ring_wp; + +}RHD_t, *RHDPtr; + +extern RHD_t rhd; + +typedef struct +{ + int xmin; + int ymin; + int xmax; + int ymax; +}clip_t, *PTRclip; + +typedef struct { + int token; /* id of the token */ + const char * name; /* token name */ +} SymTabRec, *SymTabPtr; + +extern inline CARD32 INREG(CARD16 offset) +{ + return *(volatile CARD32 *)((CARD8*)(rhd.MMIOBase + offset)); +} + +//#define INREG(offset) *(volatile CARD32 *)((CARD8*)(rhd.MMIOBase + (offset))) + +extern inline void +OUTREG(CARD16 offset, CARD32 value) +{ + *(volatile CARD32 *)((CARD8 *)(rhd.MMIOBase + offset)) = value; +} + +extern inline CARD32 _RHDRegRead(RHDPtr rhdPtr, CARD16 offset) +{ + return *(volatile CARD32 *)((CARD8*)(rhdPtr->MMIOBase + offset)); +} + +extern inline void +MASKREG(CARD16 offset, CARD32 value, CARD32 mask) +{ + CARD32 tmp; + + tmp = INREG(offset); + tmp &= ~mask; + tmp |= (value & mask); + OUTREG(offset, tmp); +}; + +extern inline void +_RHDRegWrite(RHDPtr rhdPtr, CARD16 offset, CARD32 value) +{ + *(volatile CARD32 *)((CARD8 *)(rhdPtr->MMIOBase + offset)) = value; +} + +extern inline void +_RHDRegMask(RHDPtr rhdPtr, CARD16 offset, CARD32 value, CARD32 mask) +{ + CARD32 tmp; + + tmp = _RHDRegRead(rhdPtr, offset); + tmp &= ~mask; + tmp |= (value & mask); + _RHDRegWrite(rhdPtr, offset, tmp); +}; + +enum RHD_FAMILIES RHDFamily(enum RHD_CHIPSETS chipset); + +#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->rhdPtr, (offset)) +#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value)) +#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask)) + + +RHDPtr FindPciDevice(); + +Bool RHDPreInit(); +int rhdInitHeap(RHDPtr rhdPtr); + +#define RHDFUNC(ptr) + +#define DBG(x) x +// #define DBG(x) + +#pragma pack (push,1) +typedef struct s_cursor +{ + u32 magic; // 'CURS' + void (*destroy)(struct s_cursor*); // destructor + u32 fd; // next object in list + u32 bk; // prev object in list + u32 pid; // owner id + + void *base; // allocated memory + u32 hot_x; // hotspot coords + u32 hot_y; +}cursor_t; +#pragma pack (pop) + +#define LOAD_FROM_FILE 0 +#define LOAD_FROM_MEM 1 +#define LOAD_INDIRECT 2 + +cursor_t *create_cursor(u32 pid, void *src, u32 flags); +void __stdcall copy_cursor(void *img, void *src); +void destroy_cursor(cursor_t *cursor); +void __destroy_cursor(cursor_t *cursor); // wrap + +void __stdcall r500_SelectCursor(cursor_t *cursor); +void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y); +void __stdcall r500_CursorRestore(int x, int y); + +void R5xx2DInit(); diff --git a/programs/system/drivers/ati2d/ati_mem.c b/programs/system/drivers/ati2d/ati_mem.c new file mode 100644 index 0000000000..004348df30 --- /dev/null +++ b/programs/system/drivers/ati2d/ati_mem.c @@ -0,0 +1,211 @@ +/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- */ +/* + * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. + * + * The Weather Channel (TM) funded Tungsten Graphics to develop the + * initial release of the Radeon 8500 driver under the XFree86 license. + * This notice must be preserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Keith Whitwell + */ + +#define USED_BLOCK 1 + +#define list_for_each(entry, head) \ + for (entry = (head)->next; entry != head; entry = (entry)->next) + + +/* Very simple allocator for GART memory, working on a static range + * already mapped into each client's address space. + */ + +struct mem_block { + struct mem_block *next; + struct mem_block *prev; + int start; + int size; +}; + +/* Initialize. How to check for an uninitialized heap? + */ +static int init_heap(struct mem_block **heap, int start, int size) +{ + struct mem_block *blocks = kmalloc(sizeof(*blocks)); + + if (!blocks) + return -1; //-ENOMEM; + + *heap = kmalloc(sizeof(**heap)); + if (!*heap) + { + kfree(blocks); + return -1; //-ENOMEM; + } + + blocks->start = start; + blocks->size = size; + blocks->next = blocks->prev = *heap; + + __clear(*heap,sizeof(**heap)); + (*heap)->next = (*heap)->prev = blocks; + return 0; +} + +static struct mem_block **get_heap(RHDPtr rhdPtr, int region) +{ + switch (region) + { + case RHD_MEM_GART: + return &rhdPtr->gart_heap; + case RHD_MEM_FB: + return &rhdPtr->fb_heap; + default: + return NULL; + } +} + +static struct mem_block *split_block(struct mem_block *p, int size) +{ + + /* Maybe cut off the end of an existing block */ + if (size < p->size) + { + struct mem_block *newblock = kmalloc(sizeof(*newblock)); + if (!newblock) + goto out; + newblock->start = p->start + size; + newblock->size = p->size - size; + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + p->size = size; + p->start|=1; + } + +out: + return p; +} + +static struct mem_block *alloc_block(struct mem_block *heap, int size) +{ + struct mem_block *p; + + list_for_each(p, heap) + { + if ( !(p->start & USED_BLOCK) && size <= p->size) + return split_block(p, size); + } + + return NULL; +} + + +static struct mem_block *find_block(struct mem_block *heap, int start) +{ + struct mem_block *p; + + list_for_each(p, heap) + if ((p->start & ~USED_BLOCK) == start) + return p; + + return NULL; +} + +static void free_block(struct mem_block *p) +{ + + /* Assumes a single contiguous range. Needs a special file_priv in + * 'heap' to stop it being subsumed. + */ + + p->start &= ~USED_BLOCK; + + if ( !(p->next->start & USED_BLOCK)) + { + struct mem_block *q = p->next; + p->size += q->size; + p->next = q->next; + p->next->prev = p; + kfree(q); + } + + if ( !(p->prev->start & USED_BLOCK)) + { + struct mem_block *q = p->prev; + q->size += p->size; + q->next = p->next; + q->next->prev = q; + kfree(p); + } +} + +int rhdInitHeap(RHDPtr rhdPtr) +{ + int base = rhdPtr->FbBase + rhdPtr->FbFreeStart; + + return init_heap(&rhdPtr->fb_heap, base, rhdPtr->FbFreeSize); +}; + +void *rhd_mem_alloc(RHDPtr rhdPtr,int region, int size) +{ + struct mem_block *block, **heap; + + heap = get_heap(rhdPtr, region); + if (!heap || !*heap) + return NULL; + + /* Make things easier on ourselves: all allocations at least + * 4k aligned. + */ + + size = (size+4095) & ~4095; + + block = alloc_block(*heap, size); + + if (!block) + return NULL; + + return (void*)(block->start & ~USED_BLOCK); +} + +int rhd_mem_free(RHDPtr rhdPtr, int region, void *offset) +{ + struct mem_block *block, **heap; + + heap = get_heap(rhdPtr, region); + if (!heap || !*heap) + return -1; + + block = find_block(*heap, (int)offset); + if (!block) + return -1; + + if ( !(block->start & 1)) + return -1; + + free_block(block); + return 0; +} + + diff --git a/programs/system/drivers/ati2d/common.h b/programs/system/drivers/ati2d/common.h new file mode 100644 index 0000000000..cde04cb4c8 --- /dev/null +++ b/programs/system/drivers/ati2d/common.h @@ -0,0 +1,173 @@ + +#define OS_BASE 0x80000000 + +#include "xmd.h" + +#define NULL (void*)(0) + +#define FALSE 0 +#define TRUE 1 + +typedef void *pointer; + +typedef unsigned int Bool; + +typedef unsigned char u8; +typedef unsigned short u16; +typedef unsigned int u32; + +typedef unsigned int memType; +typedef unsigned int size_t; + +typedef struct { float hi, lo; } range; + +typedef struct +{ + unsigned handle; + unsigned io_code; + void *input; + int inp_size; + void *output; + int out_size; +}ioctl_t; + +typedef int (_stdcall *srv_proc_t)(ioctl_t *); + +u32 __stdcall drvEntry(int)__asm__("_drvEntry"); + +/////////////////////////////////////////////////////////////////////////////// + +#define STDCALL __attribute__ ((stdcall)) __attribute__ ((dllimport)) +#define IMPORT __attribute__ ((dllimport)) + +/////////////////////////////////////////////////////////////////////////////// + +#define PG_SW 0x003 +#define PG_NOCACHE 0x018 + +CARD32 STDCALL AllocKernelSpace(unsigned size)__asm__("AllocKernelSpace"); +void* STDCALL KernelAlloc(unsigned size)__asm__("KernelAlloc"); +int KernelFree(void *); + +void* STDCALL CreateRingBuffer(size_t size, u32 map)__asm__("CreateRingBuffer"); + +u32 STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService"); + +//void *CreateObject(u32 pid, size_t size); +//void *DestroyObject(void *obj); + +CARD32 STDCALL MapIoMem(CARD32 Base,CARD32 size,CARD32 flags)__asm__("MapIoMem"); + +static inline u32 GetPgAddr(void *mem) +{ + u32 retval; + + asm volatile ( + "call *__imp__GetPgAddr \n\t" + :"=eax" (retval) + :"a" (mem) + ); + return retval; +} + +/////////////////////////////////////////////////////////////////////////////// + +u32 PciApi(int cmd); + +u8 STDCALL PciRead8 (u32 bus, u32 devfn, u32 reg)__asm__("PciRead8"); +u16 STDCALL PciRead16(u32 bus, u32 devfn, u32 reg)__asm__("PciRead16"); +u32 STDCALL PciRead32(u32 bus, u32 devfn, u32 reg)__asm__("PciRead32"); + +u32 STDCALL PciWrite8 (u32 bus, u32 devfn, u32 reg,u8 val) __asm__("PciWrite8"); +u32 STDCALL PciWrite16(u32 bus, u32 devfn, u32 reg,u16 val)__asm__("PciWrite16"); +u32 STDCALL PciWrite32(u32 bus, u32 devfn, u32 reg,u32 val)__asm__("PciWrite32"); + +/////////////////////////////////////////////////////////////////////////////// + +#define SysMsgBoardStr __SysMsgBoardStr +#define PciApi __PciApi +//#define RegService __RegService +#define CreateObject __CreateObject +#define DestroyObject __DestroyObject + +/////////////////////////////////////////////////////////////////////////////// + +void *malloc(size_t); +void *calloc( size_t num, size_t size ); +void *realloc(void*, size_t); +void free(void*); + +#define kmalloc malloc +#define kfree free + +/////////////////////////////////////////////////////////////////////////////// + +int memcmp(const void *s1, const void *s2, size_t n); +void * memcpy(void * _dest, const void *_src, size_t _n); +char * strcpy(char *to, const char *from); +char * strcat(char *s, const char *append); +int strcmp(const char *s1, const char *s2); +size_t strlen(const char *str); +char * strdup(const char *_s); +char * strchr(const char *s, int c); + +/////////////////////////////////////////////////////////////////////////////// + +int snprintf(char *s, size_t n, const char *format, ...); +int printf(const char* format, ...); +int dbg_open(char *path); +int dbgprintf(const char* format, ...); + +/////////////////////////////////////////////////////////////////////////////// + + +void usleep(u32 delay); + +static int __attribute__ ((always_inline)) +abs (int i) +{ + return i < 0 ? -i : i; +}; + +static void __attribute__ ((always_inline)) +__clear (void * dst, unsigned len) +{ u32 tmp; + asm __volatile__ + ( + "xorl %%eax, %%eax \n\t" + "cld \n\t" + "rep stosb \n" + :"=c"(tmp),"=D"(tmp) + :"c"(len),"D"(dst) + :"memory","eax","cc" + ); +}; + + +static inline u32 safe_cli(void) +{ + u32 tmp; + asm volatile ( + "pushf\n\t" + "popl %0\n\t" + "cli\n" + : "=r" (tmp) + ); + return tmp; +} + +static inline void safe_sti(u32 ipl) +{ + asm volatile ( + "pushl %0\n\t" + "popf\n" + : : "r" (ipl) + ); +} + +/////////////////////////////////////////////////////////////////////////////// + +int _stdcall srv_cursor(ioctl_t *io); +int _stdcall srv_2d(ioctl_t *io); + + diff --git a/programs/system/drivers/ati2d/curhelp.asm b/programs/system/drivers/ati2d/curhelp.asm new file mode 100644 index 0000000000..60a9bed227 --- /dev/null +++ b/programs/system/drivers/ati2d/curhelp.asm @@ -0,0 +1,366 @@ + +USE32 + +format MS COFF + +include 'proc32.inc' + +struc BITMAPINFOHEADER { + .biSize dd ? ; DWORD + .biWidth dd ? ; LONG + .biHeight dd ? ; LONG + .biPlanes dw ? ; WORD + .biBitCount dw ? ; WORD + .biCompression dd ? ; DWORD + .biSizeImage dd ? ; DWORD + .biXPelsPerMeter dd ? ; LONG + .biYPelsPerMeter dd ? ; LONG + .biClrUsed dd ? ; DWORD + .biClrImportant dd ? ; DWORD +} + +virtual at 0 + BI BITMAPINFOHEADER +end virtual + +public ___create_cursor +public ___destroy_cursor +public _copy_cursor@8 + +extrn _create_cursor :dword +extrn _destroy_cursor :dword +extrn _tmp_cursor :dword + +section 'AUTO' code readable executable align 16 + +align 16 +___create_cursor: + push ecx + push ebx + push eax + call _create_cursor + add esp, 12 + ret +align 16 +___destroy_cursor: + push eax + call _destroy_cursor + add esp, 4 + ret +align 16 +proc _copy_cursor@8 stdcall, dst:dword, src:dword + locals + rBase dd ? + pQuad dd ? + pBits dd ? + pAnd dd ? + width dd ? + height dd ? + counter dd ? + endl + + mov esi, [src] + add esi,[esi+18] + mov eax,esi + + cmp [esi+BI.biBitCount], 24 + je .img_24 + cmp [esi+BI.biBitCount], 8 + je .img_8 + cmp [esi+BI.biBitCount], 4 + je .img_4 + +.img_2: + add eax, [esi] + mov [pQuad],eax + add eax,8 + mov [pBits],eax + add eax, 128 + mov [pAnd],eax + mov eax,[esi+4] + mov [width],eax + mov ebx,[esi+8] + shr ebx,1 + mov [height],ebx + + mov edi, _tmp_cursor + add edi, 32*31*4 + mov [rBase],edi + + mov esi,[pQuad] +.l21: + mov ebx, [pBits] + mov ebx, [ebx] + bswap ebx + mov eax, [pAnd] + mov eax, [eax] + bswap eax + mov [counter], 32 +@@: + xor edx, edx + shl eax,1 + setc dl + dec edx + + xor ecx, ecx + shl ebx,1 + setc cl + mov ecx, [esi+ecx*4] + and ecx, edx + and edx, 0xFF000000 + or edx, ecx + mov [edi], edx + + add edi, 4 + dec [counter] + jnz @B + + add [pBits], 4 + add [pAnd], 4 + mov edi,[rBase] + sub edi,128 + mov [rBase],edi + sub [height],1 + jnz .l21 + jmp .copy +.img_4: + add eax, [esi] + mov [pQuad],eax + add eax,64 + mov [pBits],eax + add eax, 0x200 + mov [pAnd],eax + mov eax,[esi+4] + mov [width],eax + mov ebx,[esi+8] + shr ebx,1 + mov [height],ebx + + mov edi, _tmp_cursor + add edi, 32*31*4 + mov [rBase],edi + + mov esi,[pQuad] + mov ebx, [pBits] +.l4: + mov eax, [pAnd] + mov eax, [eax] + bswap eax + mov [counter], 16 +@@: + xor edx, edx + shl eax,1 + setc dl + dec edx + + movzx ecx, byte [ebx] + and cl, 0xF0 + shr ecx, 2 + mov ecx, [esi+ecx] + and ecx, edx + and edx, 0xFF000000 + or edx, ecx + mov [edi], edx + + xor edx, edx + shl eax,1 + setc dl + dec edx + + movzx ecx, byte [ebx] + and cl, 0x0F + mov ecx, [esi+ecx*4] + and ecx, edx + and edx, 0xFF000000 + or edx, ecx + mov [edi+4], edx + + inc ebx + add edi, 8 + dec [counter] + jnz @B + + add [pAnd], 4 + mov edi,[rBase] + sub edi,128 + mov [rBase],edi + sub [height],1 + jnz .l4 + jmp .copy +.img_8: + add eax, [esi] + mov [pQuad],eax + add eax,1024 + mov [pBits],eax + add eax, 1024 + mov [pAnd],eax + mov eax,[esi+4] + mov [width],eax + mov ebx,[esi+8] + shr ebx,1 + mov [height],ebx + + mov edi, _tmp_cursor + add edi, 32*31*4 + mov [rBase],edi + + mov esi,[pQuad] + mov ebx, [pBits] +.l81: + mov eax, [pAnd] + mov eax, [eax] + bswap eax + mov [counter], 32 +@@: + xor edx, edx + shl eax,1 + setc dl + dec edx + + movzx ecx, byte [ebx] + mov ecx, [esi+ecx*4] + and ecx, edx + and edx, 0xFF000000 + or edx, ecx + mov [edi], edx + + inc ebx + add edi, 4 + dec [counter] + jnz @B + + add [pAnd], 4 + mov edi,[rBase] + sub edi,128 + mov [rBase],edi + sub [height],1 + jnz .l81 + jmp .copy +.img_24: + add eax, [esi] + mov [pQuad],eax + add eax, 0xC00 + mov [pAnd],eax + mov eax,[esi+BI.biWidth] + mov [width],eax + mov ebx,[esi+BI.biHeight] + shr ebx,1 + mov [height],ebx + + mov edi, _tmp_cursor + add edi, 32*31*4 + mov [rBase],edi + + mov esi,[pAnd] + mov ebx, [pQuad] +.row_24: + mov eax, [esi] + bswap eax + mov [counter], 32 +@@: + xor edx, edx + shl eax,1 + setc dl + dec edx + + mov ecx, [ebx] + and ecx, 0x00FFFFFF + and ecx, edx + and edx, 0xFF000000 + or edx, ecx + mov [edi], edx + add ebx, 3 + add edi, 4 + dec [counter] + jnz @B + + add esi, 4 + mov edi,[rBase] + sub edi,128 + mov [rBase],edi + sub [height],1 + jnz .row_24 +.copy: + mov edi, [dst] + mov ecx, 64*64 + xor eax,eax + rep stosd + + mov esi, _tmp_cursor + mov edi, [dst] + mov ebx, 32 + cld +@@: + mov ecx, 32 + rep movsd + add edi, 128 + dec ebx + jnz @B + ret +endp + +macro rdr op1, op2 +{ + mov op1, [edi+op2] +} + +macro wrr dest, src +{ + mov dword [edi+dest], src +} + +struc CURSOR +{;common object header + .magic dd ? ;'CURS' + .destroy dd ? ;internal destructor + .fd dd ? ;next object in list + .bk dd ? ;prev object in list + .pid dd ? ;owner id + + ;cursor data + .base dd ? ;allocated memory + .hot_x dd ? ;hotspot coords + .hot_y dd ? +} +virtual at 0 + CURSOR CURSOR +end virtual + +;public _r500_SelectCursor@4 +align 4 +proc _r500_SelectCursor@4 stdcall,hcursor:dword + + mov ecx, [hcursor] + mov edi, [_rhd] + + mov edx, [ecx+CURSOR.base] + sub edx, [_rhd+3*4] + add edx, [_rhd+5*4] + mov [edi+0x6408], edx + + mov eax, [ecx+CURSOR.hot_x] + shl eax, 16 + mov ax, word [ecx+CURSOR.hot_y] + mov [edi+0x6418], eax + ret +endp + +;public _r500_SetCursor@12 +align 4 +proc _r500_SetCursor@12 stdcall, hcursor:dword, x:dword, y:dword + pushfd + cli + + mov edx, [_rhd] + + mov eax, [x] + shl eax, 16 + mov ax, word [y] + + mov [edx+0x6414], eax + or dword [edx+0x6400], 1 + + popfd + ret +endp + diff --git a/programs/system/drivers/ati2d/cursor.inc b/programs/system/drivers/ati2d/cursor.inc new file mode 100644 index 0000000000..41a511899b --- /dev/null +++ b/programs/system/drivers/ati2d/cursor.inc @@ -0,0 +1,103 @@ + +char tmp_cursor[4096]; + +cursor_t *create_cursor(u32 pid, void *src, u32 flags) +{ + void *img; + + cursor_t *cursor = (cursor_t*)CreateObject(pid, 32); + + if(cursor==0) + return 0; + dbgprintf("create object at %x\n", cursor); + + cursor->magic = 0x53525543; + cursor->destroy = __destroy_cursor; + + img = rhd_mem_alloc(&rhd,RHD_MEM_FB,64*64*4); + if(img==0) + goto cleanup; + + dbgprintf("alloc video memory at %x size %x\n",img,64*64*4); + dbgprintf("offset %x\n", img-rhd.FbBase); + cursor->base=img; + + if( (u16)flags==LOAD_INDIRECT){ + cursor->hot_x = (u8)(flags>>24); + cursor->hot_y = (u8)(flags>>16); + asm __volatile__ + ( + "cld \n\t" + "rep stosl" + : + :"a"(0),"c"(64*64),"D"(img) + ); + asm __volatile__ + ( + "1: " + "movl $32, %%ecx \n\t" + "rep stosl \n\t" + "addl $128, %%edi \n\t" + "decl %%ebx \n\t" + "jnz 1b" + : + :"b"(32),"S"(src),"D"(img) + ); + } + else { + cursor->hot_x = *(u16*)((char*)src+10); + cursor->hot_y = *(u16*)((char*)src+12); + copy_cursor(img, src); + dbgprintf("cursor loaded\n"); + } + return cursor; +cleanup: + DestroyObject(cursor); + return NULL; +}; + +void destroy_cursor(cursor_t *cursor) +{ + if(cursor->base) + rhd_mem_free(&rhd,RHD_MEM_FB,cursor->base); + DestroyObject(cursor); +} + +void __stdcall r500_SelectCursor(cursor_t *cursor) +{ + CARD32 base; + + base = (CARD32)cursor->base - rhd.FbBase; + asm __volatile__ + ( + "cli" + ); + OUTREG (D1CUR_SURFACE_ADDRESS, rhd.FbIntAddress+base); + OUTREG (D1CUR_HOT_SPOT, (cursor->hot_x<<16)|(cursor->hot_y&0xFFFF)); + asm __volatile__ + ( + "sti" + ); +} + +void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y) +{ + CARD32 tmp = (x<<16)|(y & 0xFFFF) ; + + asm __volatile__ + ( + "pushfl \n\t" + "cli" + ); + + OUTREG(D1CUR_POSITION, tmp); + OUTREG(D1CUR_CONTROL, 0x301); + asm __volatile__ + ( + "popfl" + ); +} + +void __stdcall r500_CursorRestore(int x, int y) +{}; + diff --git a/programs/system/drivers/ati2d/dbg.c b/programs/system/drivers/ati2d/dbg.c new file mode 100644 index 0000000000..ca81faaccc --- /dev/null +++ b/programs/system/drivers/ati2d/dbg.c @@ -0,0 +1,510 @@ + +#include "common.h" + +#pragma pack(push, 1) +typedef struct +{ + char sec; + char min; + char hour; + char rsv; +}detime_t; +#pragma pack(pop) + +#pragma pack(push, 1) +typedef struct +{ + char day; + char month; + short year; +}dedate_t; +#pragma pack(pop) + + +#pragma pack(push, 1) +typedef struct +{ unsigned attr; + unsigned flags; + union + { + detime_t ctime; + unsigned cr_time; + }; + union + { + dedate_t cdate; + unsigned cr_date; + }; + union + { + detime_t atime; + unsigned acc_time; + }; + union + { + dedate_t adate; + unsigned acc_date; + }; + union + { + detime_t mtime; + unsigned mod_time; + }; + union + { + dedate_t mdate; + unsigned mod_date; + }; + unsigned size; + unsigned size_high; +} FILEINFO; +#pragma pack(pop) + +typedef struct +{ + char *path; + int offset; +} dbgfile_t; + +static dbgfile_t dbgfile; + +static void __SysMsgBoardStr(char *text) +{ + asm __volatile__ + ( + "call *__imp__SysMsgBoardStr" + : + :"S" (text) + ); +}; + +int get_fileinfo(const char *path,FILEINFO *info) +{ + int retval; + + asm __volatile__ + ( + "pushl $0 \n\t" + "pushl $0 \n\t" + "movl %%eax, 1(%%esp) \n\t" + "pushl %%ebx \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl $5 \n\t" + "movl %%esp, %%ebx \n\t" + "movl $70, %%eax \n\t" + "int $0x40 \n\t" + "addl $28, %%esp \n\t" + :"=eax" (retval) + :"a" (path), "b" (info) + ); + return retval; +}; + +int create_file(const char *path) +{ + int retval; + asm __volatile__ + ( + "pushl %%ebx \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "movl %%eax, 1(%%esp) \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl $2 \n\t" + "movl %%esp, %%ebx \n\t" + "movl $70, %%eax \n\t" + "int $0x40 \n\t" + "addl $28, %%esp \n\t" + "popl %%ebx" + :"=eax" (retval) + :"a" (path) + ); + return retval; +}; + +int set_file_size(const char *path, unsigned size) +{ + int retval; + asm __volatile__( + "pushl $0 \n\t" + "pushl $0 \n\t" + "movl %%eax, 1(%%esp) \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl $0 \n\t" + "pushl %%ebx \n\t" + "push $4 \n\t" + "movl %%esp, %%ebx \n\t" + "movl $70, %%eax \n\t" + "int $0x40 \n\t" + "addl $28, %%esp \n\t" + :"=eax" (retval) + :"a" (path), "b" (size) + ); + return retval; +}; + +int write_file(const char *path,const void *buff, + unsigned offset,unsigned count,unsigned *writes) +{ + int retval; + asm __volatile__ + ( + "pushl $0 \n\t" + "pushl $0 \n\t" + "movl %%eax, 1(%%esp) \n\t" + "pushl %%ebx \n\t" + "pushl %%edx \n\t" + "pushl $0 \n\t" + "pushl %%ecx \n\t" + "pushl $3 \n\t" + "movl %%esp, %%ebx \n\t" + "mov $70, %%eax \n\t" + "int $0x40 \n\t" + "testl %%esi, %%esi \n\t" + "jz 1f \n\t" + "movl %%ebx, (%%esi) \n\t" +"1:" + "addl $28, %%esp \n\t" + :"=eax" (retval) + :"a"(path),"b"(buff),"c"(offset),"d"(count),"S"(writes) + ); + return retval; +}; + +char * _putc(char *s, int c) +{ + int i=0; + + switch(c) + { + case '\n': + *s++ = '\r'; + *s++ = '\n'; + + case '\r': + break; + + case '\t': + do + { + *s++ = ' '; + } + while (i % 8 != 0); + break; + default: + *s++ = c; + } + return s; +} + +char *print_string(char *buff, char* s) +{ + int i=0; + char c; + + while (c=*s++) + { + switch(c) + { + case '\r': + break; + + case '\n': + *buff++ = '\r'; + *buff++ = '\n'; + i=0; + + case '\t': + do + { + *buff++ = ' '; + i++; + } + while (i % 8 != 0); + break; + + default: + *buff++ = c; + i++; + }; + } + return buff; +} + +char *print_dec(char *buff,int val) +{ + char dbuff[16]; + int i = 14; + + dbuff[15] = '\0'; + do + { + dbuff[i] = (val % 10) + '0'; + val = val / 10; + i--; + } while(val); + + return print_string(buff, &dbuff[i+1]); +} + +const char hexchars[] = "0123456789ABCDEF"; + +char *print_hex(char *buff,u32 val) +{ + int i; + for (i=sizeof(u32)*8-4; i >= 0; i -= 4) + buff = _putc(buff,hexchars[((u32)val >> i) & 0xF]); + return buff; +} + +#define va_start(v,l) __builtin_va_start(v,l) +#define va_end(v) __builtin_va_end(v) +#define va_arg(v,l) __builtin_va_arg(v,l) +#if !defined(__STRICT_ANSI__) || __STDC_VERSION__ + 0 >= 199900L +#define va_copy(d,s) __builtin_va_copy(d,s) +#endif +#define __va_copy(d,s) __builtin_va_copy(d,s) + +typedef __builtin_va_list __gnuc_va_list; +typedef __gnuc_va_list va_list; + +#define arg(x) va_arg (ap, u32) + +char txtbuf[128]; + +int printf(const char* format, ...) +{ + u32 ret = 1; + u32 i = 0; + char *sbuf = txtbuf; + + va_list ap; + + va_start (ap, format); + + if (format == 0) + return 0; + + while (*format) + { + switch (*(format)) + { + case '%': +next_fmt: + switch (*(++format)) + { + case 'l': case '-': + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + goto next_fmt; + + case 'c': + sbuf = _putc (sbuf,arg (i)); + break; + case 'd': + sbuf = print_dec (sbuf,arg (i)); + break; + case 'p': + case 'x': + sbuf = print_hex (sbuf,(u32) arg (i)); + break; + case 's': + sbuf = print_string (sbuf,(char*) arg (i)); + break; + default: + sbuf = print_string (sbuf,"?"); + break; + } + i++; + break; + + default: + sbuf = _putc (sbuf,*format); + break; + } + format++; + } + + va_end (ap); + *sbuf=0; + SysMsgBoardStr(txtbuf); + return ret; +} + +int dbg_open(char *path) +{ + FILEINFO info; + + dbgfile.offset = 0; + + if(get_fileinfo(path,&info)) + { + if(!create_file(path)) + { + dbgfile.path = path; + return TRUE; + } + else + return FALSE; + }; + set_file_size(path, 0); + dbgfile.path = path; + dbgfile.offset = 0; + return TRUE; +}; + +int vsnprintf(char *s, size_t n, const char *format, va_list arg); + +int dbgprintf(const char* format, ...) +{ + unsigned writes; + + int len=0; +// char *sbuf = txtbuf; + + va_list ap; + + va_start(ap, format); + if (format) + len = vsnprintf(txtbuf, 128, format, ap); + va_end(ap); + + SysMsgBoardStr(txtbuf); + + if(dbgfile.path) + { + write_file(dbgfile.path,txtbuf,dbgfile.offset,len,&writes); + dbgfile.offset+=writes; + }; + return len; +} + +int xf86DrvMsg(int skip, int code, const char* format, ...) +{ + unsigned writes; + va_list ap; + + int len=0; + + va_start(ap, format); + if (format) + len = vsnprintf(txtbuf, 128, format, ap); + va_end(ap); + + SysMsgBoardStr(txtbuf); + + if(dbgfile.path) + { + write_file(dbgfile.path,txtbuf,dbgfile.offset,len,&writes); + dbgfile.offset+=writes; + }; + return len; +} + +int snprintf(char *s, size_t n, const char *format, ...) +{ + va_list ap; + int retval; + + va_start(ap, format); + retval = vsnprintf(s, n, format, ap); + va_end(ap); + + return retval; +} +/* +int snprintf(char *buf,int count, const char* format, ...) +{ + int len; + + // u32 ret = 1; + u32 i = 0; + char *sbuf = buf; + + va_list ap; + + va_start (ap, format); + + if (format == 0) + return 0; + + while (*format) + { + switch (*(format)) + { + case '%': +next_fmt: + switch (*(++format)) + { + case 'l': case '-': + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + goto next_fmt; + + case 'c': + sbuf = _putc (sbuf,arg (i)); + break; + case 'd': + sbuf = print_dec (sbuf,arg (i)); + break; + case 'p': + case 'x': + sbuf = print_hex (sbuf,(u32) arg (i)); + break; + case 's': + sbuf = print_string (sbuf,(char*) arg (i)); + break; + default: + sbuf = print_string (sbuf,"?"); + break; + } + i++; + break; + + default: + sbuf = _putc (sbuf,*format); + break; + } + format++; + } + + va_end (ap); + *sbuf=0; + len = sbuf-txtbuf; + + return len; +} +*/ + +char * +RhdAppendString(char *s1, const char *s2) +{ + + if (!s2) + return s1; + else + if (!s1) + return strdup(s2); + else + { + int len = strlen(s1) + strlen(s2) + 1; + char *result = (char *)kmalloc(len); + + if (!result) return s1; + + strcpy(result,s1); + strcat(result,s2); + kfree(s1); + return result; + } + + return 0; +} + + diff --git a/programs/system/drivers/ati2d/helper.c b/programs/system/drivers/ati2d/helper.c new file mode 100644 index 0000000000..70da9ba5d3 --- /dev/null +++ b/programs/system/drivers/ati2d/helper.c @@ -0,0 +1,78 @@ + +#include "common.h" + +void usleep(u32 delay) +{ + if(!delay) delay++; + delay*=2000; + + asm __volatile__ + ( + "1:\n\t" + "xorl %%eax, %%eax \n\t" + "cpuid \n\t" + "decl %%edi \n\t" + "jnz 1b" + : + :"D"(delay) + :"eax","ebx","ecx","edx" + ); +} + +u32 __PciApi(int cmd) +{ + u32 retval; + + asm __volatile__ + ( + "call *__imp__PciApi" + :"=eax" (retval) + :"a" (cmd) + :"memory" + ); + return retval; +}; + +/* +u32 __RegService(char *name, srv_proc_t proc) +{ + u32 retval; + + asm __volatile__ + ( + "pushl %%eax \n\t" + "pushl %%ebx \n\t" + "call *__imp__RegService \n\t" + :"=eax" (retval) + :"a" (proc), "b" (name) + :"memory" + ); + return retval; +}; +*/ + +void *__CreateObject(u32 pid, size_t size) +{ + void *retval; + + asm __volatile__ + ( + "call *__imp__CreateObject \n\t" + :"=eax" (retval) + :"a" (size),"b"(pid) + :"esi","edi", "memory" + ); + + return retval; +} + +void *__DestroyObject(void *obj) +{ + asm __volatile__ + ( + "call *__imp__DestroyObject" + : + :"a" (obj) + :"ebx","edx","esi","edi", "memory" + ); +} diff --git a/programs/system/drivers/ati2d/init.c b/programs/system/drivers/ati2d/init.c new file mode 100644 index 0000000000..2b8a59adc9 --- /dev/null +++ b/programs/system/drivers/ati2d/init.c @@ -0,0 +1,126 @@ + + +static Bool +rhdMapMMIO(RHDPtr rhdPtr) +{ + rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR]; + rhdPtr->MMIOBase = MapIoMem(rhdPtr->memBase[RHD_MMIO_BAR], + rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE); + if( rhdPtr->MMIOBase==0) + return 0; + + DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize)); + return 1; +} + +#define RADEON_NB_TOM 0x15c + +static CARD32 +rhdGetVideoRamSize(RHDPtr rhdPtr) +{ + CARD32 RamSize, BARSize; + + if (rhdPtr->ChipSet == RHD_RS690) + RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE))>>10; + else + if (rhdPtr->IsIGP) + { + CARD32 tom = _RHDRegRead(rhdPtr, RADEON_NB_TOM); + RamSize = (((tom >> 16) - (tom & 0xffff) + 1) << 6); + _RHDRegWrite(rhdPtr,R5XX_CONFIG_MEMSIZE, RamSize<<10); + } + else + { + if (rhdPtr->ChipSet < RHD_R600) + { + RamSize = (_RHDRegRead(rhdPtr, R5XX_CONFIG_MEMSIZE)) >> 10; + if(RamSize==0) RamSize=8192; + } + else + RamSize = (_RHDRegRead(rhdPtr, R6XX_CONFIG_MEMSIZE)) >> 10; + }; + + BARSize = 1 << (rhdPtr->memsize[RHD_FB_BAR] - 10); + if(BARSize==0) + BARSize = 0x20000; + + if (RamSize > BARSize) { + DBG(dbgprintf("The detected amount of videoram" + " exceeds the PCI BAR aperture.\n")); + DBG(dbgprintf("Using only %dkB of the total " + "%dkB.\n", (int) BARSize, (int) RamSize)); + return BARSize; + } + else return RamSize; +} + +static Bool +rhdMapFB(RHDPtr rhdPtr) +{ + rhdPtr->FbMapSize = 1 << rhdPtr->memsize[RHD_FB_BAR]; + rhdPtr->PhisBase = rhdPtr->memBase[RHD_FB_BAR]; + + rhdPtr->FbBase = MapIoMem(rhdPtr->PhisBase, rhdPtr->FbMapSize,PG_SW+PG_NOCACHE); + + if (!rhdPtr->FbBase) + return FALSE; + + /* These devices have an internal address reference, which some other + * address registers in there also use. This can be different from the + * address in the BAR */ + if (rhdPtr->ChipSet < RHD_R600) + rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, HDP_FB_LOCATION)<< 16; + else + rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, R6XX_CONFIG_FB_BASE); + +// rhdPtr->FbIntAddress = _RHDRegRead(rhdPtr, 0x6110); +// dbgprintf("rhdPtr->FbIntAddress %x\n",rhdPtr->FbIntAddress); + + if (rhdPtr->FbIntAddress != rhdPtr->PhisBase) + dbgprintf("PCI FB Address (BAR) is at " + "0x%08X while card Internal Address is 0x%08X\n", + (unsigned int) rhdPtr->PhisBase,rhdPtr->FbIntAddress); + dbgprintf("Mapped FB at %p (size 0x%08X)\n",rhdPtr->FbBase, rhdPtr->FbMapSize); + return TRUE; +} + +Bool RHDPreInit() +{ + /* We need access to IO space already */ + if (!rhdMapMMIO(&rhd)) { + dbgprintf("Failed to map MMIO.\n"); + return FALSE; + }; + + rhd.videoRam = rhdGetVideoRamSize(&rhd); + if (!rhd.videoRam) + { + dbgprintf("No Video RAM detected.\n"); + goto error1; + } + dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); + + rhd.FbFreeStart = 0; + rhd.FbFreeSize = rhd.videoRam << 10; + + if( !rhdMapFB(&rhd)) + return FALSE; + + rhd.FbScanoutStart = 0; + rhd.FbScanoutSize = 8*1024*1024; + rhd.FbFreeStart = 8*1024*1024; + rhd.FbFreeSize = rhd.FbMapSize - 8*1024*1024; + + rhdInitHeap(&rhd); + return TRUE; + +error1: + return FALSE; +}; + +int KernelFree(void *p) +{ + + return 0; +} + diff --git a/programs/system/drivers/ati2d/microcode.h b/programs/system/drivers/ati2d/microcode.h new file mode 100644 index 0000000000..2d6eb96158 --- /dev/null +++ b/programs/system/drivers/ati2d/microcode.h @@ -0,0 +1,260 @@ + +static const u32 R520_cp_microcode[][2]={ + { 0x4200e000, 0000000000 }, + { 0x4000e000, 0000000000 }, + { 0x00000099, 0x00000008 }, + { 0x0000009d, 0x00000008 }, + { 0x4a554b4a, 0000000000 }, + { 0x4a4a4467, 0000000000 }, + { 0x55526f75, 0000000000 }, + { 0x4a7e7d65, 0000000000 }, + { 0xe0dae6f6, 0000000000 }, + { 0x4ac54a4a, 0000000000 }, + { 0xc8828282, 0000000000 }, + { 0xbf4acfc1, 0000000000 }, + { 0x87b04ad5, 0000000000 }, + { 0xb5838383, 0000000000 }, + { 0x4a0f85ba, 0000000000 }, + { 0x000ca000, 0x00000004 }, + { 0x000d0012, 0x00000038 }, + { 0x0000e8b4, 0x00000004 }, + { 0x000d0014, 0x00000038 }, + { 0x0000e8b6, 0x00000004 }, + { 0x000d0016, 0x00000038 }, + { 0x0000e854, 0x00000004 }, + { 0x000d0018, 0x00000038 }, + { 0x0000e855, 0x00000004 }, + { 0x000d001a, 0x00000038 }, + { 0x0000e856, 0x00000004 }, + { 0x000d001c, 0x00000038 }, + { 0x0000e857, 0x00000004 }, + { 0x000d001e, 0x00000038 }, + { 0x0000e824, 0x00000004 }, + { 0x000d0020, 0x00000038 }, + { 0x0000e825, 0x00000004 }, + { 0x000d0022, 0x00000038 }, + { 0x0000e830, 0x00000004 }, + { 0x000d0024, 0x00000038 }, + { 0x0000f0c0, 0x00000004 }, + { 0x000d0026, 0x00000038 }, + { 0x0000f0c1, 0x00000004 }, + { 0x000d0028, 0x00000038 }, + { 0x0000e000, 0x00000004 }, + { 0x000d002a, 0x00000038 }, + { 0x0000e000, 0x00000004 }, + { 0x000d002c, 0x00000038 }, + { 0x0000e000, 0x00000004 }, + { 0x000d002e, 0x00000038 }, + { 0x0000e000, 0x00000004 }, + { 0x000d0030, 0x00000038 }, + { 0x0000e000, 0x00000004 }, + { 0x000d0032, 0x00000038 }, + { 0x0000f180, 0x00000004 }, + { 0x000d0034, 0x00000038 }, + { 0x0000f393, 0x00000004 }, + { 0x000d0036, 0x00000038 }, + { 0x0000f38a, 0x00000004 }, + { 0x000d0038, 0x00000038 }, + { 0x0000f38e, 0x00000004 }, + { 0x0000e821, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00000043, 0x00000018 }, + { 0x00cce800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x08004800, 0x00000004 }, + { 0x0000003a, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x2000451d, 0x00000004 }, + { 0x0000e580, 0x00000004 }, + { 0x000ce581, 0x00000004 }, + { 0x08004580, 0x00000004 }, + { 0x000ce581, 0x00000004 }, + { 0x00000047, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x0000e50e, 0x00000004 }, + { 0x00032000, 0x00000004 }, + { 0x00022051, 0x00000028 }, + { 0x00000051, 0x00000024 }, + { 0x0800450f, 0x00000004 }, + { 0x0000a04b, 0x00000008 }, + { 0x0000e565, 0x00000004 }, + { 0x0000e566, 0x00000004 }, + { 0x00000052, 0x00000008 }, + { 0x03cca5b4, 0x00000004 }, + { 0x05432000, 0x00000004 }, + { 0x00022000, 0x00000004 }, + { 0x4ccce05e, 0x00000030 }, + { 0x08274565, 0x00000004 }, + { 0x0000005e, 0x00000030 }, + { 0x08004564, 0x00000004 }, + { 0x0000e566, 0x00000004 }, + { 0x00000055, 0x00000008 }, + { 0x00802061, 0x00000010 }, + { 0x00202000, 0x00000004 }, + { 0x001b00ff, 0x00000004 }, + { 0x01000064, 0x00000010 }, + { 0x001f2000, 0x00000004 }, + { 0x001c00ff, 0x00000004 }, + { 0000000000, 0x0000000c }, + { 0x00000072, 0x00000030 }, + { 0x00000055, 0x00000008 }, + { 0x0000e576, 0x00000004 }, + { 0x0000e577, 0x00000004 }, + { 0x0000e50e, 0x00000004 }, + { 0x0000e50f, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00000069, 0x00000018 }, + { 0x00c0e5f9, 0x000000c2 }, + { 0x00000069, 0x00000008 }, + { 0x0014e50e, 0x00000004 }, + { 0x0040e50f, 0x00000004 }, + { 0x00c0006c, 0x00000008 }, + { 0x0000e570, 0x00000004 }, + { 0x0000e571, 0x00000004 }, + { 0x0000e572, 0x0000000c }, + { 0x0000a000, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x0000e568, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0x00000076, 0x00000018 }, + { 0x000b0000, 0x00000004 }, + { 0x18c0e562, 0x00000004 }, + { 0x00000078, 0x00000008 }, + { 0x00c00077, 0x00000008 }, + { 0x000700c7, 0x00000004 }, + { 0x00000080, 0x00000038 }, + { 0x0000e5bb, 0x00000004 }, + { 0x0000e5bc, 0000000000 }, + { 0x0000a000, 0x00000004 }, + { 0x0000e821, 0x00000004 }, + { 0x0000e800, 0000000000 }, + { 0x0000e821, 0x00000004 }, + { 0x0000e82e, 0000000000 }, + { 0x02cca000, 0x00000004 }, + { 0x00140000, 0x00000004 }, + { 0x000ce1cc, 0x00000004 }, + { 0x050de1cd, 0x00000004 }, + { 0x00400000, 0x00000004 }, + { 0x0000008f, 0x00000018 }, + { 0x00c0a000, 0x00000004 }, + { 0x0000008c, 0x00000008 }, + { 0x00000091, 0x00000020 }, + { 0x4200e000, 0000000000 }, + { 0x00000098, 0x00000038 }, + { 0x000ca000, 0x00000004 }, + { 0x00140000, 0x00000004 }, + { 0x000c2000, 0x00000004 }, + { 0x00160000, 0x00000004 }, + { 0x700ce000, 0x00000004 }, + { 0x00140094, 0x00000008 }, + { 0x4000e000, 0000000000 }, + { 0x02400000, 0x00000004 }, + { 0x400ee000, 0x00000004 }, + { 0x02400000, 0x00000004 }, + { 0x4000e000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x0240e51b, 0x00000004 }, + { 0x0080e50a, 0x00000005 }, + { 0x0080e50b, 0x00000005 }, + { 0x00220000, 0x00000004 }, + { 0x000700c7, 0x00000004 }, + { 0x000000a4, 0x00000038 }, + { 0x0080e5bd, 0x00000005 }, + { 0x0000e5bb, 0x00000005 }, + { 0x0080e5bc, 0x00000005 }, + { 0x00210000, 0x00000004 }, + { 0x02800000, 0x00000004 }, + { 0x00c000ab, 0x00000018 }, + { 0x4180e000, 0x00000040 }, + { 0x000000ad, 0x00000024 }, + { 0x01000000, 0x0000000c }, + { 0x0100e51d, 0x0000000c }, + { 0x000045bb, 0x00000004 }, + { 0x000080a7, 0x00000008 }, + { 0x0000f3ce, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c053cf, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x0000f3d2, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c053d3, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x0000f39d, 0x00000004 }, + { 0x0140a000, 0x00000004 }, + { 0x00cc2000, 0x00000004 }, + { 0x08c0539e, 0x00000040 }, + { 0x00008000, 0000000000 }, + { 0x03c00830, 0x00000004 }, + { 0x4200e000, 0000000000 }, + { 0x0000a000, 0x00000004 }, + { 0x200045e0, 0x00000004 }, + { 0x0000e5e1, 0000000000 }, + { 0x00000001, 0000000000 }, + { 0x000700c4, 0x00000004 }, + { 0x0800e394, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x0000e8c4, 0x00000004 }, + { 0x0000e8c5, 0x00000004 }, + { 0x0000e8c6, 0x00000004 }, + { 0x0000e928, 0x00000004 }, + { 0x0000e929, 0x00000004 }, + { 0x0000e92a, 0x00000004 }, + { 0x000000c8, 0x00000008 }, + { 0x0000e928, 0x00000004 }, + { 0x0000e929, 0x00000004 }, + { 0x0000e92a, 0x00000004 }, + { 0x000000cf, 0x00000008 }, + { 0xdeadbeef, 0000000000 }, + { 0x00000116, 0000000000 }, + { 0x000700d3, 0x00000004 }, + { 0x080050e7, 0x00000004 }, + { 0x000700d4, 0x00000004 }, + { 0x0800401c, 0x00000004 }, + { 0x0000e01d, 0000000000 }, + { 0x02c02000, 0x00000004 }, + { 0x00060000, 0x00000004 }, + { 0x000000de, 0x00000034 }, + { 0x000000db, 0x00000008 }, + { 0x00008000, 0x00000004 }, + { 0xc000e000, 0000000000 }, + { 0x0000e1cc, 0x00000004 }, + { 0x0500e1cd, 0x00000004 }, + { 0x000ca000, 0x00000004 }, + { 0x000000e5, 0x00000034 }, + { 0x000000e1, 0x00000008 }, + { 0x0000a000, 0000000000 }, + { 0x0019e1cc, 0x00000004 }, + { 0x001b0001, 0x00000004 }, + { 0x0500a000, 0x00000004 }, + { 0x080041cd, 0x00000004 }, + { 0x000ca000, 0x00000004 }, + { 0x000000fb, 0x00000034 }, + { 0x0000004a, 0x00000008 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0x000c2000, 0x00000004 }, + { 0x001d0018, 0x00000004 }, + { 0x001a0001, 0x00000004 }, + { 0x000000fb, 0x00000034 }, + { 0x0000004a, 0x00000008 }, + { 0x0500a04a, 0x00000008 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, + { 0000000000, 0000000000 }, +}; + diff --git a/programs/system/drivers/ati2d/pci.c b/programs/system/drivers/ati2d/pci.c new file mode 100644 index 0000000000..cd5ad7295c --- /dev/null +++ b/programs/system/drivers/ati2d/pci.c @@ -0,0 +1,397 @@ + +SymTabRec RHDChipsets[] = { + /* R500 */ + { RHD_RV505, "RV505" }, + { RHD_RV515, "RV515" }, + { RHD_RV516, "RV516" }, + { RHD_R520, "R520" }, + { RHD_RV530, "RV530" }, + { RHD_RV535, "RV535" }, + { RHD_RV550, "RV550" }, + { RHD_RV560, "RV560" }, + { RHD_RV570, "RV570" }, + { RHD_R580, "R580" }, + /* R500 Mobility */ + { RHD_M52, "M52" }, + { RHD_M54, "M54" }, + { RHD_M56, "M56" }, + { RHD_M58, "M58" }, + { RHD_M62, "M62" }, + { RHD_M64, "M64" }, + { RHD_M66, "M66" }, + { RHD_M68, "M68" }, + { RHD_M71, "M71" }, + /* R500 integrated */ + { RHD_RS600, "RS600" }, + { RHD_RS690, "RS690" }, + { RHD_RS740, "RS740" }, + /* R600 */ + { RHD_R600, "R600" }, + { RHD_RV610, "RV610" }, + { RHD_RV630, "RV630" }, + /* R600 Mobility */ + { RHD_M72, "M72" }, + { RHD_M74, "M74" }, + { RHD_M76, "M76" }, + /* RV670 came into existence after RV6x0 and M7x */ + { RHD_RV670, "RV670" }, + { RHD_R680, "R680" }, + { RHD_RV620, "RV620" }, + { RHD_RV635, "RV635" }, + { -1, NULL } +}; + +# define RHD_DEVICE_MATCH(d, i) { (d),(i) } +# define PCI_ID_LIST PciChipset_t RHDPCIchipsets[] +# define LIST_END { 0, 0} + +const PCI_ID_LIST = { + RHD_DEVICE_MATCH( 0x7100, RHD_R520 ), /* Radeon X1800 */ + RHD_DEVICE_MATCH( 0x7101, RHD_M58 ), /* Mobility Radeon X1800 XT */ + RHD_DEVICE_MATCH( 0x7102, RHD_M58 ), /* Mobility Radeon X1800 */ + RHD_DEVICE_MATCH( 0x7103, RHD_M58 ), /* Mobility FireGL V7200 */ + RHD_DEVICE_MATCH( 0x7104, RHD_R520 ), /* FireGL V7200 */ + RHD_DEVICE_MATCH( 0x7105, RHD_R520 ), /* FireGL V5300 */ + RHD_DEVICE_MATCH( 0x7106, RHD_M58 ), /* Mobility FireGL V7100 */ + RHD_DEVICE_MATCH( 0x7108, RHD_R520 ), /* Radeon X1800 */ + RHD_DEVICE_MATCH( 0x7109, RHD_R520 ), /* Radeon X1800 */ + RHD_DEVICE_MATCH( 0x710A, RHD_R520 ), /* Radeon X1800 */ + RHD_DEVICE_MATCH( 0x710B, RHD_R520 ), /* Radeon X1800 */ + RHD_DEVICE_MATCH( 0x710C, RHD_R520 ), /* Radeon X1800 */ + RHD_DEVICE_MATCH( 0x710E, RHD_R520 ), /* FireGL V7300 */ + RHD_DEVICE_MATCH( 0x710F, RHD_R520 ), /* FireGL V7350 */ + RHD_DEVICE_MATCH( 0x7140, RHD_RV515 ), /* Radeon X1600/X1550 */ + RHD_DEVICE_MATCH( 0x7141, RHD_RV505 ), /* RV505 */ + RHD_DEVICE_MATCH( 0x7142, RHD_RV515 ), /* Radeon X1300/X1550 */ + RHD_DEVICE_MATCH( 0x7143, RHD_RV505 ), /* Radeon X1550 */ + RHD_DEVICE_MATCH( 0x7144, RHD_M54 ), /* M54-GL */ + RHD_DEVICE_MATCH( 0x7145, RHD_M54 ), /* Mobility Radeon X1400 */ + RHD_DEVICE_MATCH( 0x7146, RHD_RV515 ), /* Radeon X1300/X1550 */ + RHD_DEVICE_MATCH( 0x7147, RHD_RV505 ), /* Radeon X1550 64-bit */ + RHD_DEVICE_MATCH( 0x7149, RHD_M52 ), /* Mobility Radeon X1300 */ + RHD_DEVICE_MATCH( 0x714A, RHD_M52 ), /* Mobility Radeon X1300 */ + RHD_DEVICE_MATCH( 0x714B, RHD_M52 ), /* Mobility Radeon X1300 */ + RHD_DEVICE_MATCH( 0x714C, RHD_M52 ), /* Mobility Radeon X1300 */ + RHD_DEVICE_MATCH( 0x714D, RHD_RV515 ), /* Radeon X1300 */ + RHD_DEVICE_MATCH( 0x714E, RHD_RV515 ), /* Radeon X1300 */ + RHD_DEVICE_MATCH( 0x714F, RHD_RV505 ), /* RV505 */ + RHD_DEVICE_MATCH( 0x7151, RHD_RV505 ), /* RV505 */ + RHD_DEVICE_MATCH( 0x7152, RHD_RV515 ), /* FireGL V3300 */ + RHD_DEVICE_MATCH( 0x7153, RHD_RV515 ), /* FireGL V3350 */ + RHD_DEVICE_MATCH( 0x715E, RHD_RV515 ), /* Radeon X1300 */ + RHD_DEVICE_MATCH( 0x715F, RHD_RV505 ), /* Radeon X1550 64-bit */ + RHD_DEVICE_MATCH( 0x7180, RHD_RV516 ), /* Radeon X1300/X1550 */ + RHD_DEVICE_MATCH( 0x7181, RHD_RV516 ), /* Radeon X1600 */ + RHD_DEVICE_MATCH( 0x7183, RHD_RV516 ), /* Radeon X1300/X1550 */ + RHD_DEVICE_MATCH( 0x7186, RHD_M64 ), /* Mobility Radeon X1450 */ + RHD_DEVICE_MATCH( 0x7187, RHD_RV516 ), /* Radeon X1300/X1550 */ + RHD_DEVICE_MATCH( 0x7188, RHD_M64 ), /* Mobility Radeon X2300 */ + RHD_DEVICE_MATCH( 0x718A, RHD_M64 ), /* Mobility Radeon X2300 */ + RHD_DEVICE_MATCH( 0x718B, RHD_M62 ), /* Mobility Radeon X1350 */ + RHD_DEVICE_MATCH( 0x718C, RHD_M62 ), /* Mobility Radeon X1350 */ + RHD_DEVICE_MATCH( 0x718D, RHD_M64 ), /* Mobility Radeon X1450 */ + RHD_DEVICE_MATCH( 0x718F, RHD_RV516 ), /* Radeon X1300 */ + RHD_DEVICE_MATCH( 0x7193, RHD_RV516 ), /* Radeon X1550 */ + RHD_DEVICE_MATCH( 0x7196, RHD_M62 ), /* Mobility Radeon X1350 */ + RHD_DEVICE_MATCH( 0x719B, RHD_RV516 ), /* FireMV 2250 */ + RHD_DEVICE_MATCH( 0x719F, RHD_RV516 ), /* Radeon X1550 64-bit */ + RHD_DEVICE_MATCH( 0x71C0, RHD_RV530 ), /* Radeon X1600 */ + RHD_DEVICE_MATCH( 0x71C1, RHD_RV535 ), /* Radeon X1650 */ + RHD_DEVICE_MATCH( 0x71C2, RHD_RV530 ), /* Radeon X1600 */ + RHD_DEVICE_MATCH( 0x71C3, RHD_RV535 ), /* Radeon X1600 */ + RHD_DEVICE_MATCH( 0x71C4, RHD_M56 ), /* Mobility FireGL V5200 */ + RHD_DEVICE_MATCH( 0x71C5, RHD_M56 ), /* Mobility Radeon X1600 */ + RHD_DEVICE_MATCH( 0x71C6, RHD_RV530 ), /* Radeon X1650 */ + RHD_DEVICE_MATCH( 0x71C7, RHD_RV535 ), /* Radeon X1650 */ + RHD_DEVICE_MATCH( 0x71CD, RHD_RV530 ), /* Radeon X1600 */ + RHD_DEVICE_MATCH( 0x71CE, RHD_RV530 ), /* Radeon X1300 XT/X1600 Pro */ + RHD_DEVICE_MATCH( 0x71D2, RHD_RV530 ), /* FireGL V3400 */ + RHD_DEVICE_MATCH( 0x71D4, RHD_M66 ), /* Mobility FireGL V5250 */ + RHD_DEVICE_MATCH( 0x71D5, RHD_M66 ), /* Mobility Radeon X1700 */ + RHD_DEVICE_MATCH( 0x71D6, RHD_M66 ), /* Mobility Radeon X1700 XT */ + RHD_DEVICE_MATCH( 0x71DA, RHD_RV530 ), /* FireGL V5200 */ + RHD_DEVICE_MATCH( 0x71DE, RHD_M66 ), /* Mobility Radeon X1700 */ + RHD_DEVICE_MATCH( 0x7200, RHD_RV550 ), /* Radeon X2300HD */ + RHD_DEVICE_MATCH( 0x7210, RHD_M71 ), /* Mobility Radeon HD 2300 */ + RHD_DEVICE_MATCH( 0x7211, RHD_M71 ), /* Mobility Radeon HD 2300 */ + RHD_DEVICE_MATCH( 0x7240, RHD_R580 ), /* Radeon X1950 */ + RHD_DEVICE_MATCH( 0x7243, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7244, RHD_R580 ), /* Radeon X1950 */ + RHD_DEVICE_MATCH( 0x7245, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7246, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7247, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7248, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7249, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x724A, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x724B, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x724C, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x724D, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x724E, RHD_R580 ), /* AMD Stream Processor */ + RHD_DEVICE_MATCH( 0x724F, RHD_R580 ), /* Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7280, RHD_RV570 ), /* Radeon X1950 */ + RHD_DEVICE_MATCH( 0x7281, RHD_RV560 ), /* RV560 */ + RHD_DEVICE_MATCH( 0x7283, RHD_RV560 ), /* RV560 */ + RHD_DEVICE_MATCH( 0x7284, RHD_M68 ), /* Mobility Radeon X1900 */ + RHD_DEVICE_MATCH( 0x7287, RHD_RV560 ), /* RV560 */ + RHD_DEVICE_MATCH( 0x7288, RHD_RV570 ), /* Radeon X1950 GT */ + RHD_DEVICE_MATCH( 0x7289, RHD_RV570 ), /* RV570 */ + RHD_DEVICE_MATCH( 0x728B, RHD_RV570 ), /* RV570 */ + RHD_DEVICE_MATCH( 0x728C, RHD_RV570 ), /* ATI FireGL V7400 */ + RHD_DEVICE_MATCH( 0x7290, RHD_RV560 ), /* RV560 */ + RHD_DEVICE_MATCH( 0x7291, RHD_RV560 ), /* Radeon X1650 */ + RHD_DEVICE_MATCH( 0x7293, RHD_RV560 ), /* Radeon X1650 */ + RHD_DEVICE_MATCH( 0x7297, RHD_RV560 ), /* RV560 */ + RHD_DEVICE_MATCH( 0x791E, RHD_RS690 ), /* Radeon X1200 */ + RHD_DEVICE_MATCH( 0x791F, RHD_RS690 ), /* Radeon X1200 */ + RHD_DEVICE_MATCH( 0x793F, RHD_RS600 ), /* Radeon Xpress 1200 */ + RHD_DEVICE_MATCH( 0x7941, RHD_RS600 ), /* Radeon Xpress 1200 */ + RHD_DEVICE_MATCH( 0x7942, RHD_RS600 ), /* Radeon Xpress 1200 (M) */ + RHD_DEVICE_MATCH( 0x796C, RHD_RS740 ), /* RS740 */ + RHD_DEVICE_MATCH( 0x796D, RHD_RS740 ), /* RS740M */ + RHD_DEVICE_MATCH( 0x796E, RHD_RS740 ), /* ATI Radeon 2100 RS740 */ + RHD_DEVICE_MATCH( 0x796F, RHD_RS740 ), /* RS740M */ + RHD_DEVICE_MATCH( 0x9400, RHD_R600 ), /* Radeon HD 2900 XT */ + RHD_DEVICE_MATCH( 0x9401, RHD_R600 ), /* Radeon HD 2900 XT */ + RHD_DEVICE_MATCH( 0x9402, RHD_R600 ), /* Radeon HD 2900 XT */ + RHD_DEVICE_MATCH( 0x9403, RHD_R600 ), /* Radeon HD 2900 Pro */ + RHD_DEVICE_MATCH( 0x9405, RHD_R600 ), /* Radeon HD 2900 GT */ + RHD_DEVICE_MATCH( 0x940A, RHD_R600 ), /* FireGL V8650 */ + RHD_DEVICE_MATCH( 0x940B, RHD_R600 ), /* FireGL V8600 */ + RHD_DEVICE_MATCH( 0x940F, RHD_R600 ), /* FireGL V7600 */ + RHD_DEVICE_MATCH( 0x94C0, RHD_RV610 ), /* RV610 */ + RHD_DEVICE_MATCH( 0x94C1, RHD_RV610 ), /* Radeon HD 2400 XT */ + RHD_DEVICE_MATCH( 0x94C3, RHD_RV610 ), /* Radeon HD 2400 Pro */ + RHD_DEVICE_MATCH( 0x94C4, RHD_RV610 ), /* ATI Radeon HD 2400 PRO AGP */ + RHD_DEVICE_MATCH( 0x94C5, RHD_RV610 ), /* FireGL V4000 */ + RHD_DEVICE_MATCH( 0x94C6, RHD_RV610 ), /* RV610 */ + RHD_DEVICE_MATCH( 0x94C7, RHD_RV610 ), /* ATI Radeon HD 2350 */ + RHD_DEVICE_MATCH( 0x94C8, RHD_M74 ), /* Mobility Radeon HD 2400 XT */ + RHD_DEVICE_MATCH( 0x94C9, RHD_M72 ), /* Mobility Radeon HD 2400 */ + RHD_DEVICE_MATCH( 0x94CB, RHD_M72 ), /* ATI RADEON E2400 */ + RHD_DEVICE_MATCH( 0x94CC, RHD_RV610 ), /* ATI Radeon HD 2400 */ + RHD_DEVICE_MATCH( 0x9500, RHD_RV670 ), /* RV670 */ + RHD_DEVICE_MATCH( 0x9501, RHD_RV670 ), /* ATI Radeon HD3870 */ + RHD_DEVICE_MATCH( 0x9505, RHD_RV670 ), /* ATI Radeon HD3850 */ + RHD_DEVICE_MATCH( 0x9507, RHD_RV670 ), /* RV670 */ + RHD_DEVICE_MATCH( 0x950F, RHD_R680 ), /* ATI Radeon HD3870 X2 */ + RHD_DEVICE_MATCH( 0x9511, RHD_RV670 ), /* ATI FireGL V7700 */ + RHD_DEVICE_MATCH( 0x9515, RHD_RV670 ), /* ATI Radeon HD 3850 AGP */ + RHD_DEVICE_MATCH( 0x9580, RHD_RV630 ), /* RV630 */ + RHD_DEVICE_MATCH( 0x9581, RHD_M76 ), /* Mobility Radeon HD 2600 */ + RHD_DEVICE_MATCH( 0x9583, RHD_M76 ), /* Mobility Radeon HD 2600 XT */ + RHD_DEVICE_MATCH( 0x9586, RHD_RV630 ), /* ATI Radeon HD 2600 XT AGP */ + RHD_DEVICE_MATCH( 0x9587, RHD_RV630 ), /* ATI Radeon HD 2600 Pro AGP */ + RHD_DEVICE_MATCH( 0x9588, RHD_RV630 ), /* Radeon HD 2600 XT */ + RHD_DEVICE_MATCH( 0x9589, RHD_RV630 ), /* Radeon HD 2600 Pro */ + RHD_DEVICE_MATCH( 0x958A, RHD_RV630 ), /* Gemini RV630 */ + RHD_DEVICE_MATCH( 0x958B, RHD_M76 ), /* Gemini ATI Mobility Radeon HD 2600 XT */ + RHD_DEVICE_MATCH( 0x958C, RHD_RV630 ), /* FireGL V5600 */ + RHD_DEVICE_MATCH( 0x958D, RHD_RV630 ), /* FireGL V3600 */ + RHD_DEVICE_MATCH( 0x958E, RHD_RV630 ), /* ATI Radeon HD 2600 LE */ + RHD_DEVICE_MATCH( 0x9590, RHD_RV635 ), /* ATI Radeon HD 3600 Series */ + RHD_DEVICE_MATCH( 0x9591, RHD_RV635 ), /* ATI Mobility Radeon HD 3650 */ + RHD_DEVICE_MATCH( 0x9596, RHD_RV635 ), /* ATI Radeon HD 3650 AGP */ + RHD_DEVICE_MATCH( 0x9597, RHD_RV635 ), /* ATI Radeon HD 3600 Series */ + RHD_DEVICE_MATCH( 0x9598, RHD_RV635 ), /* ATI Radeon HD 3670 */ + RHD_DEVICE_MATCH( 0x9599, RHD_RV635 ), /* ATI Radeon HD 3600 Series */ + RHD_DEVICE_MATCH( 0x95C0, RHD_RV620 ), /* ATI Radeon HD 3470 */ + RHD_DEVICE_MATCH( 0x95C2, RHD_M82 ), /* ATI Mobility Radeon HD 3430 (M82) */ + RHD_DEVICE_MATCH( 0x95C4, RHD_M82 ), /* ATI Mobility Radeon HD 3400 Series (M82) */ + RHD_DEVICE_MATCH( 0x95C5, RHD_RV620 ), /* ATI Radeon HD 3450 */ + RHD_DEVICE_MATCH( 0x95C7, RHD_RV620 ), /* ATI Radeon HD 3430 */ + RHD_DEVICE_MATCH( 0x95CD, RHD_RV620 ), /* ATI FireMV 2450 */ + RHD_DEVICE_MATCH( 0x95CE, RHD_RV620 ), /* ATI FireMV 2260 */ + RHD_DEVICE_MATCH( 0x95CF, RHD_RV620 ), /* ATI FireMV 2260 */ + LIST_END +}; + +const char * +xf86TokenToString(SymTabPtr table, int token) +{ + int i; + + for (i = 0; table[i].token >= 0 && table[i].token != token; i++){}; + + if (table[i].token < 0) + return NULL; + else + return(table[i].name); +} + +RHDPtr FindPciDevice() +{ + const PciChipset_t *dev; + u32 bus, last_bus; + + if( (last_bus = PciApi(1))==-1) + return 0; + + for(bus=0;bus<=last_bus;bus++) + { + u32 devfn; + + for(devfn=0;devfn<256;devfn++) + { + u32 id; + id = PciRead32(bus,devfn, 0); + + if( (CARD16)id != VENDOR_ATI) + continue; + + if( (dev=PciDevMatch(id>>16,RHDPCIchipsets))!=NULL) + { + CARD32 reg2C; + int i; + + rhd.PciDeviceID = (id>>16); + + rhd.bus = bus; + rhd.devfn = devfn; + rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); + + rhd.ChipSet = dev->ChipSet; + + reg2C = PciRead32(bus,devfn, 0x2C); + + rhd.subvendor_id = reg2C & 0xFFFF;; + rhd.subdevice_id = reg2C >> 16; + + for (i = 0; i < 6; i++) + { + CARD32 base; + Bool validSize; + + base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2)); + if(base) + { + if (base & PCI_MAP_IO) + { + rhd.ioBase[i] = (CARD32)PCIGETIO(base); + rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; + } + else + { + rhd.memBase[i] = (CARD32)PCIGETMEMORY(base); + rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; + } + } + rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); + } + rhd.ChipName = (char*)xf86TokenToString(RHDChipsets, rhd.PciDeviceID); + + return &rhd; + } + }; + }; + return NULL; +} + +const PciChipset_t *PciDevMatch(CARD16 dev,const PciChipset_t *list) +{ + while(list->device) + { + if(dev==list->device) + return list; + list++; + } + return 0; +} + + +CARD32 pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min) +{ + int offset; + CARD32 addr1; + CARD32 addr2; + CARD32 mask1; + CARD32 mask2; + int bits = 0; + + /* + * silently ignore bogus index values. Valid values are 0-6. 0-5 are + * the 6 base address registers, and 6 is the ROM base address register. + */ + if (index < 0 || index > 6) + return 0; + + if (min) + *min = destructive; + + /* Get the PCI offset */ + if (index == 6) + offset = PCI_MAP_ROM_REG; + else + offset = PCI_MAP_REG_START + (index << 2); + + addr1 = PciRead32(bus, devfn, offset); + /* + * Check if this is the second part of a 64 bit address. + * XXX need to check how endianness affects 64 bit addresses. + */ + if (index > 0 && index < 6) { + addr2 = PciRead32(bus, devfn, offset - 4); + if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) + return 0; + } + + if (destructive) { + PciWrite32(bus, devfn, offset, 0xffffffff); + mask1 = PciRead32(bus, devfn, offset); + PciWrite32(bus, devfn, offset, addr1); + } else { + mask1 = addr1; + } + + /* Check if this is the first part of a 64 bit address. */ + if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) + { + if (PCIGETMEMORY(mask1) == 0) + { + addr2 = PciRead32(bus, devfn, offset + 4); + if (destructive) + { + PciWrite32(bus, devfn, offset + 4, 0xffffffff); + mask2 = PciRead32(bus, devfn, offset + 4); + PciWrite32(bus, devfn, offset + 4, addr2); + } + else + { + mask2 = addr2; + } + if (mask2 == 0) + return 0; + bits = 32; + while ((mask2 & 1) == 0) + { + bits++; + mask2 >>= 1; + } + if (bits > 32) + return bits; + } + } + if (index < 6) + if (PCI_MAP_IS_MEM(mask1)) + mask1 = PCIGETMEMORY(mask1); + else + mask1 = PCIGETIO(mask1); + else + mask1 = PCIGETROM(mask1); + if (mask1 == 0) + return 0; + bits = 0; + while ((mask1 & 1) == 0) { + bits++; + mask1 >>= 1; + } + /* I/O maps can be no larger than 8 bits */ + + if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8) + bits = 8; + /* ROM maps can be no larger than 24 bits */ + if (index == 6 && bits > 24) + bits = 24; + return bits; +} + + diff --git a/programs/system/drivers/ati2d/pci.h b/programs/system/drivers/ati2d/pci.h new file mode 100644 index 0000000000..6cb4f89063 --- /dev/null +++ b/programs/system/drivers/ati2d/pci.h @@ -0,0 +1,79 @@ + + +#pragma pack(push, 1) +typedef struct +{ + CARD16 device; + CARD16 ChipSet; +}PciChipset_t; +#pragma pack(pop) + +#define VENDOR_ATI 0x1002 + + +#define PCI_MAP_REG_START 0x10 +#define PCI_MAP_REG_END 0x28 +#define PCI_MAP_ROM_REG 0x30 + +#define PCI_MAP_MEMORY 0x00000000 +#define PCI_MAP_IO 0x00000001 + +#define PCI_MAP_MEMORY_TYPE 0x00000007 +#define PCI_MAP_IO_TYPE 0x00000003 + +#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 +#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 +#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 +#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 +#define PCI_MAP_MEMORY_CACHABLE 0x00000008 +#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e +#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 + +#define PCI_MAP_IO_ATTR_MASK 0x00000003 + +#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) +#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) + +#define PCI_MAP_IS64BITMEM(b) \ + (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) + +#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) +#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) +#define PCIGETMEMORY64(b) \ + (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) + +#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc + +#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) + +#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 +#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 + +#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) + + +#ifndef PCI_DOM_MASK +# define PCI_DOM_MASK 0x0ffu +#endif +#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) + +#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ + (((d) & 0x00001fu) << 11) | \ + (((f) & 0x000007u) << 8)) + +#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) +#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) +#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) +#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) + + +typedef unsigned int PCITAG; + +extern inline PCITAG +pciTag(int busnum, int devnum, int funcnum) +{ + return(PCI_MAKE_TAG(busnum,devnum,funcnum)); +} + +const PciChipset_t *PciDevMatch(CARD16 dev,const PciChipset_t *list); +CARD32 pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min); diff --git a/programs/system/drivers/ati2d/proc32.inc b/programs/system/drivers/ati2d/proc32.inc new file mode 100644 index 0000000000..f623e7273d --- /dev/null +++ b/programs/system/drivers/ati2d/proc32.inc @@ -0,0 +1,269 @@ + + +; Macroinstructions for defining and calling procedures + +macro stdcall proc,[arg] ; directly call STDCALL procedure + { common + if ~ arg eq + reverse + pushd arg + common + end if + call proc } + +macro invoke proc,[arg] ; indirectly call STDCALL procedure + { common + if ~ arg eq + reverse + pushd arg + common + end if + call [proc] } + +macro ccall proc,[arg] ; directly call CDECL procedure + { common + size@ccall = 0 + if ~ arg eq + reverse + pushd arg + size@ccall = size@ccall+4 + common + end if + call proc + if size@ccall + add esp,size@ccall + end if } + +macro cinvoke proc,[arg] ; indirectly call CDECL procedure + { common + size@ccall = 0 + if ~ arg eq + reverse + pushd arg + size@ccall = size@ccall+4 + common + end if + call [proc] + if size@ccall + add esp,size@ccall + end if } + +macro proc [args] ; define procedure + { common + match name params, args> + \{ define@proc name, \{ prologue name,flag,parmbytes,localbytes,reglist \} + macro locals + \{ virtual at ebp-localbytes+current + macro label . \\{ deflocal@proc .,:, \\} + struc db [val] \\{ \common deflocal@proc .,db,val \\} + struc dw [val] \\{ \common deflocal@proc .,dw,val \\} + struc dp [val] \\{ \common deflocal@proc .,dp,val \\} + struc dd [val] \\{ \common deflocal@proc .,dd,val \\} + struc dt [val] \\{ \common deflocal@proc .,dt,val \\} + struc dq [val] \\{ \common deflocal@proc .,dq,val \\} + struc rb cnt \\{ deflocal@proc .,rb cnt, \\} + struc rw cnt \\{ deflocal@proc .,rw cnt, \\} + struc rp cnt \\{ deflocal@proc .,rp cnt, \\} + struc rd cnt \\{ deflocal@proc .,rd cnt, \\} + struc rt cnt \\{ deflocal@proc .,rt cnt, \\} + struc rq cnt \\{ deflocal@proc .,rq cnt, \\} \} + macro endl + \{ purge label + restruc db,dw,dp,dd,dt,dq + restruc rb,rw,rp,rd,rt,rq + restruc byte,word,dword,pword,tword,qword + current = $-(ebp-localbytes) + end virtual \} + macro ret operand + \{ match any, operand \\{ retn operand \\} + match , operand \\{ match epilogue:reglist, epilogue@proc: + \\\{ epilogue name,flag,parmbytes,localbytes,reglist \\\} \\} \} + macro finish@proc \{ localbytes = (((current-1) shr 2)+1) shl 2 + end if \} } + +macro defargs@proc [arg] + { common + if ~ arg eq + forward + local ..arg,current@arg + match argname:type, arg + \{ current@arg equ argname + label ..arg type + argname equ ..arg + if dqword eq type + dd ?,?,?,? + else if tbyte eq type + dd ?,?,? + else if qword eq type | pword eq type + dd ?,? + else + dd ? + end if \} + match =current@arg,current@arg + \{ current@arg equ arg + arg equ ..arg + ..arg dd ? \} + common + args@proc equ current@arg + forward + restore current@arg + common + end if } + +macro deflocal@proc name,def,[val] + { common + match vars, all@vars \{ all@vars equ all@vars, \} + all@vars equ all@vars name + forward + local ..var,..tmp + ..var def val + match =?, val \{ ..tmp equ \} + match any =dup (=?), val \{ ..tmp equ \} + match tmp : value, ..tmp : val + \{ tmp: end virtual + initlocal@proc ..var,def value + virtual at tmp\} + common + match first rest, ..var, \{ name equ first \} } + +macro initlocal@proc name,def + { virtual at name + def + size@initlocal = $ - name + end virtual + position@initlocal = 0 + while size@initlocal > position@initlocal + virtual at name + def + if size@initlocal - position@initlocal < 2 + current@initlocal = 1 + load byte@initlocal byte from name+position@initlocal + else if size@initlocal - position@initlocal < 4 + current@initlocal = 2 + load word@initlocal word from name+position@initlocal + else + current@initlocal = 4 + load dword@initlocal dword from name+position@initlocal + end if + end virtual + if current@initlocal = 1 + mov byte [name+position@initlocal],byte@initlocal + else if current@initlocal = 2 + mov word [name+position@initlocal],word@initlocal + else + mov dword [name+position@initlocal],dword@initlocal + end if + position@initlocal = position@initlocal + current@initlocal + end while } + +macro endp + { purge ret,locals,endl + finish@proc + purge finish@proc + restore regs@proc + match all,args@proc \{ restore all \} + restore args@proc + match all,all@vars \{ restore all \} } + +macro local [var] + { common + locals + forward done@local equ + match varname[count]:vartype, var + \{ match =BYTE, vartype \\{ varname rb count + restore done@local \\} + match =WORD, vartype \\{ varname rw count + restore done@local \\} + match =DWORD, vartype \\{ varname rd count + restore done@local \\} + match =PWORD, vartype \\{ varname rp count + restore done@local \\} + match =QWORD, vartype \\{ varname rq count + restore done@local \\} + match =TBYTE, vartype \\{ varname rt count + restore done@local \\} + match =DQWORD, vartype \\{ label varname dqword + rq count+count + restore done@local \\} + match , done@local \\{ virtual + varname vartype + end virtual + rb count*sizeof.\#vartype + restore done@local \\} \} + match :varname:vartype, done@local:var + \{ match =BYTE, vartype \\{ varname db ? + restore done@local \\} + match =WORD, vartype \\{ varname dw ? + restore done@local \\} + match =DWORD, vartype \\{ varname dd ? + restore done@local \\} + match =PWORD, vartype \\{ varname dp ? + restore done@local \\} + match =QWORD, vartype \\{ varname dq ? + restore done@local \\} + match =TBYTE, vartype \\{ varname dt ? + restore done@local \\} + match =DQWORD, vartype \\{ label varname dqword + dq ?,? + restore done@local \\} + match , done@local \\{ varname vartype + restore done@local \\} \} + match ,done@local + \{ var + restore done@local \} + common + endl } diff --git a/programs/system/drivers/ati2d/r500.inc b/programs/system/drivers/ati2d/r500.inc new file mode 100644 index 0000000000..9214acc8be --- /dev/null +++ b/programs/system/drivers/ati2d/r500.inc @@ -0,0 +1,313 @@ + +#include "r5xx_regs.h" + +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) + + +#define RADEON_SCRATCH_UMSK 0x0770 +#define RADEON_SCRATCH_ADDR 0x0774 + +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_AIC_CNTL 0x01d0 +#define RADEON_PCIGART_TRANSLATE_EN (1 << 0) + + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +# define RADEON_BUF_SWAP_32BIT (2 << 16) +# define RADEON_RB_NO_UPDATE (1 << 27) +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_CP_IB_BASE 0x0738 + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) + +#define RADEON_ISYNC_CNTL 0x1724 +# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) +# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) +# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) +# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) +# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) +# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) + +#define R5XX_LOOP_COUNT 2000000 + +#include "microcode.h" + +static Bool +R5xxFIFOWaitLocal(CARD32 required) //R100-R500 +{ + int i; + + for (i = 0; i < R5XX_LOOP_COUNT; i++) + if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) + return TRUE; + + dbgprintf("%s: Timeout 0x%08X.\n", __func__, + (unsigned int) INREG(R5XX_RBBM_STATUS)); + return FALSE; +} + +/* + * Flush all dirty data in the Pixel Cache to memory. + */ + +static Bool +R5xx2DFlush() +{ + int i; + + MASKREG(R5XX_DSTCACHE_CTLSTAT, + R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); + + for (i = 0; i < R5XX_LOOP_COUNT; i++) + if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) + return TRUE; + + dbgprintf("%s: Timeout 0x%08x.\n", __func__, + (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); + return FALSE; +} + +static Bool +R5xx2DIdleLocal() //R100-R500 +{ + int i; + + /* wait for fifo to clear */ + for (i = 0; i < R5XX_LOOP_COUNT; i++) + if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) + break; + + if (i == R5XX_LOOP_COUNT) { + dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); + return FALSE; + } + + /* wait for engine to go idle */ + for (i = 0; i < R5XX_LOOP_COUNT; i++) { + if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { + R5xx2DFlush(); + return TRUE; + } + } + dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); + return FALSE; + +} + +static void +R5xx2DReset() +{ + CARD32 save, tmp; + + /* The following RBBM_SOFT_RESET sequence can help un-wedge + * an R300 after the command processor got stuck. */ + save = INREG(R5XX_RBBM_SOFT_RESET); + tmp = save | R5XX_SOFT_RESET_CP | + R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE | + R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP | + R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB; + OUTREG(R5XX_RBBM_SOFT_RESET, tmp); + + INREG(R5XX_RBBM_SOFT_RESET); + tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | + R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE | + R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 | + R5XX_SOFT_RESET_RB); + OUTREG(R5XX_RBBM_SOFT_RESET, tmp); + + INREG(R5XX_RBBM_SOFT_RESET); + OUTREG(R5XX_RBBM_SOFT_RESET, save); + INREG(R5XX_RBBM_SOFT_RESET); + + R5xx2DFlush(); + + /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some + * unexpected behaviour on some machines. Here we use + * R5XX_HOST_PATH_CNTL to reset it. */ + save = INREG(R5XX_HOST_PATH_CNTL); + + tmp = INREG(R5XX_RBBM_SOFT_RESET); + tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2; + OUTREG(R5XX_RBBM_SOFT_RESET, tmp); + + INREG(R5XX_RBBM_SOFT_RESET); + OUTREG(R5XX_RBBM_SOFT_RESET, 0); + + MASKREG(R5XX_RB2D_DSTCACHE_MODE, + R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, + R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); + + OUTREG(R5XX_HOST_PATH_CNTL, save | R5XX_HDP_SOFT_RESET); + INREG(R5XX_HOST_PATH_CNTL); + OUTREG(R5XX_HOST_PATH_CNTL, save); +} + +void +R5xx2DSetup() +{ + + /* Setup engine location. This shouldn't be necessary since we + * set them appropriately before any accel ops, but let's avoid + * random bogus DMA in case we inadvertently trigger the engine + * in the wrong place (happened). */ + R5xxFIFOWaitLocal(2); + OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); + OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); + + R5xxFIFOWaitLocal(1); + MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); + + OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl); + + R5xxFIFOWaitLocal(1); + OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT, + R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX); + R5xxFIFOWaitLocal(1); + OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | + R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR); + + R5xxFIFOWaitLocal(5); + OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); + OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000); + OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF); + OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000); + OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); + + R5xx2DIdleLocal(); +} + +void R5xxFIFOWait(CARD32 required) +{ + if (!R5xxFIFOWaitLocal(required)) { + R5xx2DReset(); + R5xx2DSetup(); + } +} + +void R5xx2DIdle() +{ + if (!R5xx2DIdleLocal()) { + R5xx2DReset(); + R5xx2DSetup(); + } +} + +static void load_microcode() +{ + u32 ifl; + int i; + + ifl = safe_cli(); + + R5xx2DIdleLocal(); + OUTREG(RADEON_CP_ME_RAM_ADDR,0); + for (i = 0; i < 256; i++) + { + OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); + OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); + } + safe_sti(ifl); +}; + + +void R5xx2DInit() +{ + u32 base; + + rhd.displayWidth = INREG(D1GRPH_X_END); + rhd.displayHeight = INREG(D1GRPH_Y_END); + + rhd.__xmin = 0; + rhd.__ymin = 0; + rhd.__xmax = rhd.displayWidth - 1; + rhd.__ymax = rhd.displayHeight - 1; + + clip.xmin = 0; + clip.ymin = 0; + clip.xmax = rhd.displayWidth - 1; + clip.ymax = rhd.displayHeight - 1; + + dbgprintf("width %d \n", rhd.displayWidth); + dbgprintf("height %d \n", rhd.displayHeight); + + rhd.gui_control = (R5XX_DATATYPE_ARGB8888 << R5XX_GMC_DST_DATATYPE_SHIFT) | + R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL; + + dbgprintf("gui_control %x \n", rhd.gui_control); + + rhd.surface_cntl = 0; + rhd.dst_pitch_offset = (((rhd.displayWidth * 4) / 64) << 22) | + ((rhd.FbIntAddress + rhd.FbScanoutStart) >> 10); + + dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset); + + MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING); + OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN); + MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG); + MASKREG(R5XX_RB2D_DSTCACHE_MODE, + R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE, + R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE); + + + R5xx2DReset(); + R5xx2DSetup(); + + MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN); + + load_microcode(); + + rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE); + dbgprintf("create cp ring buffer %x\n", rhd.ring_base); + base = GetPgAddr(rhd.ring_base); + + OUTREG(RADEON_CP_RB_BASE, base); + dbgprintf("ring base %x\n", base); + + OUTREG(RADEON_CP_RB_WPTR_DELAY, 0); + + rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); + OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); + + OUTREG(RADEON_CP_RB_RPTR_ADDR, 0); // ring buffer read pointer no update + + OUTREG(RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE | 12); + OUTREG(RADEON_SCRATCH_UMSK, 0); // no scratch update + + MASKREG(RADEON_BUS_CNTL,0,RADEON_BUS_MASTER_DIS); + + R5xx2DIdleLocal(); + + OUTREG(RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D | + RADEON_ISYNC_ANY3D_IDLE2D | + RADEON_ISYNC_WAIT_IDLEGUI | + RADEON_ISYNC_CPSCRATCH_IDLEGUI); + + OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); // run + + + // OUTREG(D1CUR_SIZE, (31<<16)|31); + // OUTREG(D1CUR_CONTROL, 0x300); +} + + + diff --git a/programs/system/drivers/ati2d/r5xx_regs.h b/programs/system/drivers/ati2d/r5xx_regs.h new file mode 100644 index 0000000000..d408f584b3 --- /dev/null +++ b/programs/system/drivers/ati2d/r5xx_regs.h @@ -0,0 +1,273 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* WARNING: the above is not a standard MIT license. */ +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + */ + +#ifndef _R5XX_2DREGS_H +# define _R5XX_2DREGS_H + +#define R5XX_DATATYPE_VQ 0 +#define R5XX_DATATYPE_CI4 1 +#define R5XX_DATATYPE_CI8 2 +#define R5XX_DATATYPE_ARGB1555 3 +#define R5XX_DATATYPE_RGB565 4 +#define R5XX_DATATYPE_RGB888 5 +#define R5XX_DATATYPE_ARGB8888 6 +#define R5XX_DATATYPE_RGB332 7 +#define R5XX_DATATYPE_Y8 8 +#define R5XX_DATATYPE_RGB8 9 +#define R5XX_DATATYPE_CI16 10 +#define R5XX_DATATYPE_VYUY_422 11 +#define R5XX_DATATYPE_YVYU_422 12 +#define R5XX_DATATYPE_AYUV_444 14 +#define R5XX_DATATYPE_ARGB4444 15 + +#define R5XX_RBBM_SOFT_RESET 0x00f0 +# define R5XX_SOFT_RESET_CP (1 << 0) +# define R5XX_SOFT_RESET_HI (1 << 1) +# define R5XX_SOFT_RESET_SE (1 << 2) +# define R5XX_SOFT_RESET_RE (1 << 3) +# define R5XX_SOFT_RESET_PP (1 << 4) +# define R5XX_SOFT_RESET_E2 (1 << 5) +# define R5XX_SOFT_RESET_RB (1 << 6) +# define R5XX_SOFT_RESET_HDP (1 << 7) + +#define R5XX_HOST_PATH_CNTL 0x0130 +# define R5XX_HDP_SOFT_RESET (1 << 26) +# define R5XX_HDP_APER_CNTL (1 << 23) + +#define R5XX_SURFACE_CNTL 0x0b00 +# define R5XX_SURF_TRANSLATION_DIS (1 << 8) +# define R5XX_NONSURF_AP0_SWP_16BPP (1 << 20) +# define R5XX_NONSURF_AP0_SWP_32BPP (1 << 21) +# define R5XX_NONSURF_AP1_SWP_16BPP (1 << 22) +# define R5XX_NONSURF_AP1_SWP_32BPP (1 << 23) + +#define R5XX_SURFACE0_INFO 0x0b0c +# define R5XX_SURF_TILE_COLOR_MACRO (0 << 16) +# define R5XX_SURF_TILE_COLOR_BOTH (1 << 16) +# define R5XX_SURF_TILE_DEPTH_32BPP (2 << 16) +# define R5XX_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R5XX_SURF_AP0_SWP_16BPP (1 << 20) +# define R5XX_SURF_AP0_SWP_32BPP (1 << 21) +# define R5XX_SURF_AP1_SWP_16BPP (1 << 22) +# define R5XX_SURF_AP1_SWP_32BPP (1 << 23) +#define R5XX_SURFACE0_LOWER_BOUND 0x0b04 +#define R5XX_SURFACE0_UPPER_BOUND 0x0b08 + +#define R5XX_RBBM_STATUS 0x0e40 +# define R5XX_RBBM_FIFOCNT_MASK 0x007f +# define R5XX_RBBM_ACTIVE (1 << 31) + +#define R5XX_SRC_PITCH_OFFSET 0x1428 +#define R5XX_DST_PITCH_OFFSET 0x142c + +#define R5XX_SRC_Y_X 0x1434 +#define R5XX_DST_Y_X 0x1438 +#define R5XX_DST_HEIGHT_WIDTH 0x143c + +#define R5XX_DP_GUI_MASTER_CNTL 0x146c +# define R5XX_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define R5XX_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define R5XX_GMC_SRC_CLIPPING (1 << 2) +# define R5XX_GMC_DST_CLIPPING (1 << 3) +# define R5XX_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +# define R5XX_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +# define R5XX_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +# define R5XX_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +# define R5XX_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +# define R5XX_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +# define R5XX_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +# define R5XX_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +# define R5XX_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +# define R5XX_GMC_BRUSH_8x8_COLOR (10 << 4) +# define R5XX_GMC_BRUSH_1X8_COLOR (12 << 4) +# define R5XX_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define R5XX_GMC_BRUSH_NONE (15 << 4) +# define R5XX_GMC_DST_8BPP_CI (2 << 8) +# define R5XX_GMC_DST_15BPP (3 << 8) +# define R5XX_GMC_DST_16BPP (4 << 8) +# define R5XX_GMC_DST_24BPP (5 << 8) +# define R5XX_GMC_DST_32BPP (6 << 8) +# define R5XX_GMC_DST_8BPP_RGB (7 << 8) +# define R5XX_GMC_DST_Y8 (8 << 8) +# define R5XX_GMC_DST_RGB8 (9 << 8) +# define R5XX_GMC_DST_VYUY (11 << 8) +# define R5XX_GMC_DST_YVYU (12 << 8) +# define R5XX_GMC_DST_AYUV444 (14 << 8) +# define R5XX_GMC_DST_ARGB4444 (15 << 8) +# define R5XX_GMC_DST_DATATYPE_MASK (0x0f << 8) +# define R5XX_GMC_DST_DATATYPE_SHIFT 8 +# define R5XX_GMC_SRC_DATATYPE_MASK (3 << 12) +# define R5XX_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +# define R5XX_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +# define R5XX_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define R5XX_GMC_BYTE_PIX_ORDER (1 << 14) +# define R5XX_GMC_BYTE_MSB_TO_LSB (0 << 14) +# define R5XX_GMC_BYTE_LSB_TO_MSB (1 << 14) +# define R5XX_GMC_CONVERSION_TEMP (1 << 15) +# define R5XX_GMC_CONVERSION_TEMP_6500 (0 << 15) +# define R5XX_GMC_CONVERSION_TEMP_9300 (1 << 15) +# define R5XX_GMC_ROP3_MASK (0xff << 16) +# define R5XX_DP_SRC_SOURCE_MASK (7 << 24) +# define R5XX_DP_SRC_SOURCE_MEMORY (2 << 24) +# define R5XX_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define R5XX_GMC_3D_FCN_EN (1 << 27) +# define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define R5XX_GMC_AUX_CLIP_DIS (1 << 29) +# define R5XX_GMC_WR_MSK_DIS (1 << 30) +# define R5XX_GMC_LD_BRUSH_Y_X (1 << 31) +# define R5XX_ROP3_ZERO 0x00000000 +# define R5XX_ROP3_DSa 0x00880000 +# define R5XX_ROP3_SDna 0x00440000 +# define R5XX_ROP3_S 0x00cc0000 +# define R5XX_ROP3_DSna 0x00220000 +# define R5XX_ROP3_D 0x00aa0000 +# define R5XX_ROP3_DSx 0x00660000 +# define R5XX_ROP3_DSo 0x00ee0000 +# define R5XX_ROP3_DSon 0x00110000 +# define R5XX_ROP3_DSxn 0x00990000 +# define R5XX_ROP3_Dn 0x00550000 +# define R5XX_ROP3_SDno 0x00dd0000 +# define R5XX_ROP3_Sn 0x00330000 +# define R5XX_ROP3_DSno 0x00bb0000 +# define R5XX_ROP3_DSan 0x00770000 +# define R5XX_ROP3_ONE 0x00ff0000 +# define R5XX_ROP3_DPa 0x00a00000 +# define R5XX_ROP3_PDna 0x00500000 +# define R5XX_ROP3_P 0x00f00000 +# define R5XX_ROP3_DPna 0x000a0000 +# define R5XX_ROP3_D 0x00aa0000 +# define R5XX_ROP3_DPx 0x005a0000 +# define R5XX_ROP3_DPo 0x00fa0000 +# define R5XX_ROP3_DPon 0x00050000 +# define R5XX_ROP3_PDxn 0x00a50000 +# define R5XX_ROP3_PDno 0x00f50000 +# define R5XX_ROP3_Pn 0x000f0000 +# define R5XX_ROP3_DPno 0x00af0000 +# define R5XX_ROP3_DPan 0x005f0000 + +#define R5XX_BRUSH_Y_X 0x1474 +#define R5XX_DP_BRUSH_BKGD_CLR 0x1478 +#define R5XX_DP_BRUSH_FRGD_CLR 0x147c +#define R5XX_BRUSH_DATA0 0x1480 +#define R5XX_BRUSH_DATA1 0x1484 + +#define R5XX_DST_WIDTH_HEIGHT 0x1598 + +#define R5XX_CLR_CMP_CNTL 0x15c0 +# define R5XX_SRC_CMP_EQ_COLOR (4 << 0) +# define R5XX_SRC_CMP_NEQ_COLOR (5 << 0) +# define R5XX_CLR_CMP_SRC_SOURCE (1 << 24) + +#define R5XX_CLR_CMP_CLR_SRC 0x15c4 + +#define R5XX_CLR_CMP_MASK 0x15cc +# define R5XX_CLR_CMP_MSK 0xffffffff + +#define R5XX_DP_SRC_BKGD_CLR 0x15dc +#define R5XX_DP_SRC_FRGD_CLR 0x15d8 + +#define R5XX_DST_LINE_START 0x1600 +#define R5XX_DST_LINE_END 0x1604 +#define R5XX_DST_LINE_PATCOUNT 0x1608 +# define R5XX_BRES_CNTL_SHIFT 8 + +#define R5XX_DP_CNTL 0x16c0 +# define R5XX_DST_X_LEFT_TO_RIGHT (1 << 0) +# define R5XX_DST_Y_TOP_TO_BOTTOM (1 << 1) +# define R5XX_DP_DST_TILE_LINEAR (0 << 3) +# define R5XX_DP_DST_TILE_MACRO (1 << 3) +# define R5XX_DP_DST_TILE_MICRO (2 << 3) +# define R5XX_DP_DST_TILE_BOTH (3 << 3) + +#define R5XX_DP_DATATYPE 0x16c4 +# define R5XX_HOST_BIG_ENDIAN_EN (1 << 29) + +#define R5XX_DP_WRITE_MASK 0x16cc + +#define R5XX_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +# define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) + +#define R5XX_SC_TOP_LEFT 0x16ec +#define R5XX_SC_BOTTOM_RIGHT 0x16f0 +# define R5XX_SC_SIGN_MASK_LO 0x8000 +# define R5XX_SC_SIGN_MASK_HI 0x80000000 + +#define R5XX_DST_PIPE_CONFIG 0x170c +# define R5XX_PIPE_AUTO_CONFIG (1 << 31) + +#define R5XX_DSTCACHE_CTLSTAT 0x1714 +# define R5XX_DSTCACHE_FLUSH_2D (1 << 0) +# define R5XX_DSTCACHE_FREE_2D (1 << 2) +# define R5XX_DSTCACHE_FLUSH_ALL (R5XX_DSTCACHE_FLUSH_2D | R5XX_DSTCACHE_FREE_2D) +# define R5XX_DSTCACHE_BUSY (1 << 31) + +#define R5XX_WAIT_UNTIL 0x1720 +# define R5XX_WAIT_2D_IDLECLEAN (1 << 16) +# define R5XX_WAIT_3D_IDLECLEAN (1 << 17) + +#define R5XX_RBBM_GUICNTL 0x172c +# define R5XX_HOST_DATA_SWAP_NONE (0 << 0) +# define R5XX_HOST_DATA_SWAP_16BIT (1 << 0) +# define R5XX_HOST_DATA_SWAP_32BIT (2 << 0) +# define R5XX_HOST_DATA_SWAP_HDW (3 << 0) + +#define R5XX_HOST_DATA0 0x17c0 +#define R5XX_HOST_DATA1 0x17c4 +#define R5XX_HOST_DATA2 0x17c8 +#define R5XX_HOST_DATA3 0x17cc +#define R5XX_HOST_DATA4 0x17d0 +#define R5XX_HOST_DATA5 0x17d4 +#define R5XX_HOST_DATA6 0x17d8 +#define R5XX_HOST_DATA7 0x17dc +#define R5XX_HOST_DATA_LAST 0x17e0 + +#define R5XX_RB2D_DSTCACHE_MODE 0x3428 +# define R5XX_RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) +# define R5XX_RB2D_DC_DISABLE_IGNORE_PE (1 << 17) + +#define R5XX_GB_TILE_CONFIG 0x4018 +# define R5XX_ENABLE_TILING (1 << 0) +# define R5XX_PIPE_COUNT_RV350 (0 << 1) +# define R5XX_PIPE_COUNT_R300 (3 << 1) +# define R5XX_PIPE_COUNT_R420_3P (6 << 1) +# define R5XX_PIPE_COUNT_R420 (7 << 1) +# define R5XX_TILE_SIZE_8 (0 << 4) +# define R5XX_TILE_SIZE_16 (1 << 4) +# define R5XX_TILE_SIZE_32 (2 << 4) +# define R5XX_SUBPIXEL_1_12 (0 << 16) +# define R5XX_SUBPIXEL_1_16 (1 << 16) + +#endif /* _R5XX_2DREGS_H */ diff --git a/programs/system/drivers/ati2d/rhd_regs.h b/programs/system/drivers/ati2d/rhd_regs.h new file mode 100644 index 0000000000..f3ba1d9489 --- /dev/null +++ b/programs/system/drivers/ati2d/rhd_regs.h @@ -0,0 +1,836 @@ +/* + * Copyright 2007, 2008 Luc Verhaegen + * Copyright 2007, 2008 Matthias Hopf + * Copyright 2007, 2008 Egbert Eich + * Copyright 2007, 2008 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _RHD_REGS_H +# define _RHD_REGS_H + +enum { + CLOCK_CNTL_INDEX = 0x8, /* (RW) */ + CLOCK_CNTL_DATA = 0xC, /* (RW) */ + BUS_CNTL = 0x4C, /* (RW) */ + MC_IND_INDEX = 0x70, /* (RW) */ + MC_IND_DATA = 0x74, /* (RW) */ + CONFIG_CNTL = 0xE0, + /* RS690 ?? */ + RS69_MC_INDEX = 0xE8, + RS69_MC_DATA = 0xEC, + R5XX_CONFIG_MEMSIZE = 0x00F8, + + HDP_FB_LOCATION = 0x0134, + + SEPROM_CNTL1 = 0x1C0, /* (RW) */ + GPIOPAD_MASK = 0x198, /* (RW) */ + GPIOPAD_A = 0x19C, /* (RW) */ + GPIOPAD_EN = 0x1A0, /* (RW) */ + VIPH_CONTROL = 0xC40, /* (RW) */ + + /* VGA registers */ + VGA_RENDER_CONTROL = 0x0300, + VGA_MODE_CONTROL = 0x0308, + VGA_MEMORY_BASE_ADDRESS = 0x0310, + VGA_HDP_CONTROL = 0x0328, + D1VGA_CONTROL = 0x0330, + D2VGA_CONTROL = 0x0338, + + EXT1_PPLL_REF_DIV_SRC = 0x0400, + EXT1_PPLL_REF_DIV = 0x0404, + EXT1_PPLL_UPDATE_LOCK = 0x0408, + EXT1_PPLL_UPDATE_CNTL = 0x040C, + EXT2_PPLL_REF_DIV_SRC = 0x0410, + EXT2_PPLL_REF_DIV = 0x0414, + EXT2_PPLL_UPDATE_LOCK = 0x0418, + EXT2_PPLL_UPDATE_CNTL = 0x041C, + + EXT1_PPLL_FB_DIV = 0x0430, + EXT2_PPLL_FB_DIV = 0x0434, + EXT1_PPLL_POST_DIV_SRC = 0x0438, + EXT1_PPLL_POST_DIV = 0x043C, + EXT2_PPLL_POST_DIV_SRC = 0x0440, + EXT2_PPLL_POST_DIV = 0x0444, + EXT1_PPLL_CNTL = 0x0448, + EXT2_PPLL_CNTL = 0x044C, + P1PLL_CNTL = 0x0450, + P2PLL_CNTL = 0x0454, + P1PLL_INT_SS_CNTL = 0x0458, + P2PLL_INT_SS_CNTL = 0x045C, + + P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */ + P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */ + EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */ + EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */ + + PCLK_CRTC1_CNTL = 0x0480, + PCLK_CRTC2_CNTL = 0x0484, + + DCCG_DISP_CLK_SRCSEL = 0x0538, /* rv620+ */ + + R6XX_MC_VM_FB_LOCATION = 0x2180, + R6XX_HDP_NONSURFACE_BASE = 0x2C04, + R6XX_CONFIG_MEMSIZE = 0x5428, + R6XX_CONFIG_FB_BASE = 0x542C, /* AKA CONFIG_F0_BASE */ + + /* CRTC1 registers */ + D1CRTC_H_TOTAL = 0x6000, + D1CRTC_H_BLANK_START_END = 0x6004, + D1CRTC_H_SYNC_A = 0x6008, + D1CRTC_H_SYNC_A_CNTL = 0x600C, + D1CRTC_H_SYNC_B = 0x6010, + D1CRTC_H_SYNC_B_CNTL = 0x6014, + + D1CRTC_V_TOTAL = 0x6020, + D1CRTC_V_BLANK_START_END = 0x6024, + D1CRTC_V_SYNC_A = 0x6028, + D1CRTC_V_SYNC_A_CNTL = 0x602C, + D1CRTC_V_SYNC_B = 0x6030, + D1CRTC_V_SYNC_B_CNTL = 0x6034, + + D1CRTC_CONTROL = 0x6080, + D1CRTC_BLANK_CONTROL = 0x6084, + D1CRTC_INTERLACE_CONTROL = 0x6088, + D1CRTC_BLACK_COLOR = 0x6098, + D1CRTC_STATUS = 0x609C, + D1CRTC_COUNT_CONTROL = 0x60B4, + + /* D1GRPH registers */ + D1GRPH_ENABLE = 0x6100, + D1GRPH_CONTROL = 0x6104, + D1GRPH_LUT_SEL = 0x6108, + D1GRPH_SWAP_CNTL = 0x610C, + D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, + D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118, + D1GRPH_PITCH = 0x6120, + D1GRPH_SURFACE_OFFSET_X = 0x6124, + D1GRPH_SURFACE_OFFSET_Y = 0x6128, + D1GRPH_X_START = 0x612C, + D1GRPH_Y_START = 0x6130, + D1GRPH_X_END = 0x6134, + D1GRPH_Y_END = 0x6138, + D1GRPH_UPDATE = 0x6144, + + /* LUT */ + DC_LUT_RW_SELECT = 0x6480, + DC_LUT_RW_MODE = 0x6484, + DC_LUT_RW_INDEX = 0x6488, + DC_LUT_SEQ_COLOR = 0x648C, + DC_LUT_PWL_DATA = 0x6490, + DC_LUT_30_COLOR = 0x6494, + DC_LUT_READ_PIPE_SELECT = 0x6498, + DC_LUT_WRITE_EN_MASK = 0x649C, + DC_LUT_AUTOFILL = 0x64A0, + + /* LUTA */ + DC_LUTA_CONTROL = 0x64C0, + DC_LUTA_BLACK_OFFSET_BLUE = 0x64C4, + DC_LUTA_BLACK_OFFSET_GREEN = 0x64C8, + DC_LUTA_BLACK_OFFSET_RED = 0x64CC, + DC_LUTA_WHITE_OFFSET_BLUE = 0x64D0, + DC_LUTA_WHITE_OFFSET_GREEN = 0x64D4, + DC_LUTA_WHITE_OFFSET_RED = 0x64D8, + + /* D1CUR */ + D1CUR_CONTROL = 0x6400, + D1CUR_SURFACE_ADDRESS = 0x6408, + D1CUR_SIZE = 0x6410, + D1CUR_POSITION = 0x6414, + D1CUR_HOT_SPOT = 0x6418, + D1CUR_UPDATE = 0x6424, + + /* D1MODE */ + D1MODE_DESKTOP_HEIGHT = 0x652C, + D1MODE_VIEWPORT_START = 0x6580, + D1MODE_VIEWPORT_SIZE = 0x6584, + D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588, + D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C, + D1MODE_DATA_FORMAT = 0x6528, + + /* D1SCL */ + D1SCL_ENABLE = 0x6590, + D1SCL_TAP_CONTROL = 0x6594, + D1MODE_CENTER = 0x659C, /* guess */ + D1SCL_HVSCALE = 0x65A4, /* guess */ + D1SCL_HFILTER = 0x65B0, /* guess */ + D1SCL_VFILTER = 0x65C0, /* guess */ + D1SCL_UPDATE = 0x65CC, + D1SCL_DITHER = 0x65D4, /* guess */ + D1SCL_FLIP_CONTROL = 0x65D8, /* guess */ + + /* CRTC2 registers */ + D2CRTC_H_TOTAL = 0x6800, + D2CRTC_H_BLANK_START_END = 0x6804, + D2CRTC_H_SYNC_A = 0x6808, + D2CRTC_H_SYNC_A_CNTL = 0x680C, + D2CRTC_H_SYNC_B = 0x6810, + D2CRTC_H_SYNC_B_CNTL = 0x6814, + + D2CRTC_V_TOTAL = 0x6820, + D2CRTC_V_BLANK_START_END = 0x6824, + D2CRTC_V_SYNC_A = 0x6828, + D2CRTC_V_SYNC_A_CNTL = 0x682C, + D2CRTC_V_SYNC_B = 0x6830, + D2CRTC_V_SYNC_B_CNTL = 0x6834, + + D2CRTC_CONTROL = 0x6880, + D2CRTC_BLANK_CONTROL = 0x6884, + D2CRTC_BLACK_COLOR = 0x6898, + D2CRTC_INTERLACE_CONTROL = 0x6888, + D2CRTC_STATUS = 0x689C, + D2CRTC_COUNT_CONTROL = 0x68B4, + + /* D2GRPH registers */ + D2GRPH_ENABLE = 0x6900, + D2GRPH_CONTROL = 0x6904, + D2GRPH_LUT_SEL = 0x6908, + D2GRPH_SWAP_CNTL = 0x690C, + D2GRPH_PRIMARY_SURFACE_ADDRESS = 0x6910, + D2GRPH_PITCH = 0x6920, + D2GRPH_SURFACE_OFFSET_X = 0x6924, + D2GRPH_SURFACE_OFFSET_Y = 0x6928, + D2GRPH_X_START = 0x692C, + D2GRPH_Y_START = 0x6930, + D2GRPH_X_END = 0x6934, + D2GRPH_Y_END = 0x6938, + + /* LUTB */ + DC_LUTB_CONTROL = 0x6CC0, + DC_LUTB_BLACK_OFFSET_BLUE = 0x6CC4, + DC_LUTB_BLACK_OFFSET_GREEN = 0x6CC8, + DC_LUTB_BLACK_OFFSET_RED = 0x6CCC, + DC_LUTB_WHITE_OFFSET_BLUE = 0x6CD0, + DC_LUTB_WHITE_OFFSET_GREEN = 0x6CD4, + DC_LUTB_WHITE_OFFSET_RED = 0x6CD8, + + /* D2MODE */ + D2MODE_DESKTOP_HEIGHT = 0x6D2C, + D2MODE_VIEWPORT_START = 0x6D80, + D2MODE_VIEWPORT_SIZE = 0x6D84, + D2MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6D88, + D2MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x6D8C, + D2MODE_DATA_FORMAT = 0x6D28, + + /* D2SCL */ + D2SCL_ENABLE = 0x6D90, + D2SCL_TAP_CONTROL = 0x6D94, + D2MODE_CENTER = 0x6D9C, /* guess */ + D2SCL_HVSCALE = 0x6DA4, /* guess */ + D2SCL_HFILTER = 0x6DB0, /* guess */ + D2SCL_VFILTER = 0x6DC0, /* guess */ + D2SCL_UPDATE = 0x6DCC, + D2SCL_DITHER = 0x6DD4, /* guess */ + D2SCL_FLIP_CONTROL = 0x6DD8, /* guess */ + + /* R500 DAC A */ + DACA_ENABLE = 0x7800, + DACA_SOURCE_SELECT = 0x7804, + DACA_SYNC_TRISTATE_CONTROL = 0x7820, + DACA_SYNC_SELECT = 0x7824, + DACA_AUTODETECT_CONTROL = 0x7828, + DACA_FORCE_OUTPUT_CNTL = 0x783C, + DACA_FORCE_DATA = 0x7840, + DACA_POWERDOWN = 0x7850, + DACA_CONTROL1 = 0x7854, + DACA_CONTROL2 = 0x7858, + DACA_COMPARATOR_ENABLE = 0x785C, + DACA_COMPARATOR_OUTPUT = 0x7860, + +/* TMDSA */ + TMDSA_CNTL = 0x7880, + TMDSA_SOURCE_SELECT = 0x7884, + TMDSA_COLOR_FORMAT = 0x7888, + TMDSA_FORCE_OUTPUT_CNTL = 0x788C, + TMDSA_BIT_DEPTH_CONTROL = 0x7894, + TMDSA_DCBALANCER_CONTROL = 0x78D0, + TMDSA_DATA_SYNCHRONIZATION_R500 = 0x78D8, + TMDSA_DATA_SYNCHRONIZATION_R600 = 0x78DC, + TMDSA_TRANSMITTER_ENABLE = 0x7904, + TMDSA_LOAD_DETECT = 0x7908, + TMDSA_MACRO_CONTROL = 0x790C, /* r5x0 and r600: 3 for pll and 1 for TX */ + TMDSA_PLL_ADJUST = 0x790C, /* rv6x0: pll only */ + TMDSA_TRANSMITTER_CONTROL = 0x7910, + TMDSA_TRANSMITTER_ADJUST = 0x7920, /* rv6x0: TX part of macro control */ + + /* DAC B */ + DACB_ENABLE = 0x7A00, + DACB_SOURCE_SELECT = 0x7A04, + DACB_SYNC_TRISTATE_CONTROL = 0x7A20, + DACB_SYNC_SELECT = 0x7A24, + DACB_AUTODETECT_CONTROL = 0x7A28, + DACB_FORCE_OUTPUT_CNTL = 0x7A3C, + DACB_FORCE_DATA = 0x7A40, + DACB_POWERDOWN = 0x7A50, + DACB_CONTROL1 = 0x7A54, + DACB_CONTROL2 = 0x7A58, + DACB_COMPARATOR_ENABLE = 0x7A5C, + DACB_COMPARATOR_OUTPUT = 0x7A60, + + /* LVTMA */ + LVTMA_CNTL = 0x7A80, + LVTMA_SOURCE_SELECT = 0x7A84, + LVTMA_COLOR_FORMAT = 0x7A88, + LVTMA_FORCE_OUTPUT_CNTL = 0x7A8C, + LVTMA_BIT_DEPTH_CONTROL = 0x7A94, + LVTMA_DCBALANCER_CONTROL = 0x7AD0, + + /* no longer shared between both r5xx and r6xx */ + LVTMA_R500_DATA_SYNCHRONIZATION = 0x7AD8, + LVTMA_R500_PWRSEQ_REF_DIV = 0x7AE4, + LVTMA_R500_PWRSEQ_DELAY1 = 0x7AE8, + LVTMA_R500_PWRSEQ_DELAY2 = 0x7AEC, + LVTMA_R500_PWRSEQ_CNTL = 0x7AF0, + LVTMA_R500_PWRSEQ_STATE = 0x7AF4, + LVTMA_R500_LVDS_DATA_CNTL = 0x7AFC, + LVTMA_R500_MODE = 0x7B00, + LVTMA_R500_TRANSMITTER_ENABLE = 0x7B04, + LVTMA_R500_MACRO_CONTROL = 0x7B0C, + LVTMA_R500_TRANSMITTER_CONTROL = 0x7B10, + LVTMA_R500_REG_TEST_OUTPUT = 0x7B14, + + /* R600 adds an undocumented register at 0x7AD8, + * shifting all subsequent registers by exactly one. */ + LVTMA_R600_DATA_SYNCHRONIZATION = 0x7ADC, + LVTMA_R600_PWRSEQ_REF_DIV = 0x7AE8, + LVTMA_R600_PWRSEQ_DELAY1 = 0x7AEC, + LVTMA_R600_PWRSEQ_DELAY2 = 0x7AF0, + LVTMA_R600_PWRSEQ_CNTL = 0x7AF4, + LVTMA_R600_PWRSEQ_STATE = 0x7AF8, + LVTMA_R600_LVDS_DATA_CNTL = 0x7B00, + LVTMA_R600_MODE = 0x7B04, + LVTMA_R600_TRANSMITTER_ENABLE = 0x7B08, + LVTMA_R600_MACRO_CONTROL = 0x7B10, + LVTMA_R600_TRANSMITTER_CONTROL = 0x7B14, + LVTMA_R600_REG_TEST_OUTPUT = 0x7B18, + + LVTMA_TRANSMITTER_ADJUST = 0x7B24, /* RV630 */ + LVTMA_PREEMPHASIS_CONTROL = 0x7B28, /* RV630 */ + + /* I2C in separate enum */ + + /* HPD */ + DC_GPIO_HPD_MASK = 0x7E90, + DC_GPIO_HPD_A = 0x7E94, + DC_GPIO_HPD_EN = 0x7E98, + DC_GPIO_HPD_Y = 0x7E9C +}; + +enum CONFIG_CNTL_BITS { + RS69_CFG_ATI_REV_ID_SHIFT = 8, + RS69_CFG_ATI_REV_ID_MASK = 0xF << RS69_CFG_ATI_REV_ID_SHIFT +}; + +enum rv620Regs { + /* DAC common */ + RV620_DAC_COMPARATOR_MISC = 0x7da4, + RV620_DAC_COMPARATOR_OUTPUT = 0x7da8, + + /* RV620 DAC A */ + RV620_DACA_ENABLE = 0x7000, + RV620_DACA_SOURCE_SELECT = 0x7004, + RV620_DACA_SYNC_TRISTATE_CONTROL = 0x7020, + /* RV620_DACA_SYNC_SELECT = 0x7024, ?? */ + RV620_DACA_AUTODETECT_CONTROL = 0x7028, + RV620_DACA_AUTODETECT_STATUS = 0x7034, + RV620_DACA_AUTODETECT_INT_CONTROL = 0x7038, + RV620_DACA_FORCE_OUTPUT_CNTL = 0x703C, + RV620_DACA_FORCE_DATA = 0x7040, + RV620_DACA_POWERDOWN = 0x7050, + /* RV620_DACA_CONTROL1 moved */ + RV620_DACA_CONTROL2 = 0x7058, + RV620_DACA_COMPARATOR_ENABLE = 0x705C, + /* RV620_DACA_COMPARATOR_OUTPUT changed */ + RV620_DACA_BGADJ_SRC = 0x7ef0, + RV620_DACA_MACRO_CNTL = 0x7ef4, + RV620_DACA_AUTO_CALIB_CONTROL = 0x7ef8, + + /* DAC B */ + RV620_DACB_ENABLE = 0x7100, + RV620_DACB_SOURCE_SELECT = 0x7104, + RV620_DACB_SYNC_TRISTATE_CONTROL = 0x7120, + /* RV620_DACB_SYNC_SELECT = 0x7124, ?? */ + RV620_DACB_AUTODETECT_CONTROL = 0x7128, + RV620_DACB_AUTODETECT_STATUS = 0x7134, + RV620_DACB_AUTODETECT_INT_CONTROL = 0x7138, + RV620_DACB_FORCE_OUTPUT_CNTL = 0x713C, + RV620_DACB_FORCE_DATA = 0x7140, + RV620_DACB_POWERDOWN = 0x7150, + /* RV620_DACB_CONTROL1 moved */ + RV620_DACB_CONTROL2 = 0x7158, + RV620_DACB_COMPARATOR_ENABLE = 0x715C, + RV620_DACB_BGADJ_SRC = 0x7ef0, + RV620_DACB_MACRO_CNTL = 0x7ff4, + RV620_DACB_AUTO_CALIB_CONTROL = 0x7ef8, + /* DIG1 */ + RV620_DIG1_CNTL = 0x75A0, + RV620_DIG1_CLOCK_PATTERN = 0x75AC, + RV620_LVDS1_DATA_CNTL = 0x75BC, + RV620_TMDS1_CNTL = 0x75C0, + /* DIG2 */ + RV620_DIG2_CNTL = 0x79A0, + RV620_DIG2_CLOCK_PATTERN = 0x79AC, + RV620_LVDS2_DATA_CNTL = 0x79BC, + RV620_TMDS2_CNTL = 0x79C0, + + /* RV62x I2C */ + RV62_GENERIC_I2C_CONTROL = 0x7d80, /* (RW) */ + RV62_GENERIC_I2C_INTERRUPT_CONTROL = 0x7d84, /* (RW) */ + RV62_GENERIC_I2C_STATUS = 0x7d88, /* (RW) */ + RV62_GENERIC_I2C_SPEED = 0x7d8c, /* (RW) */ + RV62_GENERIC_I2C_SETUP = 0x7d90, /* (RW) */ + RV62_GENERIC_I2C_TRANSACTION = 0x7d94, /* (RW) */ + RV62_GENERIC_I2C_DATA = 0x7d98, /* (RW) */ + RV62_GENERIC_I2C_PIN_SELECTION = 0x7d9c, /* (RW) */ + RV62_DC_GPIO_DDC4_MASK = 0x7e20, /* (RW) */ + RV62_DC_GPIO_DDC1_MASK = 0x7e40, /* (RW) */ + RV62_DC_GPIO_DDC2_MASK = 0x7e50, /* (RW) */ + RV62_DC_GPIO_DDC3_MASK = 0x7e60, /* (RW) */ + + /* ?? */ + RV620_DCIO_LINK_STEER_CNTL = 0x7FA4, + + RV620_LVTMA_TRANSMITTER_CONTROL= 0x7F00, + RV620_LVTMA_TRANSMITTER_ENABLE = 0x7F04, + RV620_LVTMA_TRANSMITTER_ADJUST = 0x7F18, + RV620_LVTMA_PREEMPHASIS_CONTROL= 0x7F1C, + RV620_LVTMA_MACRO_CONTROL = 0x7F0C, + RV620_LVTMA_DATA_SYNCHRONIZATION = 0x7F98, + + RV620_FMT1_CONTROL = 0x6700, + RV620_FMT1_BIT_DEPTH_CONTROL= 0x6710, + RV620_FMT1_CLAMP_CNTL = 0x672C, + RV620_FMT2_CONTROL = 0x6F00, + RV620_FMT2_CNTL = 0x6F10, + RV620_FMT2_CLAMP_CNTL = 0x6F2C, + + RV620_DCCG_PCLK_DIGA_CNTL = 0x04b0, + RV620_DCCG_PCLK_DIGB_CNTL = 0x04b4, + RV620_DCCG_SYMCLK_CNTL = 0x04b8 +}; + +enum RV620_LVTMA_TRANSMITTER_CONTROL_BITS { + RV62_LVTMA_PLL_ENABLE = 1 << 0, + RV62_LVTMA_PLL_RESET = 1 << 1, + RV62_LVTMA_IDSCKSEL = 1 << 4, + RV62_LVTMA_BGSLEEP = 1 << 5, + RV62_LVTMA_IDCLK_SEL = 1 << 6, + RV62_LVTMA_TMCLK = 1 << 8, + RV62_LVTMA_TMCLK_FROM_PADS = 1 << 13, + RV62_LVTMA_TDCLK = 1 << 14, + RV62_LVTMA_TDCLK_FROM_PADS = 1 << 15, + RV62_LVTMA_BYPASS_PLL = 1 << 28, + RV62_LVTMA_USE_CLK_DATA = 1 << 29, + RV62_LVTMA_MODE = 1 << 30, + RV62_LVTMA_INPUT_TEST_CLK_SEL = 1 << 31 +}; + +enum RV620_DCCG_SYMCLK_CNTL { + RV62_SYMCLKA_SRC_SHIFT = 8, + RV62_SYMCLKB_SRC_SHIFT = 12 +}; + +enum RV620_DCCG_DIG_CNTL { + RV62_PCLK_DIGA_ON = 0x1 +}; + +enum RV620_DCIO_LINK_STEER_CNTL { + RV62_LINK_STEER_SWAP = 1 << 0, + RV62_LINK_STEER_PLLSEL_OVERWRITE_EN = 1 << 16, + RV62_LINK_STEER_PLLSELA = 1 << 17, + RV62_LINK_STEER_PLLSELB = 1 << 18 +}; + +enum R620_LVTMA_TRANSMITTER_ENABLE_BITS { + RV62_LVTMA_LNK0EN = 1 << 0, + RV62_LVTMA_LNK1EN = 1 << 1, + RV62_LVTMA_LNK2EN = 1 << 2, + RV62_LVTMA_LNK3EN = 1 << 3, + RV62_LVTMA_LNK4EN = 1 << 4, + RV62_LVTMA_LNK5EN = 1 << 5, + RV62_LVTMA_LNK6EN = 1 << 6, + RV62_LVTMA_LNK7EN = 1 << 7, + RV62_LVTMA_LNK8EN = 1 << 8, + RV62_LVTMA_LNK9EN = 1 << 9, + RV62_LVTMA_LNKL = RV62_LVTMA_LNK0EN | RV62_LVTMA_LNK1EN + | RV62_LVTMA_LNK2EN | RV62_LVTMA_LNK3EN, + RV62_LVTMA_LNKU = RV62_LVTMA_LNK4EN | RV62_LVTMA_LNK5EN + | RV62_LVTMA_LNK6EN | RV62_LVTMA_LNK7EN, + RV62_LVTMA_LNK_ALL = RV62_LVTMA_LNKL | RV62_LVTMA_LNKU + | RV62_LVTMA_LNK8EN | RV62_LVTMA_LNK9EN, + RV62_LVTMA_LNKEN_HPD_MASK = 1 << 16 +}; + +enum RV620_LVTMA_DATA_SYNCHRONIZATION { + RV62_LVTMA_DSYNSEL = (1 << 0), + RV62_LVTMA_PFREQCHG = (1 << 8) +}; + + +enum RV620_DIG_CNTL_BITS { + /* 0x75A0 */ + RV62_DIG_SWAP = (0x1 << 16), + RV62_DIG_DUAL_LINK_ENABLE = (0x1 << 12), + RV62_DIG_START = (0x1 << 6), + RV62_DIG_MODE = (0x7 << 8), + RV62_DIG_STEREOSYNC_SELECT = (1 << 2), + RV62_DIG_SOURCE_SELECT = (1 << 0) +}; + +enum RV620_DIG_LVDS_DATA_CNTL_BITS { + /* 0x75BC */ + RV62_LVDS_24BIT_ENABLE = (0x1 << 0), + RV62_LVDS_24BIT_FORMAT = (0x1 << 4) +}; + +enum RV620_TMDS_CNTL_BITS { + /* 0x75C0 */ + RV62_TMDS_PIXEL_ENCODING = (0x1 << 4), + RV62_TMDS_COLOR_FORMAT = (0x3 << 8) +}; + +enum RV620_FMT_BIT_DEPTH_CONTROL { + RV62_FMT_TRUNCATE_EN = 1 << 0, + RV62_FMT_TRUNCATE_DEPTH = 1 << 4, + RV62_FMT_SPATIAL_DITHER_EN = 1 << 8, + RV62_FMT_SPATIAL_DITHER_MODE = 1 << 9, + RV62_FMT_SPATIAL_DITHER_DEPTH = 1 << 12, + RV62_FMT_FRAME_RANDOM_ENABLE = 1 << 13, + RV62_FMT_RGB_RANDOM_ENABLE = 1 << 14, + RV62_FMT_HIGHPASS_RANDOM_ENABLE = 1 << 15, + RV62_FMT_TEMPORAL_DITHER_EN = 1 << 16, + RV62_FMT_TEMPORAL_DITHER_DEPTH = 1 << 20, + RV62_FMT_TEMPORAL_DITHER_OFFSET = 3 << 21, + RV62_FMT_TEMPORAL_LEVEL = 1 << 24, + RV62_FMT_TEMPORAL_DITHER_RESET = 1 << 25, + RV62_FMT_25FRC_SEL = 3 << 26, + RV62_FMT_50FRC_SEL = 3 << 28, + RV62_FMT_75FRC_SEL = 3 << 30 +}; + +enum RV620_FMT_CONTROL { + RV62_FMT_PIXEL_ENCODING = 1 << 16 +}; + +enum _r5xxMCRegs { + R5XX_MC_STATUS = 0x0000, + RV515_MC_FB_LOCATION = 0x0001, + R5XX_MC_FB_LOCATION = 0x0004, + RV515_MC_STATUS = 0x0008 +}; + +enum _r5xxRegs { + /* I2C */ + R5_DC_I2C_STATUS1 = 0x7D30, /* (RW) */ + R5_DC_I2C_RESET = 0x7D34, /* (RW) */ + R5_DC_I2C_CONTROL1 = 0x7D38, /* (RW) */ + R5_DC_I2C_CONTROL2 = 0x7D3C, /* (RW) */ + R5_DC_I2C_CONTROL3 = 0x7D40, /* (RW) */ + R5_DC_I2C_DATA = 0x7D44, /* (RW) */ + R5_DC_I2C_INTERRUPT_CONTROL = 0x7D48, /* (RW) */ + R5_DC_I2C_ARBITRATION = 0x7D50, /* (RW) */ + + R5_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ + R5_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ + R5_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ + R5_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ + R5_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ + R5_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ + R5_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ + R5_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ + R5_DC_GPIO_DDC3_EN = 0x7E68 /* (RW) */ +}; + +enum _r5xxSPLLRegs { + SPLL_FUNC_CNTL = 0x0 /* (RW) */ +}; + +enum _r6xxRegs { + /* MCLK */ + R6_MCLK_PWRMGT_CNTL = 0x620, + /* I2C */ + R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */ + R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */ + R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ + R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */ + R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */ + R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */ + R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */ + R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */ + R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */ + R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */ + R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */ + R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */ + R6_DC_I2C_DATA = 0x7D74, /* (RW) */ + R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */ + R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */ + R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */ + R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */ + R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */ + R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ + R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ + R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ + R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */ + R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ + R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ + R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ + R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */ + R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ + R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ + R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */ + R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */ +}; + +enum R6_MCLK_PWRMGT_CNTL { + R6_MC_BUSY = (1 << 5) +}; + + +/* *_Q: questionbable */ +enum _rs69xRegs { + /* I2C */ + RS69_DC_I2C_CONTROL = 0x7D30, /* (RW) *//* */ + RS69_DC_I2C_UNKNOWN_2 = 0x7D34, /* (RW) */ + RS69_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ + RS69_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) *//**/ + RS69_DC_I2C_UNKNOWN_1 = 0x7d40, + RS69_DC_I2C_DDC_SETUP_Q = 0x7D44, /* (RW) */ + RS69_DC_I2C_DATA = 0x7D58, /* (RW) *//**/ + RS69_DC_I2C_TRANSACTION0 = 0x7D48, /* (RW) *//**/ + RS69_DC_I2C_TRANSACTION1 = 0x7D4C, /* (RW) *//**/ + /* DDIA */ + RS69_DDIA_CNTL = 0x7200, + RS69_DDIA_SOURCE_SELECT = 0x7204, + RS69_DDIA_BIT_DEPTH_CONTROL = 0x7214, + RS69_DDIA_DCBALANCER_CONTROL = 0x7250, + RS69_DDIA_PATH_CONTROL = 0x7264, + RS69_DDIA_PCIE_LINK_CONTROL2 = 0x7278, + RS69_DDIA_PCIE_LINK_CONTROL3 = 0x727c, + RS69_DDIA_PCIE_PHY_CONTROL1 = 0x728c, + RS69_DDIA_PCIE_PHY_CONTROL2 = 0x7290 +}; + +enum RS69_DDIA_CNTL_BITS { + RS69_DDIA_ENABLE = 1 << 0, + RS69_DDIA_HDMI_EN = 1 << 2, + RS69_DDIA_ENABLE_HPD_MASK = 1 << 4, + RS69_DDIA_HPD_SELECT = 1 << 8, + RS69_DDIA_SYNC_PHASE = 1 << 12, + RS69_DDIA_PIXEL_ENCODING = 1 << 16, + RS69_DDIA_DUAL_LINK_ENABLE = 1 << 24, + RS69_DDIA_SWAP = 1 << 28 +}; + +enum RS69_DDIA_SOURCE_SELECT_BITS { + RS69_DDIA_SOURCE_SELECT_BIT = 1 << 0, + RS69_DDIA_SYNC_SELECT = 1 << 8, + RS69_DDIA_STEREOSYNC_SELECT = 1 << 16 +}; + +enum RS69_DDIA_LINK_CONTROL2_SHIFT { + RS69_DDIA_PCIE_OUTPUT_MUX_SEL0 = 0, + RS69_DDIA_PCIE_OUTPUT_MUX_SEL1 = 4, + RS69_DDIA_PCIE_OUTPUT_MUX_SEL2 = 8, + RS69_DDIA_PCIE_OUTPUT_MUX_SEL3 = 12 +}; + +enum RS69_DDIA_BIT_DEPTH_CONTROL_BITS { + RS69_DDIA_TRUNCATE_EN = 1 << 0, + RS69_DDIA_TRUNCATE_DEPTH = 1 << 4, + RS69_DDIA_SPATIAL_DITHER_EN = 1 << 8, + RS69_DDIA_SPATIAL_DITHER_DEPTH = 1 << 12, + RS69_DDIA_TEMPORAL_DITHER_EN = 1 << 16, + RS69_DDIA_TEMPORAL_DITHER_DEPTH = 1 << 20, + RS69_DDIA_TEMPORAL_LEVEL = 1 << 24, + RS69_DDIA_TEMPORAL_DITHER_RESET = 1 << 25 +}; + +enum RS69_DDIA_DCBALANCER_CONTROL_BITS { + RS69_DDIA_DCBALANCER_EN = 1 << 0, + RS69_DDIA_SYNC_DCBAL_EN = 1 << 4, + RS69_DDIA_DCBALANCER_TEST_EN = 1 << 8, + RS69_DDIA_DCBALANCER_TEST_IN_SHIFT = 16, + RS69_DDIA_DCBALANCER_FORCE = 1 << 24 +}; + +enum RS69_DDIA_PATH_CONTROL_BITS { + RS69_DDIA_PATH_SELECT_SHIFT = 0, + RS69_DDIA_DDPII_DE_ALIGN_EN = 1 << 4, + RS69_DDIA_DDPII_TRAIN_EN = 1 << 8, + RS69_DDIA_DDPII_TRAIN_SELECT = 1 << 12, + RS69_DDIA_DDPII_SCRAMBLE_EN = 1 << 16, + RS69_DDIA_REPL_MODE_SELECT = 1 << 20, + RS69_DDIA_RB_30b_SWAP_EN = 1 << 24, + RS69_DDIA_PIXVLD_RESET = 1 << 28, + RS69_DDIA_REARRANGER_EN = 1 << 30 +}; + +enum RS69_DDIA_PCIE_LINK_CONTROL3_BITS { + RS69_DDIA_PCIE_MIRROR_EN = 1 << 0, + RS69_DDIA_PCIE_CFGDUALLINK = 1 << 4, + RS69_DDIA_PCIE_NCHG3EN = 1 << 8, + RS69_DDIA_PCIE_RX_PDNB_SHIFT = 12 +}; + +enum RS69_MC_INDEX_BITS { + RS69_MC_IND_ADDR = (0x1 << 0), + RS69_C_IND_WR_EN = (0x1 << 9) +}; + +enum _rs690MCRegs { + RS69_MC_SYSTEM_STATUS = 0x90, /* (RW) */ + RS69_MCCFG_FB_LOCATION = 0x100, + RS69MCCFG_AGP_LOCATION = 0x101 +}; + +enum RS69_MC_SYSTEM_STATUS_BITS { + RS69_MC_SYSTEM_IDLE = (0x1 << 0), + RS69_MC_SEQUENCER_IDLE = (0x1 << 1), + RS69_MC_ARBITER_IDLE = (0x1 << 2), + RS69_MC_SELECT_PM = (0x1 << 3), + RS69_RESERVED4 = (0xf << 4), + RS69_RESERVED8 = (0xf << 8), + RS69_RESERVED12_SYSTEM_STATUS = (0xf << 12), + RS69_MCA_INIT_EXECUTED = (0x1 << 16), + RS69_MCA_IDLE = (0x1 << 17), + RS69_MCA_SEQ_IDLE = (0x1 << 18), + RS69_MCA_ARB_IDLE = (0x1 << 19), + RS69_RESERVED20_SYSTEM_STATUS = (0xfff << 20) +}; + +enum R5XX_MC_STATUS_BITS { + R5XX_MEM_PWRUP_COMPL = (0x1 << 0), + R5XX_MC_IDLE = (0x1 << 1) +}; + +enum RV515_MC_STATUS_BITS { + RV515_MC_IDLE = (0x1 << 4) +}; + +enum BUS_CNTL_BITS { + /* BUS_CNTL */ + BUS_DBL_RESYNC = (0x1 << 0), + BIOS_ROM_WRT_EN = (0x1 << 1), + BIOS_ROM_DIS = (0x1 << 2), + PMI_IO_DIS = (0x1 << 3), + PMI_MEM_DIS = (0x1 << 4), + PMI_BM_DIS = (0x1 << 5), + PMI_INT_DIS = (0x1 << 6) +}; + +enum SEPROM_SNTL1_BITS { + /* SEPROM_CNTL1 */ + WRITE_ENABLE = (0x1 << 0), + WRITE_DISABLE = (0x1 << 1), + READ_CONFIG = (0x1 << 2), + WRITE_CONFIG = (0x1 << 3), + READ_STATUS = (0x1 << 4), + SECT_TO_SRAM = (0x1 << 5), + READY_BUSY = (0x1 << 7), + SEPROM_BUSY = (0x1 << 8), + BCNT_OVER_WTE_EN = (0x1 << 9), + RB_MASKB = (0x1 << 10), + SOFT_RESET = (0x1 << 11), + STATE_IDLEb = (0x1 << 12), + SECTOR_ERASE = (0x1 << 13), + BYTE_CNT = (0xff << 16), + SCK_PRESCALE = (0xff << 24) +}; + +enum VIPH_CONTROL_BITS { + /* VIPH_CONTROL */ + VIPH_CLK_SEL = (0xff << 0), + VIPH_REG_RDY = (0x1 << 13), + VIPH_MAX_WAIT = (0xf << 16), + VIPH_DMA_MODE = (0x1 << 20), + VIPH_EN = (0x1 << 21), + VIPH_DV0_WID = (0x1 << 24), + VIPH_DV1_WID = (0x1 << 25), + VIPH_DV2_WID = (0x1 << 26), + VIPH_DV3_WID = (0x1 << 27), + VIPH_PWR_DOWN = (0x1 << 28), + VIPH_PWR_DOWN_AK = (0x1 << 28), + VIPH_VIPCLK_DIS = (0x1 << 29) +}; + +enum VGA_RENDER_CONTROL_BITS { + /* VGA_RENDER_CONTROL */ + VGA_BLINK_RATE = (0x1f << 0), + VGA_BLINK_MODE = (0x3 << 5), + VGA_CURSOR_BLINK_INVERT = (0x1 << 7), + VGA_EXTD_ADDR_COUNT_ENABLE = (0x1 << 8), + VGA_VSTATUS_CNTL = (0x3 << 16), + VGA_LOCK_8DOT = (0x1 << 24), + VGAREG_LINECMP_COMPATIBILITY_SEL = (0x1 << 25) +}; + +enum D1VGA_CONTROL_BITS { + /* D1VGA_CONTROL */ + D1VGA_MODE_ENABLE = (0x1 << 0), + D1VGA_TIMING_SELECT = (0x1 << 8), + D1VGA_SYNC_POLARITY_SELECT = (0x1 << 9), + D1VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10), + D1VGA_OVERSCAN_COLOR_EN = (0x1 << 16), + D1VGA_ROTATE = (0x3 << 24) +}; + +enum D2VGA_CONTROL_BITS { + /* D2VGA_CONTROL */ + D2VGA_MODE_ENABLE = (0x1 << 0), + D2VGA_TIMING_SELECT = (0x1 << 8), + D2VGA_SYNC_POLARITY_SELECT = (0x1 << 9), + D2VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10), + D2VGA_OVERSCAN_COLOR_EN = (0x1 << 16), + D2VGA_ROTATE = (0x3 << 24) +}; + +enum { + /* CLOCK_CNTL_INDEX */ + PLL_ADDR = (0x3f << 0), + PLL_WR_EN = (0x1 << 7), + PPLL_DIV_SEL = (0x3 << 8), + + /* CLOCK_CNTL_DATA */ +#define PLL_DATA 0xffffffff + + /* SPLL_FUNC_CNTL */ + SPLL_CHG_STATUS = (0x1 << 29), + SPLL_BYPASS_EN = (0x1 << 25), + + /* MC_IND_INDEX */ + MC_IND_ADDR = (0xffff << 0), + MC_IND_SEQ_RBS_0 = (0x1 << 16), + MC_IND_SEQ_RBS_1 = (0x1 << 17), + MC_IND_SEQ_RBS_2 = (0x1 << 18), + MC_IND_SEQ_RBS_3 = (0x1 << 19), + MC_IND_AIC_RBS = (0x1 << 20), + MC_IND_CITF_ARB0 = (0x1 << 21), + MC_IND_CITF_ARB1 = (0x1 << 22), + MC_IND_WR_EN = (0x1 << 23), + MC_IND_RD_INV = (0x1 << 24) +#define MC_IND_ALL (MC_IND_SEQ_RBS_0 | MC_IND_SEQ_RBS_1 \ + | MC_IND_SEQ_RBS_2 | MC_IND_SEQ_RBS_3 \ + | MC_IND_AIC_RBS | MC_IND_CITF_ARB0 | MC_IND_CITF_ARB1) + + /* MC_IND_DATA */ +#define MC_IND_DATA_BIT 0xffffffff +}; + + +#endif /* _RHD_REGS_H */ diff --git a/programs/system/drivers/ati2d/xmd.h b/programs/system/drivers/ati2d/xmd.h new file mode 100644 index 0000000000..8c70de94ab --- /dev/null +++ b/programs/system/drivers/ati2d/xmd.h @@ -0,0 +1,203 @@ +/* $XFree86: xc/include/Xmd.h,v 3.18tsi Exp $ */ +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +#ifndef XMD_H +#define XMD_H 1 +/* $Xorg: Xmd.h,v 1.4 2001/02/09 02:03:22 xorgcvs Exp $ */ +/* + * Xmd.h: MACHINE DEPENDENT DECLARATIONS. + */ + +/* + * Special per-machine configuration flags. + */ +#ifdef CRAY +#define WORD64 /* 64-bit architecture */ +#endif +#if defined (_LP64) || \ + defined(__alpha) || defined(__alpha__) || \ + defined(__ia64__) || defined(ia64) || \ + defined(__sparc64__) || \ + defined(__s390x__) || \ + (defined(__hppa__) && defined(__LP64__)) || \ + defined(__amd64__) || defined(amd64) || \ + defined(__powerpc64__) || \ + (defined(sgi) && (_MIPS_SZLONG == 64)) +#define LONG64 /* 32/64-bit architecture */ +#endif + +/* + * Stuff to handle large architecture machines; the constants were generated + * on a 32-bit machine and must coorespond to the protocol. + */ +#ifdef WORD64 +#define MUSTCOPY +#endif /* WORD64 */ + + +/* + * Definition of macro used to set constants for size of network structures; + * machines with preprocessors that can't handle all of the sz_ symbols + * can define this macro to be sizeof(x) if and only if their compiler doesn't + * pad out structures (esp. the xTextElt structure which contains only two + * one-byte fields). Network structures should always define sz_symbols. + * + * The sz_ prefix is used instead of something more descriptive so that the + * symbols are no more than 32 characters long (which causes problems for some + * compilers and preprocessors). + * + * The extra indirection in the __STDC__ case is to get macro arguments to + * expand correctly before the concatenation, rather than afterward. + */ +#if ((defined(__STDC__) || defined(__cplusplus) || defined(c_plusplus)) && !defined(UNIXCPP)) || defined(ANSICPP) +#define _SIZEOF(x) sz_##x +#define SIZEOF(x) _SIZEOF(x) +#else +#define SIZEOF(x) sz_/**/x +#endif /* if ANSI C compiler else not */ + +/* + * Bitfield suffixes for the protocol structure elements, if you + * need them. Note that bitfields are not guarranteed to be signed + * (or even unsigned) according to ANSI C. + */ +#ifdef WORD64 +typedef long INT64; +typedef unsigned long CARD64; +#define B32 :32 +#define B16 :16 +#ifdef UNSIGNEDBITFIELDS +typedef unsigned int INT32; +typedef unsigned int INT16; +#else +#ifdef __STDC__ +typedef signed int INT32; +typedef signed int INT16; +#else +typedef int INT32; +typedef int INT16; +#endif +#endif +#else +#define B32 +#define B16 +#ifdef LONG64 +typedef long INT64; +typedef int INT32; +#else +typedef long INT32; +#endif +typedef short INT16; +#endif + +#if defined(__STDC__) || defined(sgi) || defined(AIXV3) +typedef signed char INT8; +#else +typedef char INT8; +#endif + +#ifdef LONG64 +typedef unsigned long CARD64; +typedef unsigned int CARD32; +#else +typedef unsigned long CARD32; +#endif +typedef unsigned short CARD16; +typedef unsigned char CARD8; + +typedef CARD32 BITS32; +typedef CARD16 BITS16; + +#ifndef I_NEED_OS2_H +typedef CARD8 BYTE; +typedef CARD8 BOOL; +#else +#define BYTE CARD8 +#define BOOL CARD8 +#endif + +/* + * definitions for sign-extending bitfields on 64-bit architectures + */ +#if defined(WORD64) && defined(UNSIGNEDBITFIELDS) +#define cvtINT8toInt(val) (((val) & 0x00000080) ? ((val) | 0xffffffffffffff00) : (val)) +#define cvtINT16toInt(val) (((val) & 0x00008000) ? ((val) | 0xffffffffffff0000) : (val)) +#define cvtINT32toInt(val) (((val) & 0x80000000) ? ((val) | 0xffffffff00000000) : (val)) +#define cvtINT8toShort(val) cvtINT8toInt(val) +#define cvtINT16toShort(val) cvtINT16toInt(val) +#define cvtINT32toShort(val) cvtINT32toInt(val) +#define cvtINT8toLong(val) cvtINT8toInt(val) +#define cvtINT16toLong(val) cvtINT16toInt(val) +#define cvtINT32toLong(val) cvtINT32toInt(val) +#else +#define cvtINT8toInt(val) (val) +#define cvtINT16toInt(val) (val) +#define cvtINT32toInt(val) (val) +#define cvtINT8toShort(val) (val) +#define cvtINT16toShort(val) (val) +#define cvtINT32toShort(val) (val) +#define cvtINT8toLong(val) (val) +#define cvtINT16toLong(val) (val) +#define cvtINT32toLong(val) (val) +#endif /* WORD64 and UNSIGNEDBITFIELDS */ + + + +#ifdef MUSTCOPY +/* + * This macro must not cast or else pointers will get aligned and be wrong + */ +#define NEXTPTR(p,t) (((char *) p) + SIZEOF(t)) +#else /* else not MUSTCOPY, this is used for 32-bit machines */ +/* + * this version should leave result of type (t *), but that should only be + * used when not in MUSTCOPY + */ +#define NEXTPTR(p,t) (((t *)(p)) + 1) +#endif /* MUSTCOPY - used machines whose C structs don't line up with proto */ + +#endif /* XMD_H */