ati-4.6.7

git-svn-id: svn://kolibrios.org@7146 a494cfbc-eb01-0410-851d-a64ba20cac60

drivers/video/drm/radeon/Makefile

@@ -33,17 +33,6 @@ LDFLAGS = -nostdlib -shared -s $(PE_FLAGS) --image-base 0\
 
 NAME:=	  atikms
 
-HFILES:=     		$(DDK_INCLUDES)/linux/types.h		\
-			$(DDK_INCLUDES)/linux/list.h		\
-			$(DDK_INCLUDES)/linux/pci.h		\
-			$(DDK_INCLUDES)/drm/drmP.h		\
-			$(DDK_INCLUDES)/drm/drm_edid.h		\
-			$(DDK_INCLUDES)/drm/drm_crtc.h		\
-			$(DDK_INCLUDES)/drm/drm_mm.h		\
-			atom.h					\
-			radeon.h				\
-			radeon_asic.h
-
 NAME_SRC=							\
 			main.c					\
 			pci.c					\
@@ -231,7 +220,7 @@ NAME_OBJS =  $(patsubst %.S, %.o, $(patsubst %.asm, %.o,\
 
 all: $(NAME).dll
 
-$(NAME).dll: $(NAME_OBJS) $(FW_BINS) $(SRC_DEP) $(HFILES) $(LIBPATH)/libcore.a $(LIBPATH)/libddk.a atikms.lds Makefile
+$(NAME).dll: $(NAME_OBJS) $(FW_BINS) $(SRC_DEP) $(LIBPATH)/libcore.a $(LIBPATH)/libddk.a atikms.lds Makefile
 	$(LD) -L$(LIBPATH) $(LDFLAGS) -T atikms.lds -o $@ $(NAME_OBJS) $(LIBS)  
 
 

drivers/video/drm/radeon/atom.c

@@ -66,9 +66,10 @@ int atom_debug = 0;
 static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
 int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
 
-static uint32_t atom_arg_mask[8] =
+static uint32_t atom_arg_mask[8] = {
-    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
+	0xFFFFFFFF, 0x0000FFFF, 0x00FFFF00, 0xFFFF0000,
-0xFF000000 };
+	0x000000FF, 0x0000FF00, 0x00FF0000, 0xFF000000
+};
 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
 
 static int atom_dst_to_src[8][4] = {

drivers/video/drm/radeon/atombios_crtc.c

@@ -275,13 +275,15 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 			atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 		atombios_blank_crtc(crtc, ATOM_DISABLE);
-		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
+		if (dev->num_crtcs > radeon_crtc->crtc_id)
+			drm_vblank_on(dev, radeon_crtc->crtc_id);
 		radeon_crtc_load_lut(crtc);
 		break;
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 	case DRM_MODE_DPMS_OFF:
-		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
+		if (dev->num_crtcs > radeon_crtc->crtc_id)
+			drm_vblank_off(dev, radeon_crtc->crtc_id);
 		if (radeon_crtc->enabled)
 			atombios_blank_crtc(crtc, ATOM_ENABLE);
 		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))

drivers/video/drm/radeon/atombios_encoders.c

@@ -2629,16 +2629,8 @@ radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
 
 }
 
-static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
-				       const struct drm_display_mode *mode,
-				       struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
 	.dpms = radeon_atom_ext_dpms,
-	.mode_fixup = radeon_atom_ext_mode_fixup,
 	.prepare = radeon_atom_ext_prepare,
 	.mode_set = radeon_atom_ext_mode_set,
 	.commit = radeon_atom_ext_commit,

drivers/video/drm/radeon/btc_dpm.c

@@ -1163,8 +1163,7 @@ u32 btc_valid_sclk[40] =
 	155000, 160000, 165000, 170000, 175000, 180000, 185000, 190000, 195000, 200000
 };
 
-static const struct radeon_blacklist_clocks btc_blacklist_clocks[] =
+static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = {
-{
 	{ 10000, 30000, RADEON_SCLK_UP },
 	{ 15000, 30000, RADEON_SCLK_UP },
 	{ 20000, 30000, RADEON_SCLK_UP },

drivers/video/drm/radeon/cik_sdma.c

@@ -737,11 +737,16 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 		DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
 		return r;
 	}
-	r = radeon_fence_wait(ib.fence, false);
+	r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
-	if (r) {
+		RADEON_USEC_IB_TEST_TIMEOUT));
+	if (r < 0) {
 		DRM_ERROR("radeon: fence wait failed (%d).\n", r);
 		return r;
+	} else if (r == 0) {
+		DRM_ERROR("radeon: fence wait timed out.\n");
+		return -ETIMEDOUT;
 	}
+	r = 0;
 	for (i = 0; i < rdev->usec_timeout; i++) {
 		tmp = le32_to_cpu(rdev->wb.wb[index/4]);
 		if (tmp == 0xDEADBEEF)

drivers/video/drm/radeon/main.c

@@ -5,7 +5,7 @@
 #include "radeon.h"
 #include "bitmap.h"
 
-#define DRV_NAME "atikms v4.5.7"
+#define DRV_NAME "atikms v4.6.7"
 
 void __init dmi_scan_machine(void);
 int printf ( const char * format, ... );

drivers/video/drm/radeon/ni_dpm.c

@@ -1621,9 +1621,7 @@ static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
 		(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
 
 
-	radeon_atom_set_engine_dram_timings(rdev,
+	radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk);
-                                            pl->sclk,
-                                            pl->mclk);
 
 	dram_timing = RREG32(MC_ARB_DRAM_TIMING);
 	dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);

drivers/video/drm/radeon/ni_reg.h

@@ -109,6 +109,8 @@
 #define NI_DP_MSE_SAT2                                 0x7398
 
 #define NI_DP_MSE_SAT_UPDATE                           0x739c
+#       define NI_DP_MSE_SAT_UPDATE_MASK               0x3
+#       define NI_DP_MSE_16_MTP_KEEPOUT                0x100
 
 #define NI_DIG_BE_CNTL                                 0x7140
 #       define NI_DIG_FE_SOURCE_SELECT(x)              (((x) & 0x7f) << 8)

drivers/video/drm/radeon/pci.c

@@ -17,6 +17,9 @@ static LIST_HEAD(devices);
 
 #define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
 
+#define IORESOURCE_ROM_COPY             (1<<2)  /* ROM is alloc'd copy, resource field overlaid */
+#define IORESOURCE_ROM_BIOS_COPY        (1<<3)  /* ROM is BIOS copy, resource field overlaid */
+
 /*
  * Translate the low bits of the PCI base
  * to the resource type

drivers/video/drm/radeon/r300.c

@@ -1547,6 +1547,7 @@ int r300_init(struct radeon_device *rdev)
 			rv370_pcie_gart_fini(rdev);
 		if (rdev->flags & RADEON_IS_PCI)
 			r100_pci_gart_fini(rdev);
+		radeon_agp_fini(rdev);
 		rdev->accel_working = false;
 	}
 	return 0;

drivers/video/drm/radeon/r420.c

@@ -416,6 +416,7 @@ int r420_init(struct radeon_device *rdev)
 			rv370_pcie_gart_fini(rdev);
 		if (rdev->flags & RADEON_IS_PCI)
 			r100_pci_gart_fini(rdev);
+		radeon_agp_fini(rdev);
 		rdev->accel_working = false;
 	}
 	return 0;

drivers/video/drm/radeon/r520.c

@@ -297,6 +297,7 @@ int r520_init(struct radeon_device *rdev)
 		radeon_ib_pool_fini(rdev);
 		radeon_irq_kms_fini(rdev);
 		rv370_pcie_gart_fini(rdev);
+		radeon_agp_fini(rdev);
 		rdev->accel_working = false;
 	}
 	return 0;

drivers/video/drm/radeon/radeon.h

@@ -126,6 +126,7 @@ extern int radeon_mst;
  */
 #define RADEON_MAX_USEC_TIMEOUT			100000	/* 100 ms */
 #define RADEON_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
+#define RADEON_USEC_IB_TEST_TIMEOUT		1000000 /* 1s */
 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 #define RADEON_IB_POOL_SIZE			16
 #define RADEON_DEBUGFS_MAX_COMPONENTS		32
@@ -388,6 +389,7 @@ void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
 void radeon_fence_process(struct radeon_device *rdev, int ring);
 bool radeon_fence_signaled(struct radeon_fence *fence);
+long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
@@ -474,7 +476,6 @@ struct radeon_bo_va {
 	/* protected by bo being reserved */
 	struct list_head		bo_list;
 	uint32_t			flags;
-	uint64_t			addr;
 	struct radeon_fence		*last_pt_update;
 	unsigned			ref_count;
 

drivers/video/drm/radeon/radeon_bios.c

@@ -31,6 +31,7 @@
 #include "atom.h"
 
 #include <linux/slab.h>
+#include <linux/acpi.h>
 /*
  * BIOS.
  */

drivers/video/drm/radeon/radeon_combios.c

@@ -34,7 +34,6 @@
 #include <asm/machdep.h>
 #include <asm/pmac_feature.h>
 #include <asm/prom.h>
-#include <asm/pci-bridge.h>
 #endif /* CONFIG_PPC_PMAC */
 
 /* from radeon_legacy_encoder.c */

drivers/video/drm/radeon/radeon_connectors.c

@@ -34,6 +34,7 @@
 #include "atom.h"
 
 #include <linux/pm_runtime.h>
+#include <linux/vga_switcheroo.h>
 
 static int radeon_dp_handle_hpd(struct drm_connector *connector)
 {
@@ -344,6 +345,11 @@ static void radeon_connector_get_edid(struct drm_connector *connector)
 		else if (radeon_connector->ddc_bus)
 			radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 							      &radeon_connector->ddc_bus->adapter);
+	} else if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC &&
+		   connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
+		   radeon_connector->ddc_bus) {
+		radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base,
+								 &radeon_connector->ddc_bus->adapter);
 	} else if (radeon_connector->ddc_bus) {
 		radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 						      &radeon_connector->ddc_bus->adapter);

drivers/video/drm/radeon/radeon_device.c

@@ -31,6 +31,7 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/radeon_drm.h>
 #include <linux/vgaarb.h>
+#include <linux/vga_switcheroo.h>
 #include "radeon_reg.h"
 #include "radeon.h"
 #include "atom.h"
@@ -1278,9 +1279,9 @@ int radeon_device_init(struct radeon_device *rdev,
 	}
 	rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
 
-	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
+	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
 		 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
-		pdev->subsystem_vendor, pdev->subsystem_device);
+		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
 
 	/* mutex initialization are all done here so we
 	 * can recall function without having locking issues */
@@ -1348,13 +1349,6 @@ int radeon_device_init(struct radeon_device *rdev,
 	    (rdev->family <= CHIP_RS740))
 		rdev->need_dma32 = true;
 
-	dma_bits = rdev->need_dma32 ? 32 : 40;
-	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
-	if (r) {
-		rdev->need_dma32 = true;
-		dma_bits = 32;
-		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
-	}
 
 	/* Registers mapping */
 	/* TODO: block userspace mapping of io register */

drivers/video/drm/radeon/radeon_display.c

@@ -351,6 +351,7 @@ radeon_crtc_set_config(struct drm_mode_set *set)
 
 	/* drop the power reference we got coming in here */
 //   pm_runtime_put_autosuspend(dev->dev);
+
 	return ret;
 }
 static const struct drm_crtc_funcs radeon_crtc_funcs = {
@@ -1326,6 +1327,9 @@ void radeon_modeset_fini(struct radeon_device *rdev)
 {
 	kfree(rdev->mode_info.bios_hardcoded_edid);
 
+	/* free i2c buses */
+	radeon_i2c_fini(rdev);
+
 	if (rdev->mode_info.mode_config_initialized) {
 //		radeon_afmt_fini(rdev);
 //       drm_kms_helper_poll_fini(rdev->ddev);
@@ -1333,8 +1337,6 @@ void radeon_modeset_fini(struct radeon_device *rdev)
 //       drm_mode_config_cleanup(rdev->ddev);
 		rdev->mode_info.mode_config_initialized = false;
 	}
-	/* free i2c buses */
-	radeon_i2c_fini(rdev);
 }
 
 static bool is_hdtv_mode(const struct drm_display_mode *mode)

drivers/video/drm/radeon/radeon_dp_mst.c

@@ -89,8 +89,16 @@ static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
 	WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
 
 	do {
+		unsigned value1, value2;
+		udelay(10);
 		temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
-	} while ((temp & 0x1) && retries++ < 10000);
+
+		value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
+		value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
+
+		if (!value1 && !value2)
+			break;
+	} while (retries++ < 50);
 
 	if (retries == 10000)
 		DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
@@ -150,7 +158,7 @@ static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn
 	return 0;
 }
 
-static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
+static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 {
 	struct drm_device *dev = mst->base.dev;
 	struct radeon_device *rdev = dev->dev_private;
@@ -158,6 +166,8 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
 	uint32_t val, temp;
 	uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 	int retries = 0;
+	uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
+	uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 
 	val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 
@@ -165,6 +175,7 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
 
 	do {
 		temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
+		udelay(10);
 	} while ((temp & 0x1) && (retries++ < 10000));
 
 	if (retries >= 10000)
@@ -246,14 +257,8 @@ radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 	kfree(radeon_connector);
 }
 
-static int radeon_connector_dpms(struct drm_connector *connector, int mode)
-{
-	DRM_DEBUG_KMS("\n");
-	return 0;
-}
-
 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
-	.dpms = radeon_connector_dpms,
+	.dpms = drm_helper_connector_dpms,
 	.detect = radeon_dp_mst_detect,
 	.fill_modes = drm_helper_probe_single_connector_modes,
 	.destroy = radeon_dp_mst_connector_destroy,
@@ -394,7 +399,7 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 	struct drm_crtc *crtc;
 	struct radeon_crtc *radeon_crtc;
 	int ret, slots;
-
+	s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 	if (!ASIC_IS_DCE5(rdev)) {
 		DRM_ERROR("got mst dpms on non-DCE5\n");
 		return;
@@ -456,7 +461,11 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 
 		mst_enc->enc_active = true;
 		radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
-		radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
+
+		fixed_pbn = drm_int2fixp(mst_enc->pbn);
+		fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
+		avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
+		radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 
 		atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 					    mst_enc->fe);
@@ -510,6 +519,7 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 {
 	struct radeon_encoder_mst *mst_enc;
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+	struct radeon_connector_atom_dig *dig_connector;
 	int bpp = 24;
 
 	mst_enc = radeon_encoder->enc_priv;
@@ -523,14 +533,11 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 
 
 	drm_mode_set_crtcinfo(adjusted_mode, 0);
-	{
-	  struct radeon_connector_atom_dig *dig_connector;
 	dig_connector = mst_enc->connector->con_priv;
 	dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 	dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 	DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 		      dig_connector->dp_lane_count, dig_connector->dp_clock);
-	}
 	return true;
 }
 

drivers/video/drm/radeon/radeon_fb.c

@@ -39,8 +39,8 @@ struct drm_framebuffer *main_fb;
 struct drm_gem_object  *main_fb_obj;
 
 /* object hierarchy -
-   this contains a helper + a radeon fb
+ * this contains a helper + a radeon fb
-   the helper contains a pointer to radeon framebuffer baseclass.
+ * the helper contains a pointer to radeon framebuffer baseclass.
  */
 struct radeon_fbdev {
 	struct drm_fb_helper helper;
@@ -309,6 +309,10 @@ int radeon_fbdev_init(struct radeon_device *rdev)
 	int bpp_sel = 32;
 	int ret;
 
+	/* don't enable fbdev if no connectors */
+	if (list_empty(&rdev->ddev->mode_config.connector_list))
+		return 0;
+
 	/* select 8 bpp console on RN50 or 16MB cards */
 	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
 		bpp_sel = 8;

drivers/video/drm/radeon/radeon_fence.c

@@ -507,6 +507,46 @@ static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
 	return r;
 }
 
+/**
+ * radeon_fence_wait_timeout - wait for a fence to signal with timeout
+ *
+ * @fence: radeon fence object
+ * @intr: use interruptible sleep
+ *
+ * Wait for the requested fence to signal (all asics).
+ * @intr selects whether to use interruptable (true) or non-interruptable
+ * (false) sleep when waiting for the fence.
+ * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
+ * Returns remaining time if the sequence number has passed, 0 when
+ * the wait timeout, or an error for all other cases.
+ */
+long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
+{
+	uint64_t seq[RADEON_NUM_RINGS] = {};
+	long r;
+	int r_sig;
+
+	/*
+	 * This function should not be called on !radeon fences.
+	 * If this is the case, it would mean this function can
+	 * also be called on radeon fences belonging to another card.
+	 * exclusive_lock is not held in that case.
+	 */
+	if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
+		return fence_wait(&fence->base, intr);
+
+	seq[fence->ring] = fence->seq;
+	r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
+	if (r <= 0) {
+		return r;
+	}
+
+	r_sig = fence_signal(&fence->base);
+	if (!r_sig)
+		FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
+	return r;
+}
+
 /**
  * radeon_fence_wait - wait for a fence to signal
  *
@@ -520,28 +560,12 @@ static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
  */
 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 {
-	uint64_t seq[RADEON_NUM_RINGS] = {};
+	long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
-	long r;
+	if (r > 0) {
-
+		return 0;
-	/*
+	} else {
-	 * This function should not be called on !radeon fences.
-	 * If this is the case, it would mean this function can
-	 * also be called on radeon fences belonging to another card.
-	 * exclusive_lock is not held in that case.
-	 */
-	if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
-		return fence_wait(&fence->base, intr);
-
-	seq[fence->ring] = fence->seq;
-	r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
-	if (r < 0) {
 		return r;
 	}
-
-	r = fence_signal(&fence->base);
-	if (!r)
-		FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
-    return 0;
 }
 
 /**

drivers/video/drm/radeon/radeon_gem.c

@@ -257,7 +257,6 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 			  struct drm_file *filp)
 {
-	struct radeon_device *rdev = dev->dev_private;
 	struct drm_radeon_gem_busy *args = data;
 	struct drm_gem_object *gobj;
 	struct radeon_bo *robj;
@@ -272,7 +271,6 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 	r = radeon_bo_wait(robj, &cur_placement, true);
 	args->domain = radeon_mem_type_to_domain(cur_placement);
 	drm_gem_object_unreference_unlocked(gobj);
-	r = radeon_gem_handle_lockup(rdev, r);
 	return r;
 }
 

drivers/video/drm/radeon/radeon_irq_kms.c

@@ -156,6 +156,8 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
 	if (r) {
 		return r;
 	}
+	rdev->ddev->vblank_disable_allowed = true;
+
 	/* enable msi */
 	rdev->msi_enabled = 0;
 

drivers/video/drm/radeon/radeon_kfd.h

@@ -33,7 +33,7 @@
 
 struct radeon_device;
 
-bool radeon_kfd_init(void);
+int radeon_kfd_init(void);
 void radeon_kfd_fini(void);
 
 void radeon_kfd_suspend(struct radeon_device *rdev);

drivers/video/drm/radeon/radeon_kms.c

@@ -30,6 +30,7 @@
 #include <drm/radeon_drm.h>
 #include "radeon_asic.h"
 
+#include <linux/vga_switcheroo.h>
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
 

drivers/video/drm/radeon/radeon_legacy_crtc.c

@@ -331,13 +331,15 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 									 RADEON_CRTC_DISP_REQ_EN_B));
 			WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
 		}
-		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
+		if (dev->num_crtcs > radeon_crtc->crtc_id)
+			drm_vblank_on(dev, radeon_crtc->crtc_id);
 		radeon_crtc_load_lut(crtc);
 		break;
 	case DRM_MODE_DPMS_STANDBY:
 	case DRM_MODE_DPMS_SUSPEND:
 	case DRM_MODE_DPMS_OFF:
-		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
+		if (dev->num_crtcs > radeon_crtc->crtc_id)
+			drm_vblank_off(dev, radeon_crtc->crtc_id);
 		if (radeon_crtc->crtc_id)
 			WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 		else {

drivers/video/drm/radeon/radeon_uvd.c

@@ -722,9 +722,11 @@ static int radeon_uvd_send_msg(struct radeon_device *rdev,
 	return r;
 }
 
-/* multiple fence commands without any stream commands in between can
+/*
-   crash the vcpu so just try to emmit a dummy create/destroy msg to
+ * multiple fence commands without any stream commands in between can
-   avoid this */
+ * crash the vcpu so just try to emmit a dummy create/destroy msg to
+ * avoid this
+ */
 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 			      uint32_t handle, struct radeon_fence **fence)
 {

drivers/video/drm/radeon/radeon_vm.c

@@ -612,6 +612,7 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
 static uint32_t radeon_vm_page_flags(uint32_t flags)
 {
 	uint32_t hw_flags = 0;
+
 	hw_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
 	hw_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
 	hw_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;

drivers/video/drm/radeon/si.c

@@ -2442,8 +2442,10 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
  */
 static void si_tiling_mode_table_init(struct radeon_device *rdev)
 {
-	const u32 num_tile_mode_states = 32;
+	u32 *tile = rdev->config.si.tile_mode_array;
-	u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
+	const u32 num_tile_mode_states =
+			ARRAY_SIZE(rdev->config.si.tile_mode_array);
+	u32 reg_offset, split_equal_to_row_size;
 
 	switch (rdev->config.si.mem_row_size_in_kb) {
 	case 1:
@@ -2458,12 +2460,14 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 		break;
 	}
 
-	if ((rdev->family == CHIP_TAHITI) ||
+	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
-	    (rdev->family == CHIP_PITCAIRN)) {
+		tile[reg_offset] = 0;
-		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+
-			switch (reg_offset) {
+	switch(rdev->family) {
-			case 0:  /* non-AA compressed depth or any compressed stencil */
+	case CHIP_TAHITI:
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+	case CHIP_PITCAIRN:
+		/* non-AA compressed depth or any compressed stencil */
+		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2471,9 +2475,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 2xAA/4xAA compressed depth only */
-			case 1:  /* 2xAA/4xAA compressed depth only */
+		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2481,9 +2484,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 8xAA compressed depth only */
-			case 2:  /* 8xAA compressed depth only */
+		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2491,9 +2493,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
-			case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
+		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2501,9 +2502,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
-			case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
+		tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2511,9 +2511,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Uncompressed 16bpp depth - and stencil buffer allocated with it */
-			case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
+		tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2521,9 +2520,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Uncompressed 32bpp depth - and stencil buffer allocated with it */
-			case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
+		tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2531,9 +2529,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-				break;
+		/* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
-			case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
+		tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2541,9 +2538,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 1D and 1D Array Surfaces */
-			case 8:  /* 1D and 1D Array Surfaces */
+		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2551,9 +2547,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Displayable maps. */
-			case 9:  /* Displayable maps. */
+		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2561,9 +2556,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Display 8bpp. */
-			case 10:  /* Display 8bpp. */
+		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2571,9 +2565,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Display 16bpp. */
-			case 11:  /* Display 16bpp. */
+		tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2581,9 +2574,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Display 32bpp. */
-			case 12:  /* Display 32bpp. */
+		tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2591,9 +2583,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-				break;
+		/* Thin. */
-			case 13:  /* Thin. */
+		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2601,9 +2592,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Thin 8 bpp. */
-			case 14:  /* Thin 8 bpp. */
+		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2611,9 +2601,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-				break;
+		/* Thin 16 bpp. */
-			case 15:  /* Thin 16 bpp. */
+		tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2621,9 +2610,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-				break;
+		/* Thin 32 bpp. */
-			case 16:  /* Thin 32 bpp. */
+		tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2631,9 +2619,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-				break;
+		/* Thin 64 bpp. */
-			case 17:  /* Thin 64 bpp. */
+		tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2641,9 +2628,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-				break;
+		/* 8 bpp PRT. */
-			case 21:  /* 8 bpp PRT. */
+		tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2651,9 +2637,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 16 bpp PRT */
-			case 22:  /* 16 bpp PRT */
+		tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2661,9 +2646,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* 32 bpp PRT */
-			case 23:  /* 32 bpp PRT */
+		tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2671,9 +2655,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 64 bpp PRT */
-			case 24:  /* 64 bpp PRT */
+		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2681,9 +2664,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 128 bpp PRT */
-			case 25:  /* 128 bpp PRT */
+		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
@@ -2691,21 +2673,16 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+
+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
 		break;
-			default:
+
-				gb_tile_moden = 0;
+	case CHIP_VERDE:
-				break;
+	case CHIP_OLAND:
-			}
+	case CHIP_HAINAN:
-			rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
+		/* non-AA compressed depth or any compressed stencil */
-			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
+		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-		}
-	} else if ((rdev->family == CHIP_VERDE) ||
-		   (rdev->family == CHIP_OLAND) ||
-		   (rdev->family == CHIP_HAINAN)) {
-		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-			switch (reg_offset) {
-			case 0:  /* non-AA compressed depth or any compressed stencil */
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2713,9 +2690,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* 2xAA/4xAA compressed depth only */
-			case 1:  /* 2xAA/4xAA compressed depth only */
+		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2723,9 +2699,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* 8xAA compressed depth only */
-			case 2:  /* 8xAA compressed depth only */
+		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2733,9 +2708,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
-			case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
+		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
@@ -2743,9 +2717,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
-			case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
+		tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2753,9 +2726,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Uncompressed 16bpp depth - and stencil buffer allocated with it */
-			case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
+		tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2763,9 +2735,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Uncompressed 32bpp depth - and stencil buffer allocated with it */
-			case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
+		tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2773,9 +2744,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
-			case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
+		tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2783,9 +2753,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* 1D and 1D Array Surfaces */
-			case 8:  /* 1D and 1D Array Surfaces */
+		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2793,9 +2762,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Displayable maps. */
-			case 9:  /* Displayable maps. */
+		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2803,9 +2771,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Display 8bpp. */
-			case 10:  /* Display 8bpp. */
+		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2813,9 +2780,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* Display 16bpp. */
-			case 11:  /* Display 16bpp. */
+		tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2823,9 +2789,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Display 32bpp. */
-			case 12:  /* Display 32bpp. */
+		tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2833,9 +2798,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Thin. */
-			case 13:  /* Thin. */
+		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2843,9 +2807,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Thin 8 bpp. */
-			case 14:  /* Thin 8 bpp. */
+		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2853,9 +2816,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Thin 16 bpp. */
-			case 15:  /* Thin 16 bpp. */
+		tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2863,9 +2825,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Thin 32 bpp. */
-			case 16:  /* Thin 32 bpp. */
+		tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2873,9 +2834,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* Thin 64 bpp. */
-			case 17:  /* Thin 64 bpp. */
+		tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 			   TILE_SPLIT(split_equal_to_row_size) |
@@ -2883,9 +2843,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 8 bpp PRT. */
-			case 21:  /* 8 bpp PRT. */
+		tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2893,9 +2852,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 16 bpp PRT */
-			case 22:  /* 16 bpp PRT */
+		tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2903,9 +2861,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-				break;
+		/* 32 bpp PRT */
-			case 23:  /* 32 bpp PRT */
+		tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
@@ -2913,9 +2870,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 64 bpp PRT */
-			case 24:  /* 64 bpp PRT */
+		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
@@ -2923,9 +2879,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-				break;
+		/* 128 bpp PRT */
-			case 25:  /* 128 bpp PRT */
+		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 			   MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
 			   PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
@@ -2933,17 +2888,15 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
 			   BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 			   BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 			   MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+
+		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+			WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
 		break;
+
 	default:
-				gb_tile_moden = 0;
-				break;
-			}
-			rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
-			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
-		}
-	} else
 		DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
 	}
+}
 
 static void si_select_se_sh(struct radeon_device *rdev,
 			    u32 se_num, u32 sh_num)

drivers/video/drm/ttm/ttm_bo.c

@@ -854,6 +854,7 @@ bool ttm_bo_mem_compat(struct ttm_placement *placement,
 
 	return false;
 }
+EXPORT_SYMBOL(ttm_bo_mem_compat);
 
 int ttm_bo_validate(struct ttm_buffer_object *bo,
 			struct ttm_placement *placement,
@@ -974,9 +975,15 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
 	if (likely(!ret))
 		ret = ttm_bo_validate(bo, placement, interruptible, false);
 
-	if (!resv)
+	if (!resv) {
 		ttm_bo_unreserve(bo);
 
+	} else if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
+		spin_lock(&bo->glob->lru_lock);
+		ttm_bo_add_to_lru(bo);
+		spin_unlock(&bo->glob->lru_lock);
+	}
+
 	if (unlikely(ret))
 		ttm_bo_unref(&bo);
 

drivers/video/drm/ttm/ttm_bo_util.c

@@ -40,8 +40,6 @@
 
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-void *vmap(struct page **pages, unsigned int count,
-           unsigned long flags, pgprot_t prot);
 
 void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
 {
@@ -575,6 +573,7 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map)
 		iounmap(map->virtual);
 		break;
 	case ttm_bo_map_vmap:
+		vunmap(map->virtual);
 		break;
 	case ttm_bo_map_kmap:
 		kunmap(map->page);
@@ -677,3 +676,8 @@ void *vmap(struct page **pages, unsigned int count,
     return vaddr;
 };
 
+void vunmap(const void *addr)
+{
+    FreeKernelSpace((void*)addr);
+}
+