forked from KolibriOS/kolibrios
385 lines
13 KiB
C
385 lines
13 KiB
C
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/*
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* Copyright <EFBFBD> 2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Xiang Haihao <haihao.xiang@intel.com>
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* Zou Nan hai <nanhai.zou@intel.com>
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*
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "intel_batchbuffer.h"
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#include "intel_driver.h"
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#include "i965_defines.h"
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#include "i965_drv_video.h"
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#include "i965_media.h"
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#include "i965_media_mpeg2.h"
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#include "i965_media_h264.h"
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static void
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i965_media_pipeline_select(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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struct intel_batchbuffer *batch = media_context->base.batch;
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BEGIN_BATCH(batch, 1);
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OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
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ADVANCE_BATCH(batch);
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}
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static void
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i965_media_urb_layout(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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struct i965_driver_data *i965 = i965_driver_data(ctx);
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struct intel_batchbuffer *batch = media_context->base.batch;
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unsigned int vfe_fence, cs_fence;
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vfe_fence = media_context->urb.cs_start;
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cs_fence = URB_SIZE((&i965->intel));
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BEGIN_BATCH(batch, 3);
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OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
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OUT_BATCH(batch, 0);
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OUT_BATCH(batch,
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(vfe_fence << UF2_VFE_FENCE_SHIFT) | /* VFE_SIZE */
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(cs_fence << UF2_CS_FENCE_SHIFT)); /* CS_SIZE */
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ADVANCE_BATCH(batch);
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}
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static void
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i965_media_state_base_address(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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struct i965_driver_data *i965 = i965_driver_data(ctx);
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struct intel_batchbuffer *batch = media_context->base.batch;
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if (IS_IRONLAKE(i965->intel.device_id)) {
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BEGIN_BATCH(batch, 8);
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OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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if (media_context->indirect_object.bo) {
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OUT_RELOC(batch, media_context->indirect_object.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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media_context->indirect_object.offset | BASE_ADDRESS_MODIFY);
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} else {
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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}
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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ADVANCE_BATCH(batch);
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} else {
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BEGIN_BATCH(batch, 6);
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OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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if (media_context->indirect_object.bo) {
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OUT_RELOC(batch, media_context->indirect_object.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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media_context->indirect_object.offset | BASE_ADDRESS_MODIFY);
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} else {
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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}
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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ADVANCE_BATCH(batch);
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}
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}
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static void
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i965_media_state_pointers(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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struct intel_batchbuffer *batch = media_context->base.batch;
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BEGIN_BATCH(batch, 3);
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OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
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if (media_context->extended_state.enabled)
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OUT_RELOC(batch, media_context->extended_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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else
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OUT_BATCH(batch, 0);
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OUT_RELOC(batch, media_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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ADVANCE_BATCH(batch);
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}
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static void
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i965_media_cs_urb_layout(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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struct intel_batchbuffer *batch = media_context->base.batch;
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BEGIN_BATCH(batch, 2);
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OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
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OUT_BATCH(batch,
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((media_context->urb.size_cs_entry - 1) << 4) | /* URB Entry Allocation Size */
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(media_context->urb.num_cs_entries << 0)); /* Number of URB Entries */
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ADVANCE_BATCH(batch);
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}
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static void
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i965_media_pipeline_state(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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i965_media_state_base_address(ctx, media_context);
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i965_media_state_pointers(ctx, media_context);
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i965_media_cs_urb_layout(ctx, media_context);
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}
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static void
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i965_media_constant_buffer(VADriverContextP ctx, struct decode_state *decode_state, struct i965_media_context *media_context)
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{
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struct intel_batchbuffer *batch = media_context->base.batch;
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BEGIN_BATCH(batch, 2);
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OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
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OUT_RELOC(batch, media_context->curbe.bo,
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I915_GEM_DOMAIN_INSTRUCTION, 0,
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media_context->urb.size_cs_entry - 1);
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ADVANCE_BATCH(batch);
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}
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static void
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i965_media_depth_buffer(VADriverContextP ctx, struct i965_media_context *media_context)
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{
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struct intel_batchbuffer *batch = media_context->base.batch;
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BEGIN_BATCH(batch, 6);
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OUT_BATCH(batch, CMD_DEPTH_BUFFER | 4);
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OUT_BATCH(batch, (I965_DEPTHFORMAT_D32_FLOAT << 18) |
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(I965_SURFACE_NULL << 29));
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OUT_BATCH(batch, 0);
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OUT_BATCH(batch, 0);
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OUT_BATCH(batch, 0);
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OUT_BATCH(batch, 0);
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ADVANCE_BATCH(batch);
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}
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static void
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i965_media_pipeline_setup(VADriverContextP ctx,
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struct decode_state *decode_state,
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struct i965_media_context *media_context)
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{
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struct intel_batchbuffer *batch = media_context->base.batch;
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intel_batchbuffer_start_atomic(batch, 0x1000);
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intel_batchbuffer_emit_mi_flush(batch); /* step 1 */
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i965_media_depth_buffer(ctx, media_context);
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i965_media_pipeline_select(ctx, media_context); /* step 2 */
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i965_media_urb_layout(ctx, media_context); /* step 3 */
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i965_media_pipeline_state(ctx, media_context); /* step 4 */
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i965_media_constant_buffer(ctx, decode_state, media_context); /* step 5 */
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assert(media_context->media_objects);
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media_context->media_objects(ctx, decode_state, media_context); /* step 6 */
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intel_batchbuffer_end_atomic(batch);
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}
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static void
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i965_media_decode_init(VADriverContextP ctx,
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VAProfile profile,
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struct decode_state *decode_state,
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struct i965_media_context *media_context)
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{
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int i;
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struct i965_driver_data *i965 = i965_driver_data(ctx);
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dri_bo *bo;
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/* constant buffer */
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dri_bo_unreference(media_context->curbe.bo);
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bo = dri_bo_alloc(i965->intel.bufmgr,
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"constant buffer",
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4096, 64);
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assert(bo);
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media_context->curbe.bo = bo;
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/* surface state */
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for (i = 0; i < MAX_MEDIA_SURFACES; i++) {
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dri_bo_unreference(media_context->surface_state[i].bo);
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media_context->surface_state[i].bo = NULL;
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}
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/* binding table */
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dri_bo_unreference(media_context->binding_table.bo);
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bo = dri_bo_alloc(i965->intel.bufmgr,
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"binding table",
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MAX_MEDIA_SURFACES * sizeof(unsigned int), 32);
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assert(bo);
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media_context->binding_table.bo = bo;
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/* interface descriptor remapping table */
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dri_bo_unreference(media_context->idrt.bo);
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bo = dri_bo_alloc(i965->intel.bufmgr,
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"interface discriptor",
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MAX_INTERFACE_DESC * sizeof(struct i965_interface_descriptor), 16);
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assert(bo);
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media_context->idrt.bo = bo;
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/* vfe state */
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dri_bo_unreference(media_context->vfe_state.bo);
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bo = dri_bo_alloc(i965->intel.bufmgr,
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"vfe state",
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sizeof(struct i965_vfe_state), 32);
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assert(bo);
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media_context->vfe_state.bo = bo;
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/* extended state */
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media_context->extended_state.enabled = 0;
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switch (profile) {
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case VAProfileMPEG2Simple:
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case VAProfileMPEG2Main:
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i965_media_mpeg2_decode_init(ctx, decode_state, media_context);
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break;
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case VAProfileH264Baseline:
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case VAProfileH264Main:
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case VAProfileH264High:
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i965_media_h264_decode_init(ctx, decode_state, media_context);
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break;
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default:
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assert(0);
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break;
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}
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}
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static void
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i965_media_decode_picture(VADriverContextP ctx,
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VAProfile profile,
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union codec_state *codec_state,
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struct hw_context *hw_context)
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{
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struct i965_media_context *media_context = (struct i965_media_context *)hw_context;
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struct decode_state *decode_state = &codec_state->decode;
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i965_media_decode_init(ctx, profile, decode_state, media_context);
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assert(media_context->media_states_setup);
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media_context->media_states_setup(ctx, decode_state, media_context);
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i965_media_pipeline_setup(ctx, decode_state, media_context);
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intel_batchbuffer_flush(hw_context->batch);
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}
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static void
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i965_media_context_destroy(void *hw_context)
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{
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struct i965_media_context *media_context = (struct i965_media_context *)hw_context;
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int i;
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if (media_context->free_private_context)
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media_context->free_private_context(&media_context->private_context);
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for (i = 0; i < MAX_MEDIA_SURFACES; i++) {
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dri_bo_unreference(media_context->surface_state[i].bo);
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media_context->surface_state[i].bo = NULL;
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}
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dri_bo_unreference(media_context->extended_state.bo);
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media_context->extended_state.bo = NULL;
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dri_bo_unreference(media_context->vfe_state.bo);
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media_context->vfe_state.bo = NULL;
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dri_bo_unreference(media_context->idrt.bo);
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media_context->idrt.bo = NULL;
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dri_bo_unreference(media_context->binding_table.bo);
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media_context->binding_table.bo = NULL;
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dri_bo_unreference(media_context->curbe.bo);
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media_context->curbe.bo = NULL;
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dri_bo_unreference(media_context->indirect_object.bo);
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media_context->indirect_object.bo = NULL;
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intel_batchbuffer_free(media_context->base.batch);
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free(media_context);
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}
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struct hw_context *
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g4x_dec_hw_context_init(VADriverContextP ctx, VAProfile profile)
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{
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struct intel_driver_data *intel = intel_driver_data(ctx);
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struct i965_media_context *media_context = calloc(1, sizeof(struct i965_media_context));
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|||
|
|
|
|||
|
|
media_context->base.destroy = i965_media_context_destroy;
|
|||
|
|
media_context->base.run = i965_media_decode_picture;
|
|||
|
|
media_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
|
|||
|
|
|
|||
|
|
switch (profile) {
|
|||
|
|
case VAProfileMPEG2Simple:
|
|||
|
|
case VAProfileMPEG2Main:
|
|||
|
|
i965_media_mpeg2_dec_context_init(ctx, media_context);
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case VAProfileH264Baseline:
|
|||
|
|
case VAProfileH264Main:
|
|||
|
|
case VAProfileH264High:
|
|||
|
|
case VAProfileVC1Simple:
|
|||
|
|
case VAProfileVC1Main:
|
|||
|
|
case VAProfileVC1Advanced:
|
|||
|
|
default:
|
|||
|
|
assert(0);
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return (struct hw_context *)media_context;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
struct hw_context *
|
|||
|
|
ironlake_dec_hw_context_init(VADriverContextP ctx, VAProfile profile)
|
|||
|
|
{
|
|||
|
|
struct intel_driver_data *intel = intel_driver_data(ctx);
|
|||
|
|
struct i965_media_context *media_context = calloc(1, sizeof(struct i965_media_context));
|
|||
|
|
|
|||
|
|
media_context->base.destroy = i965_media_context_destroy;
|
|||
|
|
media_context->base.run = i965_media_decode_picture;
|
|||
|
|
media_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
|
|||
|
|
|
|||
|
|
switch (profile) {
|
|||
|
|
case VAProfileMPEG2Simple:
|
|||
|
|
case VAProfileMPEG2Main:
|
|||
|
|
i965_media_mpeg2_dec_context_init(ctx, media_context);
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case VAProfileH264Baseline:
|
|||
|
|
case VAProfileH264Main:
|
|||
|
|
case VAProfileH264High:
|
|||
|
|
i965_media_h264_dec_context_init(ctx, media_context);
|
|||
|
|
break;
|
|||
|
|
|
|||
|
|
case VAProfileVC1Simple:
|
|||
|
|
case VAProfileVC1Main:
|
|||
|
|
case VAProfileVC1Advanced:
|
|||
|
|
default:
|
|||
|
|
assert(0);
|
|||
|
|
break;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
return (struct hw_context *)media_context;
|
|||
|
|
}
|