2014-09-01 13:49:48 +02:00
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#ifndef __CIK_REG_H__
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#define __CIK_REG_H__
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#define CIK_DIDT_IND_INDEX 0xca00
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#define CIK_DIDT_IND_DATA 0xca04
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#define CIK_DC_GPIO_HPD_MASK 0x65b0
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#define CIK_DC_GPIO_HPD_A 0x65b4
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#define CIK_DC_GPIO_HPD_EN 0x65b8
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#define CIK_DC_GPIO_HPD_Y 0x65bc
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#define CIK_GRPH_CONTROL 0x6804
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# define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
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# define CIK_GRPH_DEPTH_8BPP 0
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# define CIK_GRPH_DEPTH_16BPP 1
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# define CIK_GRPH_DEPTH_32BPP 2
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# define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
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# define CIK_ADDR_SURF_2_BANK 0
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# define CIK_ADDR_SURF_4_BANK 1
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# define CIK_ADDR_SURF_8_BANK 2
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# define CIK_ADDR_SURF_16_BANK 3
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# define CIK_GRPH_Z(x) (((x) & 0x3) << 4)
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# define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
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# define CIK_ADDR_SURF_BANK_WIDTH_1 0
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# define CIK_ADDR_SURF_BANK_WIDTH_2 1
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# define CIK_ADDR_SURF_BANK_WIDTH_4 2
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# define CIK_ADDR_SURF_BANK_WIDTH_8 3
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# define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8)
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/* 8 BPP */
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# define CIK_GRPH_FORMAT_INDEXED 0
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/* 16 BPP */
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# define CIK_GRPH_FORMAT_ARGB1555 0
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# define CIK_GRPH_FORMAT_ARGB565 1
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# define CIK_GRPH_FORMAT_ARGB4444 2
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# define CIK_GRPH_FORMAT_AI88 3
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# define CIK_GRPH_FORMAT_MONO16 4
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# define CIK_GRPH_FORMAT_BGRA5551 5
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/* 32 BPP */
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# define CIK_GRPH_FORMAT_ARGB8888 0
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# define CIK_GRPH_FORMAT_ARGB2101010 1
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# define CIK_GRPH_FORMAT_32BPP_DIG 2
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# define CIK_GRPH_FORMAT_8B_ARGB2101010 3
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# define CIK_GRPH_FORMAT_BGRA1010102 4
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# define CIK_GRPH_FORMAT_8B_BGRA1010102 5
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# define CIK_GRPH_FORMAT_RGB111110 6
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# define CIK_GRPH_FORMAT_BGR101111 7
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# define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
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# define CIK_ADDR_SURF_BANK_HEIGHT_1 0
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# define CIK_ADDR_SURF_BANK_HEIGHT_2 1
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# define CIK_ADDR_SURF_BANK_HEIGHT_4 2
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# define CIK_ADDR_SURF_BANK_HEIGHT_8 3
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# define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
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# define CIK_ADDR_SURF_TILE_SPLIT_64B 0
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# define CIK_ADDR_SURF_TILE_SPLIT_128B 1
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# define CIK_ADDR_SURF_TILE_SPLIT_256B 2
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# define CIK_ADDR_SURF_TILE_SPLIT_512B 3
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# define CIK_ADDR_SURF_TILE_SPLIT_1KB 4
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# define CIK_ADDR_SURF_TILE_SPLIT_2KB 5
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# define CIK_ADDR_SURF_TILE_SPLIT_4KB 6
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# define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
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# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0
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# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 1
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# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 2
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# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 3
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# define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
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# define CIK_GRPH_ARRAY_LINEAR_GENERAL 0
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# define CIK_GRPH_ARRAY_LINEAR_ALIGNED 1
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# define CIK_GRPH_ARRAY_1D_TILED_THIN1 2
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# define CIK_GRPH_ARRAY_2D_TILED_THIN1 4
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# define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
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# define CIK_ADDR_SURF_P2 0
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# define CIK_ADDR_SURF_P4_8x16 4
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# define CIK_ADDR_SURF_P4_16x16 5
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# define CIK_ADDR_SURF_P4_16x32 6
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# define CIK_ADDR_SURF_P4_32x32 7
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# define CIK_ADDR_SURF_P8_16x16_8x16 8
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# define CIK_ADDR_SURF_P8_16x32_8x16 9
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# define CIK_ADDR_SURF_P8_32x32_8x16 10
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# define CIK_ADDR_SURF_P8_16x32_16x16 11
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# define CIK_ADDR_SURF_P8_32x32_16x16 12
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# define CIK_ADDR_SURF_P8_32x32_16x32 13
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# define CIK_ADDR_SURF_P8_32x64_32x32 14
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# define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29)
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# define CIK_DISPLAY_MICRO_TILING 0
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# define CIK_THIN_MICRO_TILING 1
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# define CIK_DEPTH_MICRO_TILING 2
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# define CIK_ROTATED_MICRO_TILING 4
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/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
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#define CIK_CUR_CONTROL 0x6998
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# define CIK_CURSOR_EN (1 << 0)
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# define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8)
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# define CIK_CURSOR_MONO 0
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# define CIK_CURSOR_24_1 1
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# define CIK_CURSOR_24_8_PRE_MULT 2
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# define CIK_CURSOR_24_8_UNPRE_MULT 3
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# define CIK_CURSOR_2X_MAGNIFY (1 << 16)
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# define CIK_CURSOR_FORCE_MC_ON (1 << 20)
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# define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
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# define CIK_CURSOR_URGENT_ALWAYS 0
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# define CIK_CURSOR_URGENT_1_8 1
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# define CIK_CURSOR_URGENT_1_4 2
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# define CIK_CURSOR_URGENT_3_8 3
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# define CIK_CURSOR_URGENT_1_2 4
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#define CIK_CUR_SURFACE_ADDRESS 0x699c
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# define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000
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#define CIK_CUR_SIZE 0x69a0
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#define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4
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#define CIK_CUR_POSITION 0x69a8
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#define CIK_CUR_HOT_SPOT 0x69ac
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#define CIK_CUR_COLOR1 0x69b0
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#define CIK_CUR_COLOR2 0x69b4
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#define CIK_CUR_UPDATE 0x69b8
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# define CIK_CURSOR_UPDATE_PENDING (1 << 0)
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# define CIK_CURSOR_UPDATE_TAKEN (1 << 1)
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# define CIK_CURSOR_UPDATE_LOCK (1 << 16)
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# define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
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#define CIK_ALPHA_CONTROL 0x6af0
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# define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1)
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#define CIK_LB_DATA_FORMAT 0x6b00
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# define CIK_INTERLEAVE_EN (1 << 3)
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#define CIK_LB_DESKTOP_HEIGHT 0x6b0c
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2014-12-27 16:58:21 +01:00
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#define CP_HQD_IQ_RPTR 0xC970u
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#define AQL_ENABLE (1U << 0)
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#define IDLE (1 << 2)
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struct cik_mqd {
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uint32_t header;
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uint32_t compute_dispatch_initiator;
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uint32_t compute_dim_x;
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uint32_t compute_dim_y;
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uint32_t compute_dim_z;
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uint32_t compute_start_x;
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uint32_t compute_start_y;
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uint32_t compute_start_z;
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uint32_t compute_num_thread_x;
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uint32_t compute_num_thread_y;
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uint32_t compute_num_thread_z;
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uint32_t compute_pipelinestat_enable;
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uint32_t compute_perfcount_enable;
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uint32_t compute_pgm_lo;
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uint32_t compute_pgm_hi;
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uint32_t compute_tba_lo;
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uint32_t compute_tba_hi;
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uint32_t compute_tma_lo;
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uint32_t compute_tma_hi;
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uint32_t compute_pgm_rsrc1;
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uint32_t compute_pgm_rsrc2;
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uint32_t compute_vmid;
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uint32_t compute_resource_limits;
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uint32_t compute_static_thread_mgmt_se0;
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uint32_t compute_static_thread_mgmt_se1;
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uint32_t compute_tmpring_size;
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uint32_t compute_static_thread_mgmt_se2;
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uint32_t compute_static_thread_mgmt_se3;
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uint32_t compute_restart_x;
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uint32_t compute_restart_y;
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uint32_t compute_restart_z;
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uint32_t compute_thread_trace_enable;
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uint32_t compute_misc_reserved;
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uint32_t compute_user_data_0;
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uint32_t compute_user_data_1;
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uint32_t compute_user_data_2;
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uint32_t compute_user_data_3;
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uint32_t compute_user_data_4;
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uint32_t compute_user_data_5;
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uint32_t compute_user_data_6;
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uint32_t compute_user_data_7;
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uint32_t compute_user_data_8;
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uint32_t compute_user_data_9;
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uint32_t compute_user_data_10;
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uint32_t compute_user_data_11;
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uint32_t compute_user_data_12;
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uint32_t compute_user_data_13;
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uint32_t compute_user_data_14;
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uint32_t compute_user_data_15;
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uint32_t cp_compute_csinvoc_count_lo;
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uint32_t cp_compute_csinvoc_count_hi;
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uint32_t cp_mqd_base_addr_lo;
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uint32_t cp_mqd_base_addr_hi;
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uint32_t cp_hqd_active;
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uint32_t cp_hqd_vmid;
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uint32_t cp_hqd_persistent_state;
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uint32_t cp_hqd_pipe_priority;
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uint32_t cp_hqd_queue_priority;
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uint32_t cp_hqd_quantum;
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uint32_t cp_hqd_pq_base_lo;
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uint32_t cp_hqd_pq_base_hi;
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uint32_t cp_hqd_pq_rptr;
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uint32_t cp_hqd_pq_rptr_report_addr_lo;
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uint32_t cp_hqd_pq_rptr_report_addr_hi;
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uint32_t cp_hqd_pq_wptr_poll_addr_lo;
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uint32_t cp_hqd_pq_wptr_poll_addr_hi;
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uint32_t cp_hqd_pq_doorbell_control;
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uint32_t cp_hqd_pq_wptr;
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uint32_t cp_hqd_pq_control;
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uint32_t cp_hqd_ib_base_addr_lo;
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uint32_t cp_hqd_ib_base_addr_hi;
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uint32_t cp_hqd_ib_rptr;
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uint32_t cp_hqd_ib_control;
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uint32_t cp_hqd_iq_timer;
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uint32_t cp_hqd_iq_rptr;
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uint32_t cp_hqd_dequeue_request;
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uint32_t cp_hqd_dma_offload;
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uint32_t cp_hqd_sema_cmd;
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uint32_t cp_hqd_msg_type;
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uint32_t cp_hqd_atomic0_preop_lo;
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uint32_t cp_hqd_atomic0_preop_hi;
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uint32_t cp_hqd_atomic1_preop_lo;
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uint32_t cp_hqd_atomic1_preop_hi;
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uint32_t cp_hqd_hq_status0;
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uint32_t cp_hqd_hq_control0;
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uint32_t cp_mqd_control;
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uint32_t cp_mqd_query_time_lo;
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uint32_t cp_mqd_query_time_hi;
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uint32_t cp_mqd_connect_start_time_lo;
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uint32_t cp_mqd_connect_start_time_hi;
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uint32_t cp_mqd_connect_end_time_lo;
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uint32_t cp_mqd_connect_end_time_hi;
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uint32_t cp_mqd_connect_end_wf_count;
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uint32_t cp_mqd_connect_end_pq_rptr;
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uint32_t cp_mqd_connect_end_pq_wptr;
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uint32_t cp_mqd_connect_end_ib_rptr;
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uint32_t reserved_96;
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uint32_t reserved_97;
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uint32_t reserved_98;
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uint32_t reserved_99;
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uint32_t iqtimer_pkt_header;
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uint32_t iqtimer_pkt_dw0;
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|
uint32_t iqtimer_pkt_dw1;
|
|
|
|
|
uint32_t iqtimer_pkt_dw2;
|
|
|
|
|
uint32_t iqtimer_pkt_dw3;
|
|
|
|
|
uint32_t iqtimer_pkt_dw4;
|
|
|
|
|
uint32_t iqtimer_pkt_dw5;
|
|
|
|
|
uint32_t iqtimer_pkt_dw6;
|
|
|
|
|
uint32_t reserved_108;
|
|
|
|
|
uint32_t reserved_109;
|
|
|
|
|
uint32_t reserved_110;
|
|
|
|
|
uint32_t reserved_111;
|
|
|
|
|
uint32_t queue_doorbell_id0;
|
|
|
|
|
uint32_t queue_doorbell_id1;
|
|
|
|
|
uint32_t queue_doorbell_id2;
|
|
|
|
|
uint32_t queue_doorbell_id3;
|
|
|
|
|
uint32_t queue_doorbell_id4;
|
|
|
|
|
uint32_t queue_doorbell_id5;
|
|
|
|
|
uint32_t queue_doorbell_id6;
|
|
|
|
|
uint32_t queue_doorbell_id7;
|
|
|
|
|
uint32_t queue_doorbell_id8;
|
|
|
|
|
uint32_t queue_doorbell_id9;
|
|
|
|
|
uint32_t queue_doorbell_id10;
|
|
|
|
|
uint32_t queue_doorbell_id11;
|
|
|
|
|
uint32_t queue_doorbell_id12;
|
|
|
|
|
uint32_t queue_doorbell_id13;
|
|
|
|
|
uint32_t queue_doorbell_id14;
|
|
|
|
|
uint32_t queue_doorbell_id15;
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-01 13:49:48 +02:00
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|
|
#endif
|
