forked from KolibriOS/kolibrios
389 lines
13 KiB
PHP
389 lines
13 KiB
PHP
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2005-01-11 10:31 ******* Source: ATtiny15.xml ************
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn15def.inc"
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;* Title : Register/Bit Definitions for the ATtiny15
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;* Date : 2005-01-11
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;* Version : 2.14
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny15
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN15DEF_INC_
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#define _TN15DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny15
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#pragma AVRPART ADMIN PART_NAME ATtiny15
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x90
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.equ SIGNATURE_002 = 0x06
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#pragma AVRPART CORE CORE_VERSION V0E
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ GIMSK = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK = 0x39
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.equ TIFR = 0x38
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0 = 0x33
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.equ TCNT0 = 0x32
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.equ OSCCAL = 0x31
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.equ TCCR1 = 0x30
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.equ TCNT1 = 0x2f
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.equ OCR1A = 0x2e
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.equ OCR1B = 0x2d
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.equ SFIOR = 0x2c
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.equ WDTCR = 0x21
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.equ EEAR = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ ACSR = 0x08
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.equ ADMUX = 0x07
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.equ ADCSR = 0x06
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.equ ADCH = 0x05
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.equ ADCL = 0x04
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; ***** BIT DEFINITIONS **************************************************
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; ***** AD_CONVERTER *****************
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; ADMUX - The ADC multiplexer Selection Register
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.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
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.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
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.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
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.equ ADLAR = 5 ; Left Adjust Result
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.equ REFS0 = 6 ; Reference Selection Bit 0
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.equ REFS1 = 7 ; Reference Selection Bit 1
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; ADCSR - The ADC Control and Status register
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.equ ADPS0 = 0 ; ADC Prescaler Select Bits
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.equ ADPS1 = 1 ; ADC Prescaler Select Bits
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.equ ADPS2 = 2 ; ADC Prescaler Select Bits
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.equ ADIE = 3 ; ADC Interrupt Enable
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.equ ADIF = 4 ; ADC Interrupt Flag
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.equ ADFR = 5 ; ADC Free Running Select
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.equ ADSC = 6 ; ADC Start Conversion
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.equ ADEN = 7 ; ADC Enable
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; ADCH - ADC Data Register High Byte
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.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
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.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
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.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
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.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
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.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
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.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
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.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
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.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
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; ADCL - ADC Data Register Low Byte
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.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
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.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
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.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
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.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
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.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
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.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
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.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
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.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ AINBG6 = ACBG ; For compatibility
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.equ ACD = 7 ; Analog Comparator Disable
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; ***** EEPROM ***********************
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; EEAR - EEPROM Read/Write Access
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.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEWE = 1 ; EEPROM Write Enable
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.equ EEMWE = 2 ; EEPROM Master Write Enable
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.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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; ***** PORTB ************************
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; PORTB - Data Register, Port B
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.equ PORTB0 = 0 ;
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ;
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ;
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ;
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ;
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.equ PB4 = 4 ; For compatibility
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; DDRB - Data Direction Register, Port B
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.equ DDB0 = 0 ;
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.equ DDB1 = 1 ;
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.equ DDB2 = 2 ;
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.equ DDB3 = 3 ;
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.equ DDB4 = 4 ;
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.equ DDB5 = 5 ;
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; PINB - Input Pins, Port B
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.equ PINB0 = 0 ;
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.equ PINB1 = 1 ;
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.equ PINB2 = 2 ;
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.equ PINB3 = 3 ;
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.equ PINB4 = 4 ;
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.equ PINB5 = 5 ;
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; ***** TIMER_COUNTER_0 **************
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; TIMSK - Timer/Counter Interrupt Mask Register
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.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
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; TIFR - Timer/Counter Interrupt Flag register
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.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
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; TCCR0 - Timer/Counter0 Control Register
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.equ CS00 = 0 ; Clock Select0 bit 0
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.equ CS01 = 1 ; Clock Select0 bit 1
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.equ CS02 = 2 ; Clock Select0 bit 2
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; TCNT0 - Timer Counter 0
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.equ TCNT00 = 0 ; Timer Counter 0 bit 0
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.equ TCNT01 = 1 ; Timer Counter 0 bit 1
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.equ TCNT02 = 2 ; Timer Counter 0 bit 2
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.equ TCNT03 = 3 ; Timer Counter 0 bit 3
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.equ TCNT04 = 4 ; Timer Counter 0 bit 4
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.equ TCNT05 = 5 ; Timer Counter 0 bit 5
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.equ TCNT06 = 6 ; Timer Counter 0 bit 6
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.equ TCNT07 = 7 ; Timer Counter 0 bit 7
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; ***** WATCHDOG *********************
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; WDTCR - Watchdog Timer Control Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDTOE = 4 ; RW
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.equ WDDE = WDTOE ; For compatibility
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; MCUCR - MCU Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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.equ SM0 = 3 ; Sleep Mode Select Bit 0
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.equ SM1 = 4 ; Sleep Mode Select Bit 1
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.equ SE = 5 ; Sleep Enable
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.equ PUD = 6 ; Pull-up Disable
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; MCUSR - MCU Status register
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.equ PORF = 0 ; Power-On Reset Flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ BORF = 2 ; Brown-out Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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; OSCCAL - Status Register
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.equ CAL0 = 0 ; Oscillator Calibration Value Bit 0
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.equ CAL1 = 1 ; Oscillator Calibration Value Bit 1
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.equ CAL2 = 2 ; Oscillator Calibration Value Bit 2
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.equ CAL3 = 3 ; Oscillator Calibration Value Bit 3
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.equ CAL4 = 4
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.equ CAL5 = 5 ; Oscillator Calibration Value Bit 5
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.equ CAL6 = 6 ; Oscillator Calibration Value Bit 6
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.equ CAL7 = 7 ; Oscillator Calibration Value Bit 7
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; ***** EXTERNAL_INTERRUPT ***********
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; GIMSK - General Interrupt Mask Register
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.equ PCIE = 5 ; Pin Change Interrupt Enable
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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; GIFR - General Interrupt Flag register
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.equ PCIF = 5 ; Pin Change Interrupt Flag
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.equ INTF0 = 6 ; External Interrupt Flag 0
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; ***** TIMER_COUNTER_1 **************
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; TCCR1 - Timer/Counter Control Register
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.equ CS10 = 0 ; Clock Select Bits
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.equ CS11 = 1 ; Clock Select Bits
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.equ CS12 = 2 ; Clock Select Bits
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.equ CS13 = 3 ; Clock Select Bits
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.equ COM1A0 = 4 ; Compare Output Mode, Bit 1
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.equ COM1A1 = 5 ; Compare Output Mode, Bit 0
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.equ PWM1 = 6 ; Pulse Width Modulator Enable
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.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match
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; TCNT1 - Timer/Counter Register
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.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0
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.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1
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.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2
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.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3
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.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4
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.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5
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.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6
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.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7
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; OCR1A - Output Compare Register
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.equ OCR1A0 = 0 ; Output Compare Register A Bit 0
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.equ OCR1A1 = 1 ; Output Compare Register A Bit 1
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.equ OCR1A2 = 2 ; Output Compare Register A Bit 2
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.equ OCR1A3 = 3 ; Output Compare Register A Bit 3
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.equ OCR1A4 = 4 ; Output Compare Register A Bit 4
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.equ OCR1A5 = 5 ; Output Compare Register A Bit 5
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.equ OCR1A6 = 6 ; Output Compare Register A Bit 6
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.equ OCR1A7 = 7 ; Output Compare Register A Bit 7
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; OCR1B - Output Compare Register
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.equ OCR1B0 = 0 ; Output Compare Register B Bit 0
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.equ OCR1B1 = 1 ; Output Compare Register B Bit 1
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.equ OCR1B2 = 2 ; Output Compare Register B Bit 2
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.equ OCR1B3 = 3 ; Output Compare Register B Bit 3
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.equ OCR1B4 = 4 ; Output Compare Register B Bit 4
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.equ OCR1B5 = 5 ; Output Compare Register B Bit 5
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.equ OCR1B6 = 6 ; Output Compare Register B Bit 6
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.equ OCR1B7 = 7 ; Output Compare Register B Bit 7
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; TIMSK - Timer/Counter Interrupt Mask Register
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.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
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.equ OCIE1A = 6 ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
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; TIFR - Timer/Counter Interrupt Flag Register
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.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
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.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A
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; SFIOR - Special Function IO Register
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.equ PSR0 = 0 ; Prescaler Reset Timer/Counter0
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.equ PSR1 = 1 ; Prescaler Reset Timer/Counter1
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.equ FOC1A = 2 ; Force Output Compare 1A
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; ***** LOCKSBITS ********************************************************
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.equ LB1 = 0 ; Lockbit
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.equ LB2 = 1 ; Lockbit
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; ***** FUSES ************************************************************
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; LOW fuse bits
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; ***** CPU REGISTER DEFINITIONS *****************************************
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.def XH = r27
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.def XL = r26
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.def YH = r29
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.def YL = r28
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.def ZH = r31
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.def ZL = r30
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; ***** DATA MEMORY DECLARATIONS *****************************************
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.equ FLASHEND = 0x01ff ; Note: Word address
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.equ IOEND = 0x003f
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.equ SRAM_SIZE = 0
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.equ RAMEND = 0x0000
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.equ XRAMEND = 0x0000
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.equ E2END = 0x003f
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||
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.equ EEPROMEND = 0x003f
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||
|
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.equ EEADRBITS = 6
|
||
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#pragma AVRPART MEMORY PROG_FLASH 1024
|
||
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#pragma AVRPART MEMORY EEPROM 64
|
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#pragma AVRPART MEMORY INT_SRAM SIZE 0
|
||
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#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0
|
||
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||
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|
; ***** INTERRUPT VECTORS ************************************************
|
||
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.equ INT0addr = 0x0001 ; External Interrupt 0
|
||
|
|
.equ PCI0addr = 0x0002 ; External Interrupt Request 0
|
||
|
|
.equ OC1addr = 0x0003 ; Timer/Counter1 Compare Match
|
||
|
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.equ OVF1addr = 0x0004 ; Timer/Counter1 Overflow
|
||
|
|
.equ OVF0addr = 0x0005 ; Timer/Counter0 Overflow
|
||
|
|
.equ ERDYaddr = 0x0006 ; EEPROM Ready
|
||
|
|
.equ ACIaddr = 0x0007 ; Analog Comparator
|
||
|
|
.equ ADCCaddr = 0x0008 ; ADC Conversion Ready
|
||
|
|
|
||
|
|
.equ INT_VECTORS_SIZE = 9 ; size in words
|
||
|
|
|
||
|
|
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
||
|
|
|
||
|
|
#endif /* _TN15DEF_INC_ */
|
||
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|
|
||
|
|
; ***** END OF FILE ******************************************************
|