forked from KolibriOS/kolibrios
230 lines
7.2 KiB
C++
230 lines
7.2 KiB
C++
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bool FindUSBControllers()
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{
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bool retval = false;
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u32_t bus, last_bus;
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PCITAG tag;
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if( (last_bus = PciApi(1))==-1)
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return retval;
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dbgprintf("last bus %x\n", last_bus);
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for(bus=0;bus<=last_bus;bus++)
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{
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u32_t devfn;
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for(devfn=0;devfn<256;devfn++)
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{
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hc_t *hc;
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u32_t id;
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u16_t pcicmd;
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u16_t devclass;
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u8_t interface;
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int i;
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interface = PciRead8(bus,devfn, 0x09);
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devclass = PciRead16(bus,devfn, 0x0A);
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if( devclass != 0x0C03)
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continue;
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if( interface != 0)
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continue;
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pcicmd = PciRead16(bus,devfn, PCI_COMMAND);
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if (! pcicmd & PCI_COMMAND_IO)
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continue;
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hc = (hc_t*)kmalloc(sizeof(hc_t), 0);
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INIT_LIST_HEAD(&hc->list);
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INIT_LIST_HEAD(&hc->rq_list);
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hc->pciId = PciRead32(bus,devfn, 0);
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hc->PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7);
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hc->irq_line = PciRead32(bus,devfn, 0x3C) & 0xFF;
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for (i = 0; i < 6; i++)
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{
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u32_t base;
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bool validSize;
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base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));
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if(base)
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{
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if (base & PCI_MAP_IO) {
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hc->ioBase[i] = (addr_t)PCIGETIO(base);
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hc->memType[i] = base & PCI_MAP_IO_ATTR_MASK;
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} else {
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hc->memBase[i] = (u32_t)PCIGETMEMORY(base);
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hc->memType[i] = base & PCI_MAP_MEMORY_ATTR_MASK;
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}
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}
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};
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dbgprintf("host controller %x bus %x devfn %x, IRQ %d\n",
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hc->pciId, bus, devfn, hc->irq_line);
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list_add_tail(&hc->list, &hc_list);
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retval = true;
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};
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};
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return retval;
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};
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#if 0
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/* these helpers provide future and backwards compatibility
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* for accessing popular PCI BAR info */
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#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
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#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
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#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
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#define pci_resource_len(dev,bar) \
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((pci_resource_start((dev), (bar)) == 0 && \
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pci_resource_end((dev), (bar)) == \
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pci_resource_start((dev), (bar))) ? 0 : \
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\
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(pci_resource_end((dev), (bar)) - \
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pci_resource_start((dev), (bar)) + 1))
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static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
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{
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return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
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}
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static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
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{
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int wait_time, delta;
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void __iomem *base, *op_reg_base;
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u32 hcc_params, val;
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u8 offset, cap_length;
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int count = 256/4;
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int tried_handoff = 0;
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if (!mmio_resource_enabled(pdev, 0))
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return;
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base = pci_ioremap_bar(pdev, 0);
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if (base == NULL)
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return;
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cap_length = readb(base);
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op_reg_base = base + cap_length;
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/* EHCI 0.96 and later may have "extended capabilities"
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* spec section 5.1 explains the bios handoff, e.g. for
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* booting from USB disk or using a usb keyboard
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*/
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hcc_params = readl(base + EHCI_HCC_PARAMS);
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offset = (hcc_params >> 8) & 0xff;
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while (offset && --count) {
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u32 cap;
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int msec;
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pci_read_config_dword(pdev, offset, &cap);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff support */
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if ((cap & EHCI_USBLEGSUP_BIOS)) {
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dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
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#if 0
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/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
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* but that seems dubious in general (the BIOS left it off intentionally)
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* and is known to prevent some systems from booting. so we won't do this
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* unless maybe we can determine when we're on a system that needs SMI forced.
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*/
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/* BIOS workaround (?): be sure the
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* pre-Linux code receives the SMI
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*/
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pci_read_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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&val);
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pci_write_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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val | EHCI_USBLEGCTLSTS_SOOE);
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#endif
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/* some systems get upset if this semaphore is
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* set for any other reason than forcing a BIOS
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* handoff..
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*/
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pci_write_config_byte(pdev, offset + 3, 1);
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}
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/* if boot firmware now owns EHCI, spin till
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* it hands it over.
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*/
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msec = 1000;
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while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
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tried_handoff = 1;
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msleep(10);
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msec -= 10;
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pci_read_config_dword(pdev, offset, &cap);
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}
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if (cap & EHCI_USBLEGSUP_BIOS) {
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/* well, possibly buggy BIOS... try to shut
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* it down, and hope nothing goes too wrong
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*/
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dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
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" (BIOS bug?) %08x\n", cap);
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pci_write_config_byte(pdev, offset + 2, 0);
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}
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/* just in case, always disable EHCI SMIs */
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pci_write_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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0);
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/* If the BIOS ever owned the controller then we
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* can't expect any power sessions to remain intact.
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*/
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if (tried_handoff)
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writel(0, op_reg_base + EHCI_CONFIGFLAG);
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break;
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case 0: /* illegal reserved capability */
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cap = 0;
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/* FALLTHROUGH */
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default:
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dev_warn(&pdev->dev, "EHCI: unrecognized capability "
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"%02x\n", cap & 0xff);
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break;
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}
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offset = (cap >> 8) & 0xff;
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}
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if (!count)
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dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
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/*
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* halt EHCI & disable its interrupts in any case
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*/
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val = readl(op_reg_base + EHCI_USBSTS);
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if ((val & EHCI_USBSTS_HALTED) == 0) {
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val = readl(op_reg_base + EHCI_USBCMD);
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val &= ~EHCI_USBCMD_RUN;
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writel(val, op_reg_base + EHCI_USBCMD);
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wait_time = 2000;
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delta = 100;
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do {
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writel(0x3f, op_reg_base + EHCI_USBSTS);
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udelay(delta);
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wait_time -= delta;
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val = readl(op_reg_base + EHCI_USBSTS);
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if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
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break;
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}
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} while (wait_time > 0);
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}
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writel(0, op_reg_base + EHCI_USBINTR);
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writel(0x3f, op_reg_base + EHCI_USBSTS);
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iounmap(base);
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return;
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}
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#endif
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