forked from KolibriOS/kolibrios
1312 lines
35 KiB
C
1312 lines
35 KiB
C
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* New plane/sprite handling.
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*
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* The older chips had a separate interface for programming plane related
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* registers; newer ones are much simpler and we can use the new DRM plane
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* support.
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*/
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_rect.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
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{
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/* paranoia */
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if (!mode->crtc_htotal)
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return 1;
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return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
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}
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static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
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{
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struct drm_device *dev = crtc->base.dev;
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const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
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enum pipe pipe = crtc->pipe;
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long timeout = msecs_to_jiffies_timeout(1);
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int scanline, min, max, vblank_start;
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DEFINE_WAIT(wait);
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WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
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vblank_start = mode->crtc_vblank_start;
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if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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vblank_start = DIV_ROUND_UP(vblank_start, 2);
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/* FIXME needs to be calibrated sensibly */
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min = vblank_start - usecs_to_scanlines(mode, 100);
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max = vblank_start - 1;
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if (min <= 0 || max <= 0)
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return false;
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// if (WARN_ON(drm_vblank_get(dev, pipe)))
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// return false;
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// local_irq_disable();
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// trace_i915_pipe_update_start(crtc, min, max);
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for (;;) {
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/*
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* prepare_to_wait() has a memory barrier, which guarantees
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* other CPUs can see the task state update by the time we
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* read the scanline.
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*/
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prepare_to_wait(&crtc->vbl_wait, &wait, TASK_UNINTERRUPTIBLE);
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scanline = intel_get_crtc_scanline(crtc);
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if (scanline < min || scanline > max)
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break;
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if (timeout <= 0) {
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DRM_ERROR("Potential atomic update failure on pipe %c\n",
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pipe_name(crtc->pipe));
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break;
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}
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// local_irq_enable();
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schedule_timeout(timeout);
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timeout = 0;
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// local_irq_disable();
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}
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finish_wait(&crtc->vbl_wait, &wait);
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// drm_vblank_put(dev, pipe);
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*start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
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// trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
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return true;
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}
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static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
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{
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struct drm_device *dev = crtc->base.dev;
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enum pipe pipe = crtc->pipe;
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u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
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// trace_i915_pipe_update_end(crtc, end_vbl_count);
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// local_irq_enable();
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if (start_vbl_count != end_vbl_count)
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DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
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pipe_name(pipe), start_vbl_count, end_vbl_count);
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}
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static void intel_update_primary_plane(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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int reg = DSPCNTR(crtc->plane);
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if (crtc->primary_enabled)
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I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
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else
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I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
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}
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static void
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vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t x, uint32_t y,
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uint32_t src_w, uint32_t src_h)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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unsigned long sprsurf_offset, linear_offset;
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int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
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u32 start_vbl_count;
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bool atomic_update;
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sprctl = I915_READ(SPCNTR(pipe, plane));
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/* Mask out pixel format bits in case we change it */
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sprctl &= ~SP_PIXFORMAT_MASK;
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sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
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sprctl &= ~SP_TILED;
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switch (fb->pixel_format) {
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case DRM_FORMAT_YUYV:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
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break;
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case DRM_FORMAT_YVYU:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
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break;
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case DRM_FORMAT_UYVY:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
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break;
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case DRM_FORMAT_VYUY:
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sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
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break;
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case DRM_FORMAT_RGB565:
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sprctl |= SP_FORMAT_BGR565;
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break;
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case DRM_FORMAT_XRGB8888:
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sprctl |= SP_FORMAT_BGRX8888;
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break;
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case DRM_FORMAT_ARGB8888:
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sprctl |= SP_FORMAT_BGRA8888;
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break;
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case DRM_FORMAT_XBGR2101010:
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sprctl |= SP_FORMAT_RGBX1010102;
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break;
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case DRM_FORMAT_ABGR2101010:
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sprctl |= SP_FORMAT_RGBA1010102;
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break;
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case DRM_FORMAT_XBGR8888:
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sprctl |= SP_FORMAT_RGBX8888;
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break;
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case DRM_FORMAT_ABGR8888:
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sprctl |= SP_FORMAT_RGBA8888;
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break;
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default:
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/*
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* If we get here one of the upper layers failed to filter
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* out the unsupported plane formats
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*/
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BUG();
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break;
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}
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/*
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* Enable gamma to match primary/cursor plane behaviour.
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* FIXME should be user controllable via propertiesa.
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*/
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sprctl |= SP_GAMMA_ENABLE;
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if (obj->tiling_mode != I915_TILING_NONE)
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sprctl |= SP_TILED;
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sprctl |= SP_ENABLE;
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intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
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pixel_size, true,
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src_w != crtc_w || src_h != crtc_h);
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/* Sizes are 0 based */
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src_w--;
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src_h--;
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crtc_w--;
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crtc_h--;
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linear_offset = y * fb->pitches[0] + x * pixel_size;
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sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
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obj->tiling_mode,
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pixel_size,
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fb->pitches[0]);
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linear_offset -= sprsurf_offset;
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atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
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intel_update_primary_plane(intel_crtc);
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I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
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I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
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if (obj->tiling_mode != I915_TILING_NONE)
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I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
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else
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I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
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I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
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I915_WRITE(SPCNTR(pipe, plane), sprctl);
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I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
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sprsurf_offset);
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intel_flush_primary_plane(dev_priv, intel_crtc->plane);
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if (atomic_update)
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intel_pipe_update_end(intel_crtc, start_vbl_count);
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}
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static void
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vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 start_vbl_count;
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bool atomic_update;
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atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
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intel_update_primary_plane(intel_crtc);
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I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
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~SP_ENABLE);
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/* Activate double buffered register update */
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I915_WRITE(SPSURF(pipe, plane), 0);
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intel_flush_primary_plane(dev_priv, intel_crtc->plane);
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if (atomic_update)
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intel_pipe_update_end(intel_crtc, start_vbl_count);
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intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
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}
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static int
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vlv_update_colorkey(struct drm_plane *dplane,
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struct drm_intel_sprite_colorkey *key)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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if (key->flags & I915_SET_COLORKEY_DESTINATION)
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return -EINVAL;
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I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
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I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
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I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
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sprctl = I915_READ(SPCNTR(pipe, plane));
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sprctl &= ~SP_SOURCE_KEY;
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if (key->flags & I915_SET_COLORKEY_SOURCE)
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sprctl |= SP_SOURCE_KEY;
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I915_WRITE(SPCNTR(pipe, plane), sprctl);
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POSTING_READ(SPKEYMSK(pipe, plane));
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return 0;
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}
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static void
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vlv_get_colorkey(struct drm_plane *dplane,
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struct drm_intel_sprite_colorkey *key)
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{
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struct drm_device *dev = dplane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(dplane);
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int pipe = intel_plane->pipe;
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int plane = intel_plane->plane;
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u32 sprctl;
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key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
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key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
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key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
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sprctl = I915_READ(SPCNTR(pipe, plane));
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if (sprctl & SP_SOURCE_KEY)
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key->flags = I915_SET_COLORKEY_SOURCE;
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else
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key->flags = I915_SET_COLORKEY_NONE;
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}
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static void
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ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t x, uint32_t y,
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uint32_t src_w, uint32_t src_h)
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{
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(plane);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_plane->pipe;
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u32 sprctl, sprscale = 0;
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unsigned long sprsurf_offset, linear_offset;
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int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
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u32 start_vbl_count;
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bool atomic_update;
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sprctl = I915_READ(SPRCTL(pipe));
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/* Mask out pixel format bits in case we change it */
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sprctl &= ~SPRITE_PIXFORMAT_MASK;
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sprctl &= ~SPRITE_RGB_ORDER_RGBX;
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sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
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sprctl &= ~SPRITE_TILED;
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switch (fb->pixel_format) {
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case DRM_FORMAT_XBGR8888:
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sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
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break;
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case DRM_FORMAT_XRGB8888:
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sprctl |= SPRITE_FORMAT_RGBX888;
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break;
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case DRM_FORMAT_YUYV:
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sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
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break;
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case DRM_FORMAT_YVYU:
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sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
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break;
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case DRM_FORMAT_UYVY:
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sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
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break;
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case DRM_FORMAT_VYUY:
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sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
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break;
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default:
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BUG();
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}
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/*
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* Enable gamma to match primary/cursor plane behaviour.
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* FIXME should be user controllable via propertiesa.
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*/
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sprctl |= SPRITE_GAMMA_ENABLE;
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if (obj->tiling_mode != I915_TILING_NONE)
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sprctl |= SPRITE_TILED;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
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else
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sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
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sprctl |= SPRITE_ENABLE;
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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sprctl |= SPRITE_PIPE_CSC_ENABLE;
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intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
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true,
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src_w != crtc_w || src_h != crtc_h);
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/* Sizes are 0 based */
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src_w--;
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src_h--;
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crtc_w--;
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crtc_h--;
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if (crtc_w != src_w || crtc_h != src_h)
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sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
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linear_offset = y * fb->pitches[0] + x * pixel_size;
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sprsurf_offset =
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intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
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pixel_size, fb->pitches[0]);
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linear_offset -= sprsurf_offset;
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atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
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intel_update_primary_plane(intel_crtc);
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I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
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I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
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/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
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* register */
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
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else if (obj->tiling_mode != I915_TILING_NONE)
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I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
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else
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I915_WRITE(SPRLINOFF(pipe), linear_offset);
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I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
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if (intel_plane->can_scale)
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I915_WRITE(SPRSCALE(pipe), sprscale);
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I915_WRITE(SPRCTL(pipe), sprctl);
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I915_WRITE(SPRSURF(pipe),
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i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
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intel_flush_primary_plane(dev_priv, intel_crtc->plane);
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if (atomic_update)
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intel_pipe_update_end(intel_crtc, start_vbl_count);
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}
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static void
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ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
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{
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struct drm_device *dev = plane->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_plane *intel_plane = to_intel_plane(plane);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_plane->pipe;
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u32 start_vbl_count;
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bool atomic_update;
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atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
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|
|
intel_update_primary_plane(intel_crtc);
|
|
|
|
I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
|
|
/* Can't leave the scaler enabled... */
|
|
if (intel_plane->can_scale)
|
|
I915_WRITE(SPRSCALE(pipe), 0);
|
|
/* Activate double buffered register update */
|
|
I915_WRITE(SPRSURF(pipe), 0);
|
|
|
|
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
|
|
|
|
if (atomic_update)
|
|
intel_pipe_update_end(intel_crtc, start_vbl_count);
|
|
|
|
/*
|
|
* Avoid underruns when disabling the sprite.
|
|
* FIXME remove once watermark updates are done properly.
|
|
*/
|
|
intel_wait_for_vblank(dev, pipe);
|
|
|
|
intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
|
|
}
|
|
|
|
static int
|
|
ivb_update_colorkey(struct drm_plane *plane,
|
|
struct drm_intel_sprite_colorkey *key)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane;
|
|
u32 sprctl;
|
|
int ret = 0;
|
|
|
|
intel_plane = to_intel_plane(plane);
|
|
|
|
I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
|
|
I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
|
|
I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
|
|
|
|
sprctl = I915_READ(SPRCTL(intel_plane->pipe));
|
|
sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
|
|
if (key->flags & I915_SET_COLORKEY_DESTINATION)
|
|
sprctl |= SPRITE_DEST_KEY;
|
|
else if (key->flags & I915_SET_COLORKEY_SOURCE)
|
|
sprctl |= SPRITE_SOURCE_KEY;
|
|
I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
|
|
|
|
POSTING_READ(SPRKEYMSK(intel_plane->pipe));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane;
|
|
u32 sprctl;
|
|
|
|
intel_plane = to_intel_plane(plane);
|
|
|
|
key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
|
|
key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
|
|
key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
|
|
key->flags = 0;
|
|
|
|
sprctl = I915_READ(SPRCTL(intel_plane->pipe));
|
|
|
|
if (sprctl & SPRITE_DEST_KEY)
|
|
key->flags = I915_SET_COLORKEY_DESTINATION;
|
|
else if (sprctl & SPRITE_SOURCE_KEY)
|
|
key->flags = I915_SET_COLORKEY_SOURCE;
|
|
else
|
|
key->flags = I915_SET_COLORKEY_NONE;
|
|
}
|
|
|
|
static void
|
|
ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
|
|
unsigned int crtc_w, unsigned int crtc_h,
|
|
uint32_t x, uint32_t y,
|
|
uint32_t src_w, uint32_t src_h)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
int pipe = intel_plane->pipe;
|
|
unsigned long dvssurf_offset, linear_offset;
|
|
u32 dvscntr, dvsscale;
|
|
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
|
|
u32 start_vbl_count;
|
|
bool atomic_update;
|
|
|
|
dvscntr = I915_READ(DVSCNTR(pipe));
|
|
|
|
/* Mask out pixel format bits in case we change it */
|
|
dvscntr &= ~DVS_PIXFORMAT_MASK;
|
|
dvscntr &= ~DVS_RGB_ORDER_XBGR;
|
|
dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
|
|
dvscntr &= ~DVS_TILED;
|
|
|
|
switch (fb->pixel_format) {
|
|
case DRM_FORMAT_XBGR8888:
|
|
dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
|
|
break;
|
|
case DRM_FORMAT_XRGB8888:
|
|
dvscntr |= DVS_FORMAT_RGBX888;
|
|
break;
|
|
case DRM_FORMAT_YUYV:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
|
|
break;
|
|
case DRM_FORMAT_YVYU:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
|
|
break;
|
|
case DRM_FORMAT_UYVY:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
|
|
break;
|
|
case DRM_FORMAT_VYUY:
|
|
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
/*
|
|
* Enable gamma to match primary/cursor plane behaviour.
|
|
* FIXME should be user controllable via propertiesa.
|
|
*/
|
|
dvscntr |= DVS_GAMMA_ENABLE;
|
|
|
|
if (obj->tiling_mode != I915_TILING_NONE)
|
|
dvscntr |= DVS_TILED;
|
|
|
|
if (IS_GEN6(dev))
|
|
dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
|
|
dvscntr |= DVS_ENABLE;
|
|
|
|
intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
|
|
pixel_size, true,
|
|
src_w != crtc_w || src_h != crtc_h);
|
|
|
|
/* Sizes are 0 based */
|
|
src_w--;
|
|
src_h--;
|
|
crtc_w--;
|
|
crtc_h--;
|
|
|
|
dvsscale = 0;
|
|
if (crtc_w != src_w || crtc_h != src_h)
|
|
dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
|
|
|
|
linear_offset = y * fb->pitches[0] + x * pixel_size;
|
|
dvssurf_offset =
|
|
intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
|
|
pixel_size, fb->pitches[0]);
|
|
linear_offset -= dvssurf_offset;
|
|
|
|
atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
|
|
|
|
intel_update_primary_plane(intel_crtc);
|
|
|
|
I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
|
|
I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
|
|
|
|
if (obj->tiling_mode != I915_TILING_NONE)
|
|
I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
|
|
else
|
|
I915_WRITE(DVSLINOFF(pipe), linear_offset);
|
|
|
|
I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
|
|
I915_WRITE(DVSSCALE(pipe), dvsscale);
|
|
I915_WRITE(DVSCNTR(pipe), dvscntr);
|
|
I915_WRITE(DVSSURF(pipe),
|
|
i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
|
|
|
|
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
|
|
|
|
if (atomic_update)
|
|
intel_pipe_update_end(intel_crtc, start_vbl_count);
|
|
}
|
|
|
|
static void
|
|
ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
int pipe = intel_plane->pipe;
|
|
u32 start_vbl_count;
|
|
bool atomic_update;
|
|
|
|
atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
|
|
|
|
intel_update_primary_plane(intel_crtc);
|
|
|
|
I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
|
|
/* Disable the scaler */
|
|
I915_WRITE(DVSSCALE(pipe), 0);
|
|
/* Flush double buffered register updates */
|
|
I915_WRITE(DVSSURF(pipe), 0);
|
|
|
|
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
|
|
|
|
if (atomic_update)
|
|
intel_pipe_update_end(intel_crtc, start_vbl_count);
|
|
|
|
/*
|
|
* Avoid underruns when disabling the sprite.
|
|
* FIXME remove once watermark updates are done properly.
|
|
*/
|
|
intel_wait_for_vblank(dev, pipe);
|
|
|
|
intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
|
|
}
|
|
|
|
static void
|
|
intel_post_enable_primary(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
/*
|
|
* FIXME IPS should be fine as long as one plane is
|
|
* enabled, but in practice it seems to have problems
|
|
* when going from primary only to sprite only and vice
|
|
* versa.
|
|
*/
|
|
hsw_enable_ips(intel_crtc);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
intel_update_fbc(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
}
|
|
|
|
static void
|
|
intel_pre_disable_primary(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
if (dev_priv->fbc.plane == intel_crtc->plane)
|
|
intel_disable_fbc(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
/*
|
|
* FIXME IPS should be fine as long as one plane is
|
|
* enabled, but in practice it seems to have problems
|
|
* when going from primary only to sprite only and vice
|
|
* versa.
|
|
*/
|
|
hsw_disable_ips(intel_crtc);
|
|
}
|
|
|
|
static int
|
|
ilk_update_colorkey(struct drm_plane *plane,
|
|
struct drm_intel_sprite_colorkey *key)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane;
|
|
u32 dvscntr;
|
|
int ret = 0;
|
|
|
|
intel_plane = to_intel_plane(plane);
|
|
|
|
I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
|
|
I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
|
|
I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
|
|
|
|
dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
|
|
dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
|
|
if (key->flags & I915_SET_COLORKEY_DESTINATION)
|
|
dvscntr |= DVS_DEST_KEY;
|
|
else if (key->flags & I915_SET_COLORKEY_SOURCE)
|
|
dvscntr |= DVS_SOURCE_KEY;
|
|
I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
|
|
|
|
POSTING_READ(DVSKEYMSK(intel_plane->pipe));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_plane *intel_plane;
|
|
u32 dvscntr;
|
|
|
|
intel_plane = to_intel_plane(plane);
|
|
|
|
key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
|
|
key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
|
|
key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
|
|
key->flags = 0;
|
|
|
|
dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
|
|
|
|
if (dvscntr & DVS_DEST_KEY)
|
|
key->flags = I915_SET_COLORKEY_DESTINATION;
|
|
else if (dvscntr & DVS_SOURCE_KEY)
|
|
key->flags = I915_SET_COLORKEY_SOURCE;
|
|
else
|
|
key->flags = I915_SET_COLORKEY_NONE;
|
|
}
|
|
|
|
static bool
|
|
format_is_yuv(uint32_t format)
|
|
{
|
|
switch (format) {
|
|
case DRM_FORMAT_YUYV:
|
|
case DRM_FORMAT_UYVY:
|
|
case DRM_FORMAT_VYUY:
|
|
case DRM_FORMAT_YVYU:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool colorkey_enabled(struct intel_plane *intel_plane)
|
|
{
|
|
struct drm_intel_sprite_colorkey key;
|
|
|
|
intel_plane->get_colorkey(&intel_plane->base, &key);
|
|
|
|
return key.flags != I915_SET_COLORKEY_NONE;
|
|
}
|
|
|
|
static int
|
|
intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb, int crtc_x, int crtc_y,
|
|
unsigned int crtc_w, unsigned int crtc_h,
|
|
uint32_t src_x, uint32_t src_y,
|
|
uint32_t src_w, uint32_t src_h)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
|
|
struct drm_i915_gem_object *obj = intel_fb->obj;
|
|
struct drm_i915_gem_object *old_obj = intel_plane->obj;
|
|
int ret;
|
|
bool primary_enabled;
|
|
bool visible;
|
|
int hscale, vscale;
|
|
int max_scale, min_scale;
|
|
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
|
|
struct drm_rect src = {
|
|
/* sample coordinates in 16.16 fixed point */
|
|
.x1 = src_x,
|
|
.x2 = src_x + src_w,
|
|
.y1 = src_y,
|
|
.y2 = src_y + src_h,
|
|
};
|
|
struct drm_rect dst = {
|
|
/* integer pixels */
|
|
.x1 = crtc_x,
|
|
.x2 = crtc_x + crtc_w,
|
|
.y1 = crtc_y,
|
|
.y2 = crtc_y + crtc_h,
|
|
};
|
|
const struct drm_rect clip = {
|
|
.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
|
|
.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
|
|
};
|
|
const struct {
|
|
int crtc_x, crtc_y;
|
|
unsigned int crtc_w, crtc_h;
|
|
uint32_t src_x, src_y, src_w, src_h;
|
|
} orig = {
|
|
.crtc_x = crtc_x,
|
|
.crtc_y = crtc_y,
|
|
.crtc_w = crtc_w,
|
|
.crtc_h = crtc_h,
|
|
.src_x = src_x,
|
|
.src_y = src_y,
|
|
.src_w = src_w,
|
|
.src_h = src_h,
|
|
};
|
|
|
|
/* Don't modify another pipe's plane */
|
|
if (intel_plane->pipe != intel_crtc->pipe) {
|
|
DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* FIXME check all gen limits */
|
|
if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
|
|
DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Sprite planes can be linear or x-tiled surfaces */
|
|
switch (obj->tiling_mode) {
|
|
case I915_TILING_NONE:
|
|
case I915_TILING_X:
|
|
break;
|
|
default:
|
|
DRM_DEBUG_KMS("Unsupported tiling mode\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* FIXME the following code does a bunch of fuzzy adjustments to the
|
|
* coordinates and sizes. We probably need some way to decide whether
|
|
* more strict checking should be done instead.
|
|
*/
|
|
max_scale = intel_plane->max_downscale << 16;
|
|
min_scale = intel_plane->can_scale ? 1 : (1 << 16);
|
|
|
|
hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
|
|
BUG_ON(hscale < 0);
|
|
|
|
vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
|
|
BUG_ON(vscale < 0);
|
|
|
|
visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
|
|
|
|
crtc_x = dst.x1;
|
|
crtc_y = dst.y1;
|
|
crtc_w = drm_rect_width(&dst);
|
|
crtc_h = drm_rect_height(&dst);
|
|
|
|
if (visible) {
|
|
/* check again in case clipping clamped the results */
|
|
hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
|
|
if (hscale < 0) {
|
|
DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
|
|
drm_rect_debug_print(&src, true);
|
|
drm_rect_debug_print(&dst, false);
|
|
|
|
return hscale;
|
|
}
|
|
|
|
vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
|
|
if (vscale < 0) {
|
|
DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
|
|
drm_rect_debug_print(&src, true);
|
|
drm_rect_debug_print(&dst, false);
|
|
|
|
return vscale;
|
|
}
|
|
|
|
/* Make the source viewport size an exact multiple of the scaling factors. */
|
|
drm_rect_adjust_size(&src,
|
|
drm_rect_width(&dst) * hscale - drm_rect_width(&src),
|
|
drm_rect_height(&dst) * vscale - drm_rect_height(&src));
|
|
|
|
/* sanity check to make sure the src viewport wasn't enlarged */
|
|
WARN_ON(src.x1 < (int) src_x ||
|
|
src.y1 < (int) src_y ||
|
|
src.x2 > (int) (src_x + src_w) ||
|
|
src.y2 > (int) (src_y + src_h));
|
|
|
|
/*
|
|
* Hardware doesn't handle subpixel coordinates.
|
|
* Adjust to (macro)pixel boundary, but be careful not to
|
|
* increase the source viewport size, because that could
|
|
* push the downscaling factor out of bounds.
|
|
*/
|
|
src_x = src.x1 >> 16;
|
|
src_w = drm_rect_width(&src) >> 16;
|
|
src_y = src.y1 >> 16;
|
|
src_h = drm_rect_height(&src) >> 16;
|
|
|
|
if (format_is_yuv(fb->pixel_format)) {
|
|
src_x &= ~1;
|
|
src_w &= ~1;
|
|
|
|
/*
|
|
* Must keep src and dst the
|
|
* same if we can't scale.
|
|
*/
|
|
if (!intel_plane->can_scale)
|
|
crtc_w &= ~1;
|
|
|
|
if (crtc_w == 0)
|
|
visible = false;
|
|
}
|
|
}
|
|
|
|
/* Check size restrictions when scaling */
|
|
if (visible && (src_w != crtc_w || src_h != crtc_h)) {
|
|
unsigned int width_bytes;
|
|
|
|
WARN_ON(!intel_plane->can_scale);
|
|
|
|
/* FIXME interlacing min height is 6 */
|
|
|
|
if (crtc_w < 3 || crtc_h < 3)
|
|
visible = false;
|
|
|
|
if (src_w < 3 || src_h < 3)
|
|
visible = false;
|
|
|
|
width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
|
|
|
|
if (src_w > 2048 || src_h > 2048 ||
|
|
width_bytes > 4096 || fb->pitches[0] > 4096) {
|
|
DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
dst.x1 = crtc_x;
|
|
dst.x2 = crtc_x + crtc_w;
|
|
dst.y1 = crtc_y;
|
|
dst.y2 = crtc_y + crtc_h;
|
|
|
|
/*
|
|
* If the sprite is completely covering the primary plane,
|
|
* we can disable the primary and save power.
|
|
*/
|
|
primary_enabled = !drm_rect_equals(&dst, &clip) || colorkey_enabled(intel_plane);
|
|
WARN_ON(!primary_enabled && !visible && intel_crtc->active);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
|
|
/* Note that this will apply the VT-d workaround for scanouts,
|
|
* which is more restrictive than required for sprites. (The
|
|
* primary plane requires 256KiB alignment with 64 PTE padding,
|
|
* the sprite planes only require 128KiB alignment and 32 PTE padding.
|
|
*/
|
|
ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
|
|
|
|
i915_gem_track_fb(old_obj, obj,
|
|
INTEL_FRONTBUFFER_SPRITE(pipe));
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_plane->crtc_x = orig.crtc_x;
|
|
intel_plane->crtc_y = orig.crtc_y;
|
|
intel_plane->crtc_w = orig.crtc_w;
|
|
intel_plane->crtc_h = orig.crtc_h;
|
|
intel_plane->src_x = orig.src_x;
|
|
intel_plane->src_y = orig.src_y;
|
|
intel_plane->src_w = orig.src_w;
|
|
intel_plane->src_h = orig.src_h;
|
|
intel_plane->obj = obj;
|
|
|
|
if (intel_crtc->active) {
|
|
bool primary_was_enabled = intel_crtc->primary_enabled;
|
|
|
|
intel_crtc->primary_enabled = primary_enabled;
|
|
|
|
// if (primary_was_enabled != primary_enabled)
|
|
|
|
if (primary_was_enabled && !primary_enabled)
|
|
intel_pre_disable_primary(crtc);
|
|
|
|
if (visible)
|
|
intel_plane->update_plane(plane, crtc, fb, obj,
|
|
crtc_x, crtc_y, crtc_w, crtc_h,
|
|
src_x, src_y, src_w, src_h);
|
|
else
|
|
intel_plane->disable_plane(plane, crtc);
|
|
|
|
if (!primary_was_enabled && primary_enabled)
|
|
intel_post_enable_primary(crtc);
|
|
}
|
|
|
|
/* Unpin old obj after new one is active to avoid ugliness */
|
|
if (old_obj) {
|
|
/*
|
|
* It's fairly common to simply update the position of
|
|
* an existing object. In that case, we don't need to
|
|
* wait for vblank to avoid ugliness, we only need to
|
|
* do the pin & ref bookkeeping.
|
|
*/
|
|
if (old_obj != obj && intel_crtc->active)
|
|
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
intel_unpin_fb_obj(old_obj);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
intel_disable_plane(struct drm_plane *plane)
|
|
{
|
|
struct drm_device *dev = plane->dev;
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
struct intel_crtc *intel_crtc;
|
|
enum pipe pipe;
|
|
|
|
if (!plane->fb)
|
|
return 0;
|
|
|
|
if (WARN_ON(!plane->crtc))
|
|
return -EINVAL;
|
|
|
|
intel_crtc = to_intel_crtc(plane->crtc);
|
|
pipe = intel_crtc->pipe;
|
|
|
|
if (intel_crtc->active) {
|
|
bool primary_was_enabled = intel_crtc->primary_enabled;
|
|
|
|
intel_crtc->primary_enabled = true;
|
|
|
|
intel_plane->disable_plane(plane, plane->crtc);
|
|
|
|
if (!primary_was_enabled && intel_crtc->primary_enabled)
|
|
intel_post_enable_primary(plane->crtc);
|
|
}
|
|
|
|
if (intel_plane->obj) {
|
|
if (intel_crtc->active)
|
|
intel_wait_for_vblank(dev, intel_plane->pipe);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
intel_unpin_fb_obj(intel_plane->obj);
|
|
i915_gem_track_fb(intel_plane->obj, NULL,
|
|
INTEL_FRONTBUFFER_SPRITE(pipe));
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
intel_plane->obj = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_destroy_plane(struct drm_plane *plane)
|
|
{
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
intel_disable_plane(plane);
|
|
drm_plane_cleanup(plane);
|
|
kfree(intel_plane);
|
|
}
|
|
|
|
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct drm_intel_sprite_colorkey *set = data;
|
|
struct drm_plane *plane;
|
|
struct intel_plane *intel_plane;
|
|
int ret = 0;
|
|
|
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
|
return -ENODEV;
|
|
|
|
/* Make sure we don't try to enable both src & dest simultaneously */
|
|
if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
|
|
return -EINVAL;
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
plane = drm_plane_find(dev, set->plane_id);
|
|
if (!plane) {
|
|
ret = -ENOENT;
|
|
goto out_unlock;
|
|
}
|
|
|
|
intel_plane = to_intel_plane(plane);
|
|
ret = intel_plane->update_colorkey(plane, set);
|
|
|
|
out_unlock:
|
|
drm_modeset_unlock_all(dev);
|
|
return ret;
|
|
}
|
|
|
|
int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct drm_intel_sprite_colorkey *get = data;
|
|
struct drm_plane *plane;
|
|
struct intel_plane *intel_plane;
|
|
int ret = 0;
|
|
|
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
|
return -ENODEV;
|
|
|
|
drm_modeset_lock_all(dev);
|
|
|
|
plane = drm_plane_find(dev, get->plane_id);
|
|
if (!plane) {
|
|
ret = -ENOENT;
|
|
goto out_unlock;
|
|
}
|
|
|
|
intel_plane = to_intel_plane(plane);
|
|
intel_plane->get_colorkey(plane, get);
|
|
|
|
out_unlock:
|
|
drm_modeset_unlock_all(dev);
|
|
return ret;
|
|
}
|
|
|
|
void intel_plane_restore(struct drm_plane *plane)
|
|
{
|
|
struct intel_plane *intel_plane = to_intel_plane(plane);
|
|
|
|
if (!plane->crtc || !plane->fb)
|
|
return;
|
|
|
|
intel_update_plane(plane, plane->crtc, plane->fb,
|
|
intel_plane->crtc_x, intel_plane->crtc_y,
|
|
intel_plane->crtc_w, intel_plane->crtc_h,
|
|
intel_plane->src_x, intel_plane->src_y,
|
|
intel_plane->src_w, intel_plane->src_h);
|
|
}
|
|
|
|
void intel_plane_disable(struct drm_plane *plane)
|
|
{
|
|
if (!plane->crtc || !plane->fb)
|
|
return;
|
|
|
|
intel_disable_plane(plane);
|
|
}
|
|
|
|
static const struct drm_plane_funcs intel_plane_funcs = {
|
|
.update_plane = intel_update_plane,
|
|
.disable_plane = intel_disable_plane,
|
|
.destroy = intel_destroy_plane,
|
|
};
|
|
|
|
static uint32_t ilk_plane_formats[] = {
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
static uint32_t snb_plane_formats[] = {
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
static uint32_t vlv_plane_formats[] = {
|
|
DRM_FORMAT_RGB565,
|
|
DRM_FORMAT_ABGR8888,
|
|
DRM_FORMAT_ARGB8888,
|
|
DRM_FORMAT_XBGR8888,
|
|
DRM_FORMAT_XRGB8888,
|
|
DRM_FORMAT_XBGR2101010,
|
|
DRM_FORMAT_ABGR2101010,
|
|
DRM_FORMAT_YUYV,
|
|
DRM_FORMAT_YVYU,
|
|
DRM_FORMAT_UYVY,
|
|
DRM_FORMAT_VYUY,
|
|
};
|
|
|
|
int
|
|
intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
|
|
{
|
|
struct intel_plane *intel_plane;
|
|
unsigned long possible_crtcs;
|
|
const uint32_t *plane_formats;
|
|
int num_plane_formats;
|
|
int ret;
|
|
|
|
if (INTEL_INFO(dev)->gen < 5)
|
|
return -ENODEV;
|
|
|
|
intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
|
|
if (!intel_plane)
|
|
return -ENOMEM;
|
|
|
|
switch (INTEL_INFO(dev)->gen) {
|
|
case 5:
|
|
case 6:
|
|
intel_plane->can_scale = true;
|
|
intel_plane->max_downscale = 16;
|
|
intel_plane->update_plane = ilk_update_plane;
|
|
intel_plane->disable_plane = ilk_disable_plane;
|
|
intel_plane->update_colorkey = ilk_update_colorkey;
|
|
intel_plane->get_colorkey = ilk_get_colorkey;
|
|
|
|
if (IS_GEN6(dev)) {
|
|
plane_formats = snb_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
|
} else {
|
|
plane_formats = ilk_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
|
|
}
|
|
break;
|
|
|
|
case 7:
|
|
case 8:
|
|
if (IS_IVYBRIDGE(dev)) {
|
|
intel_plane->can_scale = true;
|
|
intel_plane->max_downscale = 2;
|
|
} else {
|
|
intel_plane->can_scale = false;
|
|
intel_plane->max_downscale = 1;
|
|
}
|
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
intel_plane->update_plane = vlv_update_plane;
|
|
intel_plane->disable_plane = vlv_disable_plane;
|
|
intel_plane->update_colorkey = vlv_update_colorkey;
|
|
intel_plane->get_colorkey = vlv_get_colorkey;
|
|
|
|
plane_formats = vlv_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
|
|
} else {
|
|
intel_plane->update_plane = ivb_update_plane;
|
|
intel_plane->disable_plane = ivb_disable_plane;
|
|
intel_plane->update_colorkey = ivb_update_colorkey;
|
|
intel_plane->get_colorkey = ivb_get_colorkey;
|
|
|
|
plane_formats = snb_plane_formats;
|
|
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
kfree(intel_plane);
|
|
return -ENODEV;
|
|
}
|
|
|
|
intel_plane->pipe = pipe;
|
|
intel_plane->plane = plane;
|
|
possible_crtcs = (1 << pipe);
|
|
ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
|
|
&intel_plane_funcs,
|
|
plane_formats, num_plane_formats,
|
|
false);
|
|
if (ret)
|
|
kfree(intel_plane);
|
|
|
|
return ret;
|
|
}
|