forked from KolibriOS/kolibrios
625 lines
24 KiB
PHP
625 lines
24 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; RTL8139.INC ;;
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;; ;;
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;; Ethernet driver for Menuet OS ;;
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;; ;;
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;; Version 0.2 11 August 2003 ;;
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;; ;;
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;; Driver for chips of RealTek 8139 family ;;
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;; References: ;;
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;; www.realtek.com.hw - data sheets ;;
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;; rtl8139.c - linux driver ;;
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;; 8139too.c - linux driver ;;
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;; ethernet driver template by Mike Hibbett ;;
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;; ;;
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;; The copyright statement is ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;; Copyright 2003 Endre Kozma, ;;
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;; endre.kozma@axelero.hu ;;
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;; ;;
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;; See file COPYING for details ;;
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;; ;;
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;; 10.01.2007 Bugfix for l8139_transmit from Paolo Franchetti ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision$
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ETH_ALEN equ 6
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ETH_HLEN equ (2 * ETH_ALEN + 2)
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ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
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; mininmum 64bytes frame length
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PCI_REG_COMMAND equ 0x04 ; command register
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PCI_BIT_PIO equ 0 ; bit0: io space control
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PCI_BIT_MMIO equ 1 ; bit1: memory space control
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PCI_BIT_MASTER equ 2 ; bit2: device acts as a PCI master
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RTL8139_REG_MAR0 equ 0x08 ; multicast filter register 0
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RTL8139_REG_MAR4 equ 0x0c ; multicast filter register 4
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RTL8139_REG_TSD0 equ 0x10 ; transmit status of descriptor
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RTL8139_REG_TSAD0 equ 0x20 ; transmit start address of descriptor
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RTL8139_REG_RBSTART equ 0x30 ; RxBuffer start address
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RTL8139_REG_COMMAND equ 0x37 ; command register
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RTL8139_REG_CAPR equ 0x38 ; current address of packet read
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RTL8139_REG_IMR equ 0x3c ; interrupt mask register
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RTL8139_REG_ISR equ 0x3e ; interrupt status register
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RTL8139_REG_TXCONFIG equ 0x40 ; transmit configuration register
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RTL8139_REG_TXCONFIG_0 equ 0x40 ; transmit configuration register 0
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RTL8139_REG_TXCONFIG_1 equ 0x41 ; transmit configuration register 1
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RTL8139_REG_TXCONFIG_2 equ 0x42 ; transmit configuration register 2
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RTL8139_REG_TXCONFIG_3 equ 0x43 ; transmit configuration register 3
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RTL8139_REG_RXCONFIG equ 0x44 ; receive configuration register 0
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RTL8139_REG_RXCONFIG_0 equ 0x44 ; receive configuration register 0
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RTL8139_REG_RXCONFIG_1 equ 0x45 ; receive configuration register 1
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RTL8139_REG_RXCONFIG_2 equ 0x46 ; receive configuration register 2
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RTL8139_REG_RXCONFIG_3 equ 0x47 ; receive configuration register 3
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RTL8139_REG_MPC equ 0x4c ; missed packet counter
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RTL8139_REG_9346CR equ 0x50 ; serial eeprom 93C46 command register
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RTL8139_REG_CONFIG1 equ 0x52 ; configuration register 1
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RTL8139_REG_CONFIG4 equ 0x5a ; configuration register 4
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RTL8139_REG_HLTCLK equ 0x5b ; undocumented halt clock register
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RTL8139_REG_BMCR equ 0x62 ; basic mode control register
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RTL8139_REG_ANAR equ 0x66 ; auto negotiation advertisement register
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; 5.1 packet header
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RTL8139_BIT_RUNT equ 4 ; total packet length < 64 bytes
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RTL8139_BIT_LONG equ 3 ; total packet length > 4k
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RTL8139_BIT_CRC equ 2 ; crc error occured
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RTL8139_BIT_FAE equ 1 ; frame alignment error occured
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RTL8139_BIT_ROK equ 0 ; received packet is ok
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; 5.4 command register
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RTL8139_BIT_RST equ 4 ; reset bit
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RTL8139_BIT_RE equ 3 ; receiver enabled
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RTL8139_BIT_TE equ 2 ; transmitter enabled
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RTL8139_BIT_BUFE equ 0 ; rx buffer is empty, no packet stored
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; 5.6 interrupt status register
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RTL8139_BIT_ISR_TOK equ 2 ; transmit ok
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RTL8139_BIT_ISR_RER equ 1 ; receive error interrupt
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RTL8139_BIT_ISR_ROK equ 0 ; receive ok
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; 5.7 transmit configyration register
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RTL8139_BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst
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RTL8139_BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16)
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; 5.8 receive configuration register
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RTL8139_BIT_RXFTH equ 13 ; Rx fifo threshold
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RTL8139_BIT_RBLEN equ 11 ; Ring buffer length indicator
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RTL8139_BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst
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RTL8139_BIT_NOWRAP equ 7 ; transfered data wrapping
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RTL8139_BIT_9356SEL equ 6 ; eeprom selector 9346/9356
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RTL8139_BIT_AER equ 5 ; accept error packets
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RTL8139_BIT_AR equ 4 ; accept runt packets
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RTL8139_BIT_AB equ 3 ; accept broadcast packets
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RTL8139_BIT_AM equ 2 ; accept multicast packets
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RTL8139_BIT_APM equ 1 ; accept physical match packets
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RTL8139_BIT_AAP equ 0 ; accept all packets
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; 5.9 93C46/93C56 command register
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RTL8139_BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1
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RTL8139_BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0
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RTL8139_BIT_93C46_EECS equ 3 ; chip select
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RTL8139_BIT_93C46_EESK equ 2 ; serial data clock
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RTL8139_BIT_93C46_EEDI equ 1 ; serial data input
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RTL8139_BIT_93C46_EEDO equ 0 ; serial data output
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; 5.11 configuration register 1
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RTL8139_BIT_LWACT equ 4 ; see RTL8139_REG_CONFIG1
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RTL8139_BIT_SLEEP equ 1 ; sleep bit at older chips
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RTL8139_BIT_PWRDWN equ 0 ; power down bit at older chips
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RTL8139_BIT_PMEn equ 0 ; power management enabled
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; 5.14 configuration register 4
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RTL8139_BIT_LWPTN equ 2 ; see RTL8139_REG_CONFIG4
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; 6.2 transmit status register
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RTL8139_BIT_ERTXTH equ 16 ; early TX threshold
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RTL8139_BIT_TOK equ 15 ; transmit ok
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RTL8139_BIT_OWN equ 13 ; tx DMA operation is completed
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; 6.18 basic mode control register
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RTL8139_BIT_ANE equ 12 ; auto negotiation enable
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; 6.20 auto negotiation advertisement register
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RTL8139_BIT_TXFD equ 8 ; 100base-T full duplex
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RTL8139_BIT_TX equ 7 ; 100base-T
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RTL8139_BIT_10FD equ 6 ; 10base-T full duplex
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RTL8139_BIT_10 equ 5 ; 10base-T
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RTL8139_BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001
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; RX/TX buffer size
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RTL8139_RBLEN equ 0 ; 0==8K 1==16k 2==32k 3==64k
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RTL8139_RX_BUFFER_SIZE equ (8192 shl RTL8139_RBLEN)
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MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC
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RTL8139_NUM_TX_DESC equ 4
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RTL8139_TX_BUFFER_SIZE equ (MAX_ETH_FRAME_SIZE * RTL8139_NUM_TX_DESC)
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RTL8139_TXRR equ 8 ; total retries = 16+(TXRR*16)
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RTL8139_TX_MXDMA equ 6 ; 0==16 1==32 2==64 3==128
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; 4==256 5==512 6==1024 7==2048
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RTL8139_ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256
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RTL8139_RX_MXDMA equ 7 ; 0==16 1==32 2==64 3==128
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; 4==256 5==512 6==1024 7==unlimited
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RTL8139_RXFTH equ 7 ; 0==16 1==32 2==64 3==128
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; 4==256 5==512 6==1024 7==no threshold
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RTL8139_RX_CONFIG equ ((RTL8139_RBLEN shl RTL8139_BIT_RBLEN) \
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or (RTL8139_RX_MXDMA shl RTL8139_BIT_RX_MXDMA) \
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or (1 shl RTL8139_BIT_NOWRAP) \
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or (RTL8139_RXFTH shl RTL8139_BIT_RXFTH) \
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or (1 shl RTL8139_BIT_AB) or (1 shl RTL8139_BIT_APM) \
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or (1 shl RTL8139_BIT_AER) or (1 shl RTL8139_BIT_AR) \
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or (1 shl RTL8139_BIT_AM))
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RTL8139_TX_TIMEOUT equ 30 ; 300 milliseconds timeout
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EE_93C46_REG_ETH_ID equ 7 ; MAC offset
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EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address
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EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address
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EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address
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EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress
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VER_RTL8139 equ 1100000b
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VER_RTL8139A equ 1110000b
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; VER_RTL8139AG equ 1110100b
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VER_RTL8139B equ 1111000b
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VER_RTL8130 equ VER_RTL8139B
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VER_RTL8139C equ 1110100b
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VER_RTL8100 equ 1111010b
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VER_RTL8100B equ 1110101b
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VER_RTL8139D equ VER_RTL8100B
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VER_RTL8139CP equ 1110110b
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VER_RTL8101 equ 1110111b
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IDX_RTL8139 equ 0
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IDX_RTL8139A equ 1
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IDX_RTL8139B equ 2
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IDX_RTL8139C equ 3
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IDX_RTL8100 equ 4
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IDX_RTL8139D equ 5
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IDX_RTL8139D equ 6
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IDX_RTL8101 equ 7
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; These two must be 4 byte aligned ( which they are )
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rtl8139_rx_buff equ eth_data_start
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rtl8139_tx_buff equ rtl8139_rx_buff + (RTL8139_RX_BUFFER_SIZE + MAX_ETH_FRAME_SIZE)
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uglobal
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align 4
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rtl8139_rx_buff_offset:
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dd 0
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curr_tx_desc dd 0
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endg
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iglobal
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hw_ver_array:
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db VER_RTL8139, VER_RTL8139A, VER_RTL8139B, VER_RTL8139C
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db VER_RTL8100, VER_RTL8139D, VER_RTL8139CP, VER_RTL8101
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HW_VER_ARRAY_SIZE = $-hw_ver_array
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endg
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uglobal
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hw_ver_id:
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db 0
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endg
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;***************************************************************************
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; Function
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; rtl8139_probe
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; Description
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; Searches for an ethernet card, enables it and clears the rx buffer
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; If a card was found, it enables the ethernet -> TCPIP link
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; Destroyed registers
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; eax, ebx, ecx, edx
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;
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;***************************************************************************
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rtl8139_probe:
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; enable the device
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mov al, 2
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mov ah, [pci_bus]
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mov bh, [pci_dev]
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mov bl, PCI_REG_COMMAND
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call pci_read_reg
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mov cx, ax
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or cl, (1 shl PCI_BIT_MASTER) or (1 shl PCI_BIT_PIO)
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and cl, not (1 shl PCI_BIT_MMIO)
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mov al, 2
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mov ah, [pci_bus]
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mov bh, [pci_dev]
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mov bl, PCI_REG_COMMAND
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call pci_write_reg
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; get chip version
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mov edx, [io_addr]
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add edx, RTL8139_REG_TXCONFIG_2
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in ax, dx
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shr ah, 2
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shr ax, 6
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and al, 01111111b
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mov ecx, HW_VER_ARRAY_SIZE-1
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.chip_ver_loop:
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cmp al, [hw_ver_array+ecx]
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je .chip_ver_found
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dec ecx
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jns .chip_ver_loop
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xor cl, cl ; default RTL8139
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.chip_ver_found:
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mov [hw_ver_id], cl
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; wake up the chip
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mov edx, [io_addr]
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add edx, RTL8139_REG_HLTCLK
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mov al, 'R' ; run the clock
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out dx, al
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; unlock config and BMCR registers
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add edx, RTL8139_REG_9346CR - RTL8139_REG_HLTCLK
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mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
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out dx, al
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; enable power management
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add edx, RTL8139_REG_CONFIG1 - RTL8139_REG_9346CR
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in al, dx
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cmp byte [hw_ver_id], IDX_RTL8139B
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jl .old_chip
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; set LWAKE pin to active high (default value).
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; it is for Wake-On-LAN functionality of some motherboards.
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; this signal is used to inform the motherboard to execute a wake-up process.
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; only at newer chips.
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or al, (1 shl RTL8139_BIT_PMEn)
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and al, not (1 shl RTL8139_BIT_LWACT)
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out dx, al
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add edx, RTL8139_REG_CONFIG4 - RTL8139_REG_CONFIG1
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in al, dx
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and al, not (1 shl RTL8139_BIT_LWPTN)
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out dx, al
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jmp .finish_wake_up
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.old_chip:
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; wake up older chips
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and al, not ((1 shl RTL8139_BIT_SLEEP) or (1 shl RTL8139_BIT_PWRDWN))
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out dx, al
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.finish_wake_up:
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; lock config and BMCR registers
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xor al, al
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mov edx, [io_addr]
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add edx, RTL8139_REG_9346CR
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out dx, al
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;***************************************************************************
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; Function
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; rt8139_reset
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; Description
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; Place the chip (ie, the ethernet card) into a virgin state
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; Destroyed registers
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; eax, ebx, ecx, edx
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;
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;***************************************************************************
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rtl8139_reset:
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mov edx, [io_addr]
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add edx, RTL8139_REG_COMMAND
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mov al, 1 shl RTL8139_BIT_RST
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out dx, al
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mov cx, 1000 ; wait no longer for the reset
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.wait_for_reset:
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in al, dx
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test al, 1 shl RTL8139_BIT_RST
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jz .reset_completed ; RST remains 1 during reset
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dec cx
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jns .wait_for_reset
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.reset_completed:
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; get MAC (hardware address)
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mov ecx, 2
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.mac_read_loop:
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lea eax, [EE_93C46_REG_ETH_ID+ecx]
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push ecx
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call rtl8139_read_eeprom
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pop ecx
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mov [node_addr+ecx*2], ax
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dec ecx
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jns .mac_read_loop
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; unlock config and BMCR registers
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mov edx, [io_addr]
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add edx, RTL8139_REG_9346CR
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mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EEM0)
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out dx, al
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; initialize multicast registers (no filtering)
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mov eax, 0xffffffff
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add edx, RTL8139_REG_MAR0 - RTL8139_REG_9346CR
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out dx, eax
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add edx, RTL8139_REG_MAR4 - RTL8139_REG_MAR0
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out dx, eax
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; enable Rx/Tx
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mov al, (1 shl RTL8139_BIT_RE) or (1 shl RTL8139_BIT_TE)
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add edx, RTL8139_REG_COMMAND - RTL8139_REG_MAR4
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out dx, al
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; 32k Rxbuffer, unlimited dma burst, no wrapping, no rx threshold
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; accept broadcast packets, accept physical match packets
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mov eax, RTL8139_RX_CONFIG
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add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
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out dx, eax
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; 1024 bytes DMA burst, total retries = 16 + 8 * 16 = 144
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mov eax, (RTL8139_TX_MXDMA shl RTL8139_BIT_TX_MXDMA) \
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or (RTL8139_TXRR shl RTL8139_BIT_TXRR)
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add edx, RTL8139_REG_TXCONFIG - RTL8139_REG_RXCONFIG
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out dx, eax
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; enable auto negotiation
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add edx, RTL8139_REG_BMCR - RTL8139_REG_TXCONFIG
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in ax, dx
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or ax, (1 shl RTL8139_BIT_ANE)
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out dx, ax
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; set auto negotiation advertisement
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add edx, RTL8139_REG_ANAR - RTL8139_REG_BMCR
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in ax, dx
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or ax, (1 shl RTL8139_BIT_SELECTOR) or (1 shl RTL8139_BIT_10) \
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or (1 shl RTL8139_BIT_10FD) or (1 shl RTL8139_BIT_TX) \
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or (1 shl RTL8139_BIT_TXFD)
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out dx, ax
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; lock config and BMCR registers
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xor eax, eax
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add edx, RTL8139_REG_9346CR - RTL8139_REG_ANAR
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out dx, al
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; init RX/TX pointers
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mov [rtl8139_rx_buff_offset], eax
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mov [curr_tx_desc], eax
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; clear missing packet counter
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add edx, RTL8139_REG_MPC - RTL8139_REG_9346CR
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out dx, eax
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; disable all interrupts
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add edx, RTL8139_REG_IMR - RTL8139_REG_MPC
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out dx, ax
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; set RxBuffer address, init RX buffer offset, init TX ring
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mov eax, rtl8139_rx_buff ; simba
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sub eax, OS_BASE
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add edx, RTL8139_REG_RBSTART - RTL8139_REG_IMR
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out dx, eax
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; Indicate that we have successfully reset the card
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mov eax, [pci_data]
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mov [eth_status], eax
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ret
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;***************************************************************************
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; Function
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; rtl8139_read_eeprom
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; Description
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; reads eeprom type 93c46 and 93c56
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; Parameters
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; al - word to be read (6bit in case of 93c46 and 8bit otherwise)
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; Return value
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; ax - word read in
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; Destroyed register(s)
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; eax, cx, ebx, edx
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;
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;***************************************************************************
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rtl8139_read_eeprom:
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movzx ebx, al
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mov edx, [io_addr]
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add edx, RTL8139_REG_RXCONFIG
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in al, dx
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test al, (1 shl RTL8139_BIT_9356SEL)
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jz .type_93c46
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; and bl, 01111111b ; don't care first bit
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or bx, EE_93C56_READ_CMD ; it contains start bit
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mov cx, EE_93C56_CMD_LENGTH-1 ; cmd_loop counter
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jmp .read_eeprom
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.type_93c46:
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and bl, 00111111b
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or bx, EE_93C46_READ_CMD ; it contains start bit
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mov cx, EE_93C46_CMD_LENGTH-1 ; cmd_loop counter
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.read_eeprom:
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add edx, RTL8139_REG_9346CR - RTL8139_REG_RXCONFIG_0
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; mov al, (1 shl RTL8139_BIT_93C46_EEM1)
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; out dx, al
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mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
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or (1 shl RTL8139_BIT_93C46_EECS) ; wake up the eeprom
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out dx, al
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.cmd_loop:
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mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
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bt bx, cx
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jnc .zero_bit
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or al, (1 shl RTL8139_BIT_93C46_EEDI)
|
|
.zero_bit:
|
|
out dx, al
|
|
; push eax
|
|
; in eax, dx ; eeprom delay
|
|
; pop eax
|
|
or al, (1 shl RTL8139_BIT_93C46_EESK)
|
|
out dx, al
|
|
; in eax, dx ; eeprom delay
|
|
dec cx
|
|
jns .cmd_loop
|
|
; in eax, dx ; eeprom delay
|
|
mov al, (1 shl RTL8139_BIT_93C46_EEM1) or (1 shl RTL8139_BIT_93C46_EECS)
|
|
out dx, al
|
|
mov cl, 0xf
|
|
.read_loop:
|
|
shl ebx, 1
|
|
mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
|
|
or (1 shl RTL8139_BIT_93C46_EECS) \
|
|
or (1 shl RTL8139_BIT_93C46_EESK)
|
|
out dx, al
|
|
; in eax, dx ; eeprom delay
|
|
in al, dx
|
|
and al, (1 shl RTL8139_BIT_93C46_EEDO)
|
|
jz .dont_set
|
|
inc ebx
|
|
.dont_set:
|
|
mov al, (1 shl RTL8139_BIT_93C46_EEM1) \
|
|
or (1 shl RTL8139_BIT_93C46_EECS)
|
|
out dx, al
|
|
; in eax, dx ; eeprom delay
|
|
dec cl
|
|
jns .read_loop
|
|
xor al, al
|
|
out dx, al
|
|
mov ax, bx
|
|
ret
|
|
|
|
;***************************************************************************
|
|
; Function
|
|
; rtl8139_transmit
|
|
; Description
|
|
; Transmits a packet of data via the ethernet card
|
|
; Pointer to 48 bit destination address in edi
|
|
; Type of packet in bx
|
|
; Size of packet in ecx
|
|
; Pointer to packet data in esi
|
|
; Destroyed registers
|
|
; eax, edx, esi, edi
|
|
; ToDo
|
|
; for waiting of timeout the rtl8139 internal timer
|
|
; should be used
|
|
;
|
|
;***************************************************************************
|
|
rtl8139_transmit:
|
|
cmp ecx, MAX_ETH_FRAME_SIZE
|
|
jg .finish ; packet is too long
|
|
push ecx
|
|
; check descriptor
|
|
mov ecx, [curr_tx_desc]
|
|
mov edx, [io_addr]
|
|
lea edx, [edx+ecx*4+RTL8139_REG_TSD0]
|
|
push edx ebx
|
|
in ax, dx
|
|
test ax, 0x1fff ; or no size given
|
|
jz .send_packet
|
|
and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
|
|
cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
|
|
jz .send_packet
|
|
; wait for timeout
|
|
mov ebx, RTL8139_TX_TIMEOUT
|
|
mov eax, 0x5 ; delay x/100 secs
|
|
int 0x40
|
|
in ax, dx
|
|
and ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
|
|
cmp ax, (1 shl RTL8139_BIT_TOK) or (1 shl RTL8139_BIT_OWN)
|
|
jz .send_packet
|
|
; chip hung, reset it
|
|
call rtl8139_reset
|
|
; reset the card
|
|
.send_packet:
|
|
; calculate tx_buffer address
|
|
pop ebx
|
|
push esi
|
|
mov eax, MAX_ETH_FRAME_SIZE
|
|
mul dword [curr_tx_desc]
|
|
mov esi, edi
|
|
lea edi, [rtl8139_tx_buff+eax]
|
|
mov eax, edi
|
|
cld
|
|
; copy destination address
|
|
movsd
|
|
movsw
|
|
; copy source address
|
|
mov esi, node_addr
|
|
movsd
|
|
movsw
|
|
; copy packet type
|
|
mov [edi], bx
|
|
add edi, 2
|
|
; copy the packet data
|
|
pop esi edx ecx
|
|
push ecx
|
|
shr ecx, 2
|
|
rep movsd
|
|
pop ecx
|
|
push ecx
|
|
and ecx, 3
|
|
rep movsb
|
|
; set address
|
|
sub eax, OS_BASE
|
|
add edx, RTL8139_REG_TSAD0 - RTL8139_REG_TSD0
|
|
out dx, eax
|
|
; set size and early threshold
|
|
pop eax ; pick up the size
|
|
add eax, ETH_HLEN
|
|
cmp eax, ETH_ZLEN
|
|
jnc .no_pad
|
|
mov eax, ETH_ZLEN
|
|
.no_pad:
|
|
or eax, (RTL8139_ERTXTH shl RTL8139_BIT_ERTXTH)
|
|
add edx, RTL8139_REG_TSD0 - RTL8139_REG_TSAD0
|
|
out dx, eax
|
|
; get next descriptor 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, ...
|
|
inc dword [curr_tx_desc]
|
|
and dword [curr_tx_desc], 3
|
|
.finish:
|
|
ret
|
|
|
|
;***************************************************************************
|
|
; Function
|
|
; rtl8139_poll
|
|
;
|
|
; Description
|
|
; Polls the ethernet card for a received packet
|
|
; Received data, if any, ends up in Ether_buffer
|
|
; Destroyed register(s)
|
|
; eax, edx, ecx
|
|
;
|
|
;***************************************************************************
|
|
rtl8139_poll:
|
|
mov word [eth_rx_data_len], 0
|
|
mov edx, [io_addr]
|
|
add edx, RTL8139_REG_COMMAND
|
|
in al, dx
|
|
test al, (1 shl RTL8139_BIT_BUFE)
|
|
jnz .finish
|
|
; new packet received copy it from rx_buffer into Ether_buffer
|
|
mov eax, rtl8139_rx_buff
|
|
add eax, [rtl8139_rx_buff_offset]
|
|
; check if packet is ok
|
|
test byte [eax], (1 shl RTL8139_BIT_ROK)
|
|
jz .reset_rx
|
|
; packet is ok copy it into the Ether_buffer
|
|
movzx ecx, word [eax+2] ; packet length
|
|
sub ecx, 4 ; don't copy CRC
|
|
mov word [eth_rx_data_len], cx
|
|
push ecx
|
|
shr ecx, 2 ; first copy dword-wise
|
|
lea esi, [eax+4] ; don't copy the packet header
|
|
mov edi, Ether_buffer
|
|
cld
|
|
rep movsd ; copy the dwords
|
|
pop ecx
|
|
and ecx, 3
|
|
rep movsb ; copy the rest bytes
|
|
; update rtl8139_rx_buff_offset
|
|
movzx eax, word [eax+2] ; packet length
|
|
add eax, [rtl8139_rx_buff_offset]
|
|
add eax, 4+3 ; packet header is 4 bytes long + dword alignment
|
|
and eax, not 3 ; dword alignment
|
|
cmp eax, RTL8139_RX_BUFFER_SIZE
|
|
jl .no_wrap
|
|
sub eax, RTL8139_RX_BUFFER_SIZE
|
|
.no_wrap:
|
|
mov [rtl8139_rx_buff_offset], eax
|
|
; update CAPR register
|
|
sub eax, 0x10 ; value 0x10 is a constant for CAPR
|
|
add edx, RTL8139_REG_CAPR - RTL8139_REG_COMMAND
|
|
out dx, ax
|
|
.finish:
|
|
; clear active interrupt sources
|
|
mov edx, [io_addr]
|
|
add edx, RTL8139_REG_ISR
|
|
in ax, dx
|
|
out dx, ax
|
|
ret
|
|
.reset_rx:
|
|
in al, dx ; read command register
|
|
push eax
|
|
and al, not (1 shl RTL8139_BIT_RE)
|
|
out dx, al
|
|
pop eax
|
|
out dx, al
|
|
add edx, RTL8139_REG_RXCONFIG - RTL8139_REG_COMMAND
|
|
mov ax, RTL8139_RX_CONFIG
|
|
out dx, ax
|
|
ret
|
|
|
|
rtl8139_cable:
|
|
pusha
|
|
mov edx, [io_addr]
|
|
add edx, 0x58
|
|
in al, dx
|
|
test al, 1 SHL 2
|
|
jnz .notconnected
|
|
popa
|
|
xor al, al
|
|
inc al
|
|
ret
|
|
.notconnected:
|
|
popa
|
|
xor al, al
|
|
ret
|