forked from KolibriOS/kolibrios
320 lines
7.6 KiB
C
320 lines
7.6 KiB
C
#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "bitmap.h"
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void __init dmi_scan_machine(void);
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#define KMS_DEV_CLOSE 0
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#define KMS_DEV_INIT 1
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#define KMS_DEV_READY 2
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struct pci_device {
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uint16_t domain;
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uint8_t bus;
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uint8_t dev;
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uint8_t func;
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t subvendor_id;
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uint16_t subdevice_id;
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uint32_t device_class;
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uint8_t revision;
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};
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struct drm_device *main_device;
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struct drm_file *drm_file_handlers[256];
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videomode_t usermode;
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void cpu_detect1();
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int _stdcall display_handler(ioctl_t *io);
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static char log[256];
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unsigned long volatile jiffies;
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u64 jiffies_64;
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struct workqueue_struct *system_wq;
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int driver_wq_state;
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int x86_clflush_size;
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void ati_driver_thread()
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{
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struct radeon_device *rdev = NULL;
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struct workqueue_struct *cwq = NULL;
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// static int dpms = 1;
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// static int dpms_lock = 0;
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// oskey_t key;
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unsigned long irqflags;
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int tmp;
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printf("%s\n",__FUNCTION__);
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while(driver_wq_state == KMS_DEV_INIT)
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{
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jiffies = GetTimerTicks();
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jiffies_64 = jiffies;
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delay(1);
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};
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rdev = main_device->dev_private;
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// cwq = rdev->wq;
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asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1));
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asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330));
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asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330));
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while(driver_wq_state != KMS_DEV_CLOSE)
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{
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jiffies = GetTimerTicks();
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#if 0
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key = get_key();
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if( (key.val != 1) && (key.state == 0x02))
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{
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if(key.code == 0x46 && dpms_lock == 0)
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{
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dpms_lock = 1;
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if(dpms == 1)
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{
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i915_dpms(main_device, DRM_MODE_DPMS_OFF);
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printf("dpms off\n");
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}
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else
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{
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i915_dpms(main_device, DRM_MODE_DPMS_ON);
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printf("dpms on\n");
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};
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dpms ^= 1;
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}
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else if(key.code == 0xC6)
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dpms_lock = 0;
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};
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spin_lock_irqsave(&cwq->lock, irqflags);
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while (!list_empty(&cwq->worklist))
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{
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struct work_struct *work = list_entry(cwq->worklist.next,
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struct work_struct, entry);
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work_func_t f = work->func;
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list_del_init(cwq->worklist.next);
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spin_unlock_irqrestore(&cwq->lock, irqflags);
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f(work);
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spin_lock_irqsave(&cwq->lock, irqflags);
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}
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spin_unlock_irqrestore(&cwq->lock, irqflags);
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#endif
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delay(1);
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};
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asm volatile ("int $0x40"::"a"(-1));
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}
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u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
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{
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struct radeon_device *rdev = NULL;
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const struct pci_device_id *ent;
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int err = 0;
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if(action != 1)
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{
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driver_wq_state = KMS_DEV_CLOSE;
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return 0;
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};
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if( GetService("DISPLAY") != 0 )
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return 0;
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printf("Radeon v3.19-rc3 cmdline %s\n", cmdline);
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if( cmdline && *cmdline )
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parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
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if( *log && !dbg_open(log))
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{
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printf("Can't open %s\nExit\n", log);
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return 0;
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}
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cpu_detect1();
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err = enum_pci_devices();
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if( unlikely(err != 0) )
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{
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dbgprintf("Device enumeration failed\n");
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return 0;
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}
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driver_wq_state = KMS_DEV_INIT;
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CreateKernelThread(ati_driver_thread);
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err = ati_init();
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if(unlikely(err!= 0))
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{
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driver_wq_state = KMS_DEV_CLOSE;
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dbgprintf("Epic Fail :(\n");
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return 0;
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};
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driver_wq_state = KMS_DEV_READY;
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rdev = main_device->dev_private;
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printf("current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
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printf("current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
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err = RegService("DISPLAY", display_handler);
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if( err != 0)
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dbgprintf("DISPLAY service installed\n");
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return err;
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};
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#define CURRENT_API 0x0200 /* 2.00 */
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#define COMPATIBLE_API 0x0100 /* 1.00 */
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#define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API
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#define SRV_GETVERSION 0
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#define SRV_ENUM_MODES 1
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#define SRV_SET_MODE 2
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#define SRV_GET_CAPS 3
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#define SRV_CREATE_SURFACE 10
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#define SRV_DESTROY_SURFACE 11
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#define SRV_LOCK_SURFACE 12
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#define SRV_UNLOCK_SURFACE 13
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#define SRV_RESIZE_SURFACE 14
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#define SRV_BLIT_BITMAP 15
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#define SRV_BLIT_TEXTURE 16
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#define SRV_BLIT_VIDEO 17
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int r600_video_blit(uint64_t src_offset, int x, int y,
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int w, int h, int pitch);
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#define check_input(size) \
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if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \
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break;
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#define check_output(size) \
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if( unlikely((outp==NULL)||(io->out_size != (size))) ) \
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break;
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int _stdcall display_handler(ioctl_t *io)
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{
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int retval = -1;
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u32 *inp;
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u32 *outp;
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inp = io->input;
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outp = io->output;
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switch(io->io_code)
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{
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case SRV_GETVERSION:
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check_output(4);
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*outp = API_VERSION;
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retval = 0;
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break;
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case SRV_ENUM_MODES:
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// dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
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// inp, io->inp_size, io->out_size );
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check_output(4);
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if( radeon_modeset)
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retval = get_videomodes((videomode_t*)inp, outp);
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break;
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case SRV_SET_MODE:
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// dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
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// inp, io->inp_size);
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check_input(sizeof(videomode_t));
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if( radeon_modeset )
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retval = set_user_mode((videomode_t*)inp);
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break;
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/*
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case SRV_GET_CAPS:
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retval = get_driver_caps((hwcaps_t*)inp);
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break;
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case SRV_CREATE_SURFACE:
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// check_input(8);
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retval = create_surface(main_drm_device, (struct io_call_10*)inp);
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break;
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case SRV_LOCK_SURFACE:
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retval = lock_surface((struct io_call_12*)inp);
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break;
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case SRV_BLIT_BITMAP:
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srv_blit_bitmap( inp[0], inp[1], inp[2],
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inp[3], inp[4], inp[5], inp[6]);
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*/
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};
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return retval;
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}
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#define PCI_CLASS_REVISION 0x08
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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int pci_scan_filter(u32 id, u32 busnr, u32 devfn)
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{
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u16 vendor, device;
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u32 class;
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int ret = 0;
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vendor = id & 0xffff;
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device = (id >> 16) & 0xffff;
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if(vendor == 0x1002)
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{
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class = PciRead32(busnr, devfn, PCI_CLASS_REVISION);
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class >>= 24;
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if( class ==PCI_BASE_CLASS_DISPLAY)
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ret = 1;
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}
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return ret;
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}
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int seq_printf(struct seq_file *m, const char *f, ...)
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{
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// int ret;
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// va_list args;
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// va_start(args, f);
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// ret = seq_vprintf(m, f, args);
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// va_end(args);
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// return ret;
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return 0;
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}
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s64 div64_s64(s64 dividend, s64 divisor)
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{
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s64 quot, t;
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quot = div64_u64(abs64(dividend), abs64(divisor));
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t = (dividend ^ divisor) >> 63;
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return (quot ^ t) - t;
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}
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