forked from KolibriOS/kolibrios
414 lines
12 KiB
C
414 lines
12 KiB
C
/* Opcode table for the ARC.
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Copyright 1994-2015 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING3. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef OPCODE_ARC_H
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#define OPCODE_ARC_H
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#define MAX_INSN_ARGS 6
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#define MAX_INSN_FLGS 3
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/* Instruction Class. */
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typedef enum
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{
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ARITH,
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AUXREG,
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BRANCH,
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CONTROL,
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DSP,
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FLOAT,
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INVALID,
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JUMP,
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KERNEL,
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LOGICAL,
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MEMORY,
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} insn_class_t;
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/* Instruction Subclass. */
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typedef enum
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{
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NONE,
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CVT,
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BTSCN,
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CD1,
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CD2,
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DIV,
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DP,
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MPY1E,
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MPY6E,
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MPY7E,
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MPY8E,
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MPY9E,
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SHFT1,
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SHFT2,
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SWAP,
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SP
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} insn_subclass_t;
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/* Flags class. */
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typedef enum
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{
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FNONE,
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CND, /* Conditional flags. */
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WBM, /* Write-back modes. */
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FLG, /* F Flag. */
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SBP, /* Static branch prediction. */
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DLY, /* Delay slot. */
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DIF, /* Bypass caches. */
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SGX, /* Sign extend modes. */
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SZM /* Data size modes. */
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} flag_class_t;
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/* The opcode table is an array of struct arc_opcode. */
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struct arc_opcode
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{
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/* The opcode name. */
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const char *name;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned mask;
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/* One bit flags for the opcode. These are primarily used to
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indicate specific processors and environments support the
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instructions. The defined values are listed below. */
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unsigned cpu;
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/* The instruction class. This is used by gdb. */
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insn_class_t class;
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/* The instruction subclass. */
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insn_subclass_t subclass;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[MAX_INSN_ARGS + 1];
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/* An array of flag codes. Each code is an index into the flag
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table. They appear in the order which the flags must appear in
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assembly code, and are terminated by a zero. */
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unsigned char flags[MAX_INSN_FLGS + 1];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct arc_opcode arc_opcodes[];
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extern const unsigned arc_num_opcodes;
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/* CPU Availability. */
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#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
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#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
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#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
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#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
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/* CPU extensions. */
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#define ARC_EA 0x0001
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#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
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#define ARC_LLOCK 0x0002
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#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
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#define ARC_MPY 0x0004
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#define ARC_MULT 0x0004
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/* Floating point support. */
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#define ARC_DPFP 0x0010
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#define ARC_SPFP 0x0020
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#define ARC_FPU 0x0030
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/* NORM & SWAP. */
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#define ARC_SWAP 0x0100
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#define ARC_NORM 0x0200
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#define ARC_BSCAN 0x0200
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/* A7 specific. */
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#define ARC_UIX 0x1000
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#define ARC_TSTAMP 0x1000
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/* A6 specific. */
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#define ARC_VBFDW 0x1000
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#define ARC_BARREL 0x1000
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#define ARC_DSPA 0x1000
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/* EM specific. */
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#define ARC_SHIFT 0x1000
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/* V2 specific. */
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#define ARC_INTR 0x1000
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#define ARC_DIV 0x1000
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/* V1 specific. */
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#define ARC_XMAC 0x1000
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#define ARC_CRC 0x1000
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/* Base architecture -- all cpus. */
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#define ARC_OPCODE_BASE \
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(ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
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/* A macro to check for short instructions. */
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#define ARC_SHORT(mask) \
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(((mask) & 0xFFFF0000) ? 0 : 1)
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/* The operands table is an array of struct arc_operand. */
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struct arc_operand
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{
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/* The number of bits in the operand. */
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unsigned int bits;
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/* How far the operand is left shifted in the instruction. */
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unsigned int shift;
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/* The default relocation type for this operand. */
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signed int default_reloc;
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/* One bit syntax flags. */
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unsigned int flags;
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (op & ((1 << o->bits) - 1)) << o->shift;
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(i is the instruction which we are filling in, o is a pointer to
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this structure, and op is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & ARC_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(i is the instruction, o is a pointer to this structure, and op
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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TRUE if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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int (*extract) (unsigned instruction, bfd_boolean *invalid);
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the arc_opcodes table. */
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extern const struct arc_operand arc_operands[];
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extern const unsigned arc_num_operands;
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extern const unsigned arc_Toperand;
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extern const unsigned arc_NToperand;
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/* Values defined for the flags field of a struct arc_operand. */
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/* This operand does not actually exist in the assembler input. This
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is used to support extended mnemonics, for which two operands fields
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are identical. The assembler should call the insert function with
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any op value. The disassembler should call the extract function,
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ignore the return value, and check the value placed in the invalid
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argument. */
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#define ARC_OPERAND_FAKE 0x0001
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/* This operand names an integer register. */
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#define ARC_OPERAND_IR 0x0002
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/* This operand takes signed values. */
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#define ARC_OPERAND_SIGNED 0x0004
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/* This operand takes unsigned values. This exists primarily so that
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a flags value of 0 can be treated as end-of-arguments. */
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#define ARC_OPERAND_UNSIGNED 0x0008
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/* This operand takes long immediate values. */
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#define ARC_OPERAND_LIMM 0x0010
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/* This operand is identical like the previous one. */
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#define ARC_OPERAND_DUPLICATE 0x0020
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/* This operand is PC relative. Used for internal relocs. */
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#define ARC_OPERAND_PCREL 0x0040
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/* This operand is truncated. The truncation is done accordingly to
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operand alignment attribute. */
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#define ARC_OPERAND_TRUNCATE 0x0080
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/* This operand is 16bit aligned. */
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#define ARC_OPERAND_ALIGNED16 0x0100
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/* This operand is 32bit aligned. */
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#define ARC_OPERAND_ALIGNED32 0x0200
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/* This operand can be ignored by matching process if it is not
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present. */
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#define ARC_OPERAND_IGNORE 0x0400
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/* Don't check the range when matching. */
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#define ARC_OPERAND_NCHK 0x0800
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/* Mark the braket possition. */
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#define ARC_OPERAND_BRAKET 0x1000
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/* Mask for selecting the type for typecheck purposes. */
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#define ARC_OPERAND_TYPECHECK_MASK \
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(ARC_OPERAND_IR | \
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ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
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ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
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/* The flags structure. */
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struct arc_flag_operand
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{
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/* The flag name. */
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const char *name;
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/* The flag code. */
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unsigned code;
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/* The number of bits in the operand. */
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unsigned int bits;
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/* How far the operand is left shifted in the instruction. */
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unsigned int shift;
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/* Available for disassembler. */
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unsigned char favail;
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};
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/* The flag operands table. */
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extern const struct arc_flag_operand arc_flag_operands[];
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extern const unsigned arc_num_flag_operands;
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/* The flag's class structure. */
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struct arc_flag_class
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{
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/* Flag class. */
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flag_class_t class;
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/* List of valid flags (codes). */
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unsigned flags[256];
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};
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extern const struct arc_flag_class arc_flag_classes[];
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/* Structure for special cases. */
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struct arc_flag_special
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{
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/* Name of special case instruction. */
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const char *name;
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/* List of flags applicable for special case instruction. */
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unsigned flags[32];
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};
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extern const struct arc_flag_special arc_flag_special_cases[];
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extern const unsigned arc_num_flag_special;
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/* Relocation equivalence structure. */
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struct arc_reloc_equiv_tab
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{
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const char * name; /* String to lookup. */
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const char * mnemonic; /* Extra matching condition. */
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unsigned flagcode; /* Extra matching condition. */
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signed int oldreloc; /* Old relocation. */
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signed int newreloc; /* New relocation. */
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};
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extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
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extern const unsigned arc_num_equiv_tab;
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/* Structure for operand operations for pseudo/alias instructions. */
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struct arc_operand_operation
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{
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/* The index for operand from operand array. */
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unsigned operand_idx;
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/* Defines if it needs the operand inserted by the assembler or
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whether this operand comes from the pseudo instruction's
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operands. */
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unsigned char needs_insert;
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/* Count we have to add to the operand. Use negative number to
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subtract from the operand. Also use this number to add to 0 if
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the operand needs to be inserted (i.e. needs_insert == 1). */
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int count;
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/* Index of the operand to swap with. To be done AFTER applying
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inc_count. */
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unsigned swap_operand_idx;
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};
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/* Structure for pseudo/alias instructions. */
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struct arc_pseudo_insn
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{
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/* Mnemonic for pseudo/alias insn. */
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const char *mnemonic_p;
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/* Mnemonic for real instruction. */
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const char *mnemonic_r;
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/* Flag that will have to be added (if any). */
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const char *flag_r;
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/* Amount of operands. */
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unsigned operand_cnt;
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/* Array of operand operations. */
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struct arc_operand_operation operand[6];
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};
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extern const struct arc_pseudo_insn arc_pseudo_insns[];
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extern const unsigned arc_num_pseudo_insn;
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/* Structure for AUXILIARY registers. */
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struct arc_aux_reg
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{
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/* Register address. */
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int address;
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/* Register name. */
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const char *name;
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/* Size of the string. */
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size_t length;
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};
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extern const struct arc_aux_reg arc_aux_regs[];
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extern const unsigned arc_num_aux_regs;
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#endif /* OPCODE_ARC_H */
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