forked from KolibriOS/kolibrios
158 lines
12 KiB
PHP
158 lines
12 KiB
PHP
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; 20/11/2013 yogev_ezra: Initial version (Vortex86 SoC type detection)
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; 26/11/2013 yogev_ezra: Added CPU speed modifier and MMX support flag detection
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; Thanks for help to: dunkaist, eAndrew, hidnplayr, Mario
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$Revision$
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VORTEX86DEBUG = 0 ; For testing in emulators and in non-Vortex86 CPU computers, set this to 1
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VORTEX86DEBUGVALUE = 0x35504d44 ; FAKE port output = used for testing
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NORTH_BRIDGE = 0x80000000 ; Base address of Vortex86 PCI North Bridge
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SOUTH_BRIDGE = 0x80003800 ; Base address of Vortex86 PCI South Bridge
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; Detect Vortex86 CPU and generate CPU name in string format (PCI address at 93H~90H in Vortex86 North Bridge contains SoC type)
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; Available Vortex86 CPU codes taken from Coreboot project. New codes should be added to "Vortex86SoClist" below
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; #define DMP_CPUID_SX 0x31504d44 ("DMP1")
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; #define DMP_CPUID_DX 0x32504d44 ("DMP2")
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; #define DMP_CPUID_MX 0x33504d44 ("DMP3")
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; #define DMP_CPUID_DX2 0x34504d44 ("DMP4")
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; #define DMP_CPUID_MX_PLUS 0x35504d44 ("DMP5")
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; #define DMP_CPUID_EX 0x37504d44 ("DMP7")
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iglobal
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Vortex86CPUcode dd ? ; Vortex86 CPU code in HEX format (4 bytes), can be shown as string if converted to ASCII characters
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Vortex86CPUid db 0 ; Vortex86 CPU id in integer format (1=Vortex86SX, 2=Vortex86DX, ...)
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Vortex86SoCname db 'Vortex86 ',0 ; This variable will hold the full name of Vortex86 SoC
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Vortex86SoClist: ; List of Vortex86 CPUs known today. Add new record to this list when new CPU becomes available
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db 0x31, 'SX ' ; id=1
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db 0x32, 'DX ' ; id=2
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db 0x33, 'MX ' ; id=3 MMX is available starting from CPU code 'MX' (id=3)
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db 0x34, 'DX2' ; id=4
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db 0x35, 'MX+' ; id=5
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db 0x37, 'EX ' ; id=7
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Vortex86SoCnum = ($ - Vortex86SoClist) / 4 ; Calculate the total number of known Vortex86 CPUs
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endg
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; When in debug mode, perform SoC detection regardless of the actual CPU vendor (even for vendors other than DMP)
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; When in normal (not debug) mode, check the CPU vendor first, and perform SoC detection only if vendor is 'Vortex86 SoC'
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if ~ VORTEX86DEBUG
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cmp [cpu_vendor], 'Vort'
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jnz .Vortex86end ; If the CPU vendor is not 'Vortex86 SoC', skip the SoC detection
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end if
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mov eax, NORTH_BRIDGE+0x90 ; 0x80000090 = PCI Configuration Address Register to read from (32-bit register - accessed as DWORD)
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call .Vortex86PCIreg ; Get the CPU code from Vortex86 SoC North Bridge PCI register (Register Offset: 93H~90H)
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if VORTEX86DEBUG ; When in debug mode, pretend that we received port output equal to "VORTEX86DEBUGVALUE"
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mov eax, VORTEX86DEBUGVALUE
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end if
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DEBUGF 1, "K : Vortex86 SoC type register (93H~90H) returned 0x"
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test eax, eax ; Check whether the port output was '\0'
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jz .nullPCIoutput ; In case the result is '\0' (NULL), skip further testing and exit
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mov [Vortex86CPUcode], eax ; Save HEX CPU code to Vortex86CPUcode (so it can be used later)
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DEBUGF 1, "%x (%s): ", eax, Vortex86CPUcode ; Print the CPU code (as HEX and as string) to debug log
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mov ebx, 0x444d5000 ; Apply Vortex86 CPU code mask (all Vortex86 SoC have ID in form of "0xNN504d44")
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bswap eax ; Assumed it is Vortex86 SoC, the highest byte identifies the exact CPU, so move it to the lowest byte
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mov bl, al ; Copy SoC type to BL since EAX (that includes AL) is used implicitly in "LODSD" command below
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cmp eax, ebx ; Now see whether the 3 higher bytes were "0x504d44" (which means it's Vortex86)
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jnz .notVortex86 ; If it's not Vortex86 - go say so and exit
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sub al, 0x30 ; Current Vortex86 CPU codes are in the range of 31h-37h, so convert them to integer (1,2,...)
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mov [Vortex86CPUid], al ; Save the CPUid (1=Vortex86SX, 2=Vortex86DX, ..., 7=Vortex86EX, ...)
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mov esi, Vortex86SoClist ; ESI points to the start of Vortex86SoClist (used implicitly in "LODSD" command below)
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xor ecx, ecx ; Zero ECX (it is used as counter)
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cld ; Clears the DF flag in the EFLAGS register (DF=0 --> String operations increment ESI)
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@@:
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inc ecx ; Increment our counter
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cmp ecx, Vortex86SoCnum ; Check if we iterated Vortex86SoCnum times already (i.e. went over the entire Vortex86SoClist)
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ja .unknownVortex86 ; If the entire list was tested and our CPU is not in that list, it is unknown Vortex86 SoC
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lodsd ; Load DWORD at address DS:ESI into EAX (puts 1 line from Vortex86SoClist into EAX, then increments ESI)
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cmp bl, al ; Check if our CPU matches the current record in the list
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jne @b ; No match --> repeat with next record
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shr eax, 8 ; Match found --> drop the SoC type code from Vortex86SoClist name and replace it with \0
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mov dword [Vortex86SoCname+8], eax ; Concatenate it with prefix to receive complete SoC name (\0 is string termination)
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DEBUGF 1, "%s (id=%d)\n", Vortex86SoCname, [Vortex86CPUid]:1 ; Say what we have found (CPU name and id)
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jmp .Vortex86
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.notVortex86: ; In case this register is used by other CPUs for other purpose, it's interesting what it contains
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DEBUGF 1, "not a Vortex86 CPU\n"
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jmp .Vortex86end
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.unknownVortex86: ; It is Vortex86 CPU, but it's not in the list above
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DEBUGF 1, "unknown Vortex86 CPU (id=%d)\n", [Vortex86CPUid]:1 ; Inform the user that the CPU is Vortex86 but name is unknown
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.Vortex86:
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mov eax, NORTH_BRIDGE+0x60 ; 0x80000060 = PCI Configuration Address Register to read from (32-bit register - accessed as DWORD)
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call .Vortex86PCIreg ; Get current flags of Vortex86SoC North Bridge STRAP Register (Register Offset: 63h~60h)
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DEBUGF 1, "K : Vortex86 STRAP Register (63h~60h) returned 0x%x\n",eax
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mov eax, SOUTH_BRIDGE+0xC0 ; 0x800038C0 = PCI Configuration Address Register to read from (32-bit register - accessed as DWORD)
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call .Vortex86PCIreg ; Flags of Vortex86 South Bridge Internal Peripheral Feature Control Register (Register Offset: C3h~C0h)
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DEBUGF 1, "K : Vortex86 Internal Peripheral Feature Control Register (C3h~C0h) returned 0x%x\n",eax
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mov eax, SOUTH_BRIDGE+0xCC ; 0x800038CC = PCI Configuration Address Register to read from (8-bit register - accessed as BYTE)
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call .Vortex86PCIreg ; Flags of Vortex86 South Bridge Internal Peripheral Feature Control Register III (Register Offset: CCh)
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DEBUGF 1, "K : Vortex86 Internal Peripheral Feature Control Register III (CCh) returned 0x%x\n",al
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mov eax, NORTH_BRIDGE+0xA0 ; 0x800000A0 = PCI Configuration Address Register to read from (32-bit register - accessed as DWORD)
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call .Vortex86PCIreg ; Get current flags of Vortex86SoC North Bridge Host Control Register (Register Offset: A3h~A0h)
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DEBUGF 1, "K : Vortex86 Host Control Register (A3h~A0h) returned 0x%x: CPU speed is ",eax
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mov bl, al ; The lower byte of Vortex86 Host Control Register contains CPU speed modifier and MMX support status
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mov bh, al ; Backup the current AL value, so later we can test whether the value has changed
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and bl, 00000111b ; CPU speed modifier is stored in bits 0-2. Value=0 means MAX speed, other values - speed reduction
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jz .Vortex86CPUspeedMAX ; 0s in bits 0-2: CPU is at MAX speed (no need to modify)
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inc ebx ; The actual value is 1 less than 'Divide by' setting (value '001' means 'Divide by 2', etc.)
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DEBUGF 1, "reduced (divide by %d).\nK : Vortex86 changing CPU speed to ", bl ; Print the current CPU speed modifier to the log
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and al, 11111000b ; At least one of the bits 0-2 contains 1: CPU is at reduced speed. Set bits 0-2 to 0s to change to MAX
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.Vortex86CPUspeedMAX:
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DEBUGF 1, "MAX\n" ; Now the CPU should be running at MAX speed (don't write the value to PCI port yet)
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cmp [Vortex86CPUid], 3 ; MMX is available starting from CPU code 'MX' (id=3)
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jb .skipVortex86MMX ; No MMX support - skip MMX support status detection (for id=1,2)
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DEBUGF 1, "K : Vortex86 MMX support status: MMX is " ; Bits 5-6 in Host Control Register contain MMX status
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test al, 100000b ; On MMX-capable Vortex86 SoC, Bit5 = is MMX enabled? (1=Yes/0=No)
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jnz .Vortex86MMXenabled ; MMX is already enabled (Bit5=1)
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DEBUGF 1, "DISABLED - enabling it for this session\n" ; Print to the log that MMX is disabled
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or al, 100000b ; Enable MMX support (don't write the value to PCI port yet)
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jmp .AfterMMXenabled
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.Vortex86MMXenabled:
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DEBUGF 1, "ENABLED\n" ; Print to the log that MMX is enabled
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.AfterMMXenabled:
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DEBUGF 1, "K : Vortex86 MMX report to CPUID: " ; Print to the log what CPUID command knowns about MMX support
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test al, 1000000b ; On MMX-capable Vortex86 SoC, Bit6 = report MMX support to CPUID? (1=Yes/0=No)
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jnz .Vortex86MMXreported ; MMX is already reported to CPUID (Bit6=1)
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DEBUGF 1, "OFF - turning it ON for this session\n" ; Print to the log that MMX will now be reported to CPUID
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or al, 1000000b ; Turn on MMX reporting to CPUID (don't write the value to PCI port yet)
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jmp .skipVortex86MMX
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.Vortex86MMXreported:
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DEBUGF 1, "ON\n" ; Print to the log that MMX reporting to CPUID is enabled
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.skipVortex86MMX:
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cmp bh, al ; Check whether AL has changed before (if it did, we need to write it back to PCI port)
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jz .Vortex86end ; No change - no need to write to the port
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out dx, al ; Write the changed data to PCI port
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DEBUGF 1, "K : Vortex86 Host Control Register (A3h~A0h) new value is 0x%x\n",eax
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jmp .Vortex86end
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.Vortex86PCIreg: ; Procedure receives input register value in EAX, and returns the output value also in EAX
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mov dx, 0xcf8 ; CF8h = Vortex86 PCI Configuration Address port
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out dx, eax ; Send request to PCI address port to retrieve data from this address
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mov dl, 0xfc ; CFCh = Vortex86 PCI Configuration Data port
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in eax, dx ; Read data from PCI data port
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ret
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.nullPCIoutput: ; Emulators and non-Vortex86 CPU computers will usually return \0 in this register
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DEBUGF 1, "0 (NULL)\n"
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.Vortex86end: |