forked from KolibriOS/kolibrios
579 lines
25 KiB
C
579 lines
25 KiB
C
/*
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* pci.h
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*
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* PCI defines and function prototypes
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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*
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* For more information, please consult the following manuals (look at
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* http://www.pcisig.com/ for how to get them):
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*
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* PCI BIOS Specification
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* PCI Local Bus Specification
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* PCI to PCI Bridge Specification
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* PCI System Design Guide
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*/
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#ifndef LINUX_PCI_H
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#define LINUX_PCI_H
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#include <types.h>
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#include <list.h>
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#define PCI_ANY_ID (~0)
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#define PCI_CLASS_NOT_DEFINED 0x0000
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#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
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#define PCI_BASE_CLASS_STORAGE 0x01
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#define PCI_CLASS_STORAGE_SCSI 0x0100
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#define PCI_CLASS_STORAGE_IDE 0x0101
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#define PCI_CLASS_STORAGE_FLOPPY 0x0102
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#define PCI_CLASS_STORAGE_IPI 0x0103
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#define PCI_CLASS_STORAGE_RAID 0x0104
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#define PCI_CLASS_STORAGE_SATA 0x0106
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#define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
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#define PCI_CLASS_STORAGE_SAS 0x0107
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#define PCI_CLASS_STORAGE_OTHER 0x0180
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#define PCI_BASE_CLASS_NETWORK 0x02
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#define PCI_CLASS_NETWORK_ETHERNET 0x0200
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#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
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#define PCI_CLASS_NETWORK_FDDI 0x0202
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#define PCI_CLASS_NETWORK_ATM 0x0203
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#define PCI_CLASS_NETWORK_OTHER 0x0280
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#define PCI_BASE_CLASS_DISPLAY 0x03
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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#define PCI_CLASS_DISPLAY_XGA 0x0301
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#define PCI_CLASS_DISPLAY_3D 0x0302
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#define PCI_CLASS_DISPLAY_OTHER 0x0380
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#define PCI_BASE_CLASS_MULTIMEDIA 0x04
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#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
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#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
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#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
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#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
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#define PCI_BASE_CLASS_MEMORY 0x05
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#define PCI_CLASS_MEMORY_RAM 0x0500
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#define PCI_CLASS_MEMORY_FLASH 0x0501
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#define PCI_CLASS_MEMORY_OTHER 0x0580
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#define PCI_BASE_CLASS_BRIDGE 0x06
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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#define PCI_CLASS_BRIDGE_ISA 0x0601
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#define PCI_CLASS_BRIDGE_EISA 0x0602
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#define PCI_CLASS_BRIDGE_MC 0x0603
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#define PCI_CLASS_BRIDGE_PCI 0x0604
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#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
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#define PCI_CLASS_BRIDGE_NUBUS 0x0606
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#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
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#define PCI_CLASS_BRIDGE_RACEWAY 0x0608
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#define PCI_CLASS_BRIDGE_OTHER 0x0680
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#define PCI_BASE_CLASS_COMMUNICATION 0x07
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#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
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#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
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#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
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#define PCI_CLASS_COMMUNICATION_MODEM 0x0703
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#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
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#define PCI_BASE_CLASS_SYSTEM 0x08
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#define PCI_CLASS_SYSTEM_PIC 0x0800
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#define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010
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#define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020
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#define PCI_CLASS_SYSTEM_DMA 0x0801
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#define PCI_CLASS_SYSTEM_TIMER 0x0802
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#define PCI_CLASS_SYSTEM_RTC 0x0803
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#define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804
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#define PCI_CLASS_SYSTEM_SDHCI 0x0805
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#define PCI_CLASS_SYSTEM_OTHER 0x0880
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#define PCI_BASE_CLASS_INPUT 0x09
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#define PCI_CLASS_INPUT_KEYBOARD 0x0900
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#define PCI_CLASS_INPUT_PEN 0x0901
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#define PCI_CLASS_INPUT_MOUSE 0x0902
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#define PCI_CLASS_INPUT_SCANNER 0x0903
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#define PCI_CLASS_INPUT_GAMEPORT 0x0904
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#define PCI_CLASS_INPUT_OTHER 0x0980
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#define PCI_BASE_CLASS_DOCKING 0x0a
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#define PCI_CLASS_DOCKING_GENERIC 0x0a00
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#define PCI_CLASS_DOCKING_OTHER 0x0a80
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#define PCI_BASE_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_PROCESSOR_386 0x0b00
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#define PCI_CLASS_PROCESSOR_486 0x0b01
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#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
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#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
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#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
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#define PCI_CLASS_PROCESSOR_MIPS 0x0b30
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#define PCI_CLASS_PROCESSOR_CO 0x0b40
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#define PCI_BASE_CLASS_SERIAL 0x0c
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#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
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#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
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#define PCI_CLASS_SERIAL_ACCESS 0x0c01
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#define PCI_CLASS_SERIAL_SSA 0x0c02
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#define PCI_CLASS_SERIAL_USB 0x0c03
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#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300
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#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310
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#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
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#define PCI_CLASS_SERIAL_FIBER 0x0c04
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#define PCI_CLASS_SERIAL_SMBUS 0x0c05
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#define PCI_BASE_CLASS_WIRELESS 0x0d
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#define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10
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#define PCI_CLASS_WIRELESS_WHCI 0x0d1010
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#define PCI_BASE_CLASS_INTELLIGENT 0x0e
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#define PCI_CLASS_INTELLIGENT_I2O 0x0e00
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#define PCI_BASE_CLASS_SATELLITE 0x0f
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#define PCI_CLASS_SATELLITE_TV 0x0f00
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#define PCI_CLASS_SATELLITE_AUDIO 0x0f01
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#define PCI_CLASS_SATELLITE_VOICE 0x0f03
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#define PCI_CLASS_SATELLITE_DATA 0x0f04
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#define PCI_BASE_CLASS_CRYPT 0x10
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#define PCI_CLASS_CRYPT_NETWORK 0x1000
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#define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001
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#define PCI_CLASS_CRYPT_OTHER 0x1080
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#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
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#define PCI_CLASS_SP_DPIO 0x1100
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#define PCI_CLASS_SP_OTHER 0x1180
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#define PCI_CLASS_OTHERS 0xff
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/*
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_VENDOR_ID 0x000 /* 16 bits */
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#define PCI_DEVICE_ID 0x002 /* 16 bits */
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#define PCI_COMMAND 0x004 /* 16 bits */
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#define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */
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#define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */
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#define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */
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#define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */
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#define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */
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#define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */
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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
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#define PCI_STATUS 0x006 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */
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#define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
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#define PCI_REVISION_ID 0x08 /* Revision ID */
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f /* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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* Decoded size can be determined by writing a value of
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* 0xffffffff to the register, and reading it back. Only
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* 1 bits are decoded.
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*/
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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/* bit 1 is reserved if address_space = 1 */
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#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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/* Header type 0 (normal devices) */
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#define PCI_CARDBUS_CIS 0x28
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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#define PCI_SUBSYSTEM_ID 0x2e
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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#define PCI_CB_SUBSYSTEM_ID 0x42
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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#define PCI_CB_CAPABILITY_LIST 0x14
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/* Capability lists */
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#define PCI_CAP_LIST_ID 0 /* Capability ID */
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#define PCI_CAP_ID_PM 0x01 /* Power Management */
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#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
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#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */
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#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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/* AGP registers */
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#define PCI_AGP_VERSION 2 /* BCD version number */
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#define PCI_AGP_RFU 3 /* Rest of capability flags */
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#define PCI_AGP_STATUS 4 /* Status register */
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#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
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#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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#define PCI_AGP_COMMAND 8 /* Control register */
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#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
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#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
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#define PCI_AGP_SIZEOF 12
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#define PCI_MAP_REG_START 0x10
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#define PCI_MAP_REG_END 0x28
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#define PCI_MAP_ROM_REG 0x30
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#define PCI_MAP_MEMORY 0x00000000
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#define PCI_MAP_IO 0x00000001
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#define PCI_MAP_MEMORY_TYPE 0x00000007
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#define PCI_MAP_IO_TYPE 0x00000003
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#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
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#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
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#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
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#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
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#define PCI_MAP_MEMORY_CACHABLE 0x00000008
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#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
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#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
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#define PCI_MAP_IO_ATTR_MASK 0x00000003
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#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
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#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
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#define PCI_MAP_IS64BITMEM(b) \
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(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
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#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
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#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1))
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#define PCIGETMEMORY64(b) \
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(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
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#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
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#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
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#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
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#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
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#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
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#ifndef PCI_DOM_MASK
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# define PCI_DOM_MASK 0x0ffu
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#endif
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#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
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#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
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(((d) & 0x00001fu) << 11) | \
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(((f) & 0x000007u) << 8))
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#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK))
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#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11)
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#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
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#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8)
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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typedef unsigned int PCITAG;
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extern inline PCITAG
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pciTag(int busnum, int devnum, int funcnum)
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{
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return(PCI_MAKE_TAG(busnum,devnum,funcnum));
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}
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struct resource
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{
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resource_size_t start;
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resource_size_t end;
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// const char *name;
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unsigned long flags;
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// struct resource *parent, *sibling, *child;
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};
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/*
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* IO resources have these defined flags.
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*/
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#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */
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#define IORESOURCE_IO 0x00000100 /* Resource type */
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#define IORESOURCE_MEM 0x00000200
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#define IORESOURCE_IRQ 0x00000400
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#define IORESOURCE_DMA 0x00000800
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#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
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#define IORESOURCE_READONLY 0x00002000
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#define IORESOURCE_CACHEABLE 0x00004000
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#define IORESOURCE_RANGELENGTH 0x00008000
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#define IORESOURCE_SHADOWABLE 0x00010000
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#define IORESOURCE_BUS_HAS_VGA 0x00080000
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#define IORESOURCE_DISABLED 0x10000000
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#define IORESOURCE_UNSET 0x20000000
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#define IORESOURCE_AUTO 0x40000000
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#define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */
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/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_IRQ_HIGHEDGE (1<<0)
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#define IORESOURCE_IRQ_LOWEDGE (1<<1)
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#define IORESOURCE_IRQ_HIGHLEVEL (1<<2)
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#define IORESOURCE_IRQ_LOWLEVEL (1<<3)
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#define IORESOURCE_IRQ_SHAREABLE (1<<4)
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/* ISA PnP DMA specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_DMA_TYPE_MASK (3<<0)
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#define IORESOURCE_DMA_8BIT (0<<0)
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#define IORESOURCE_DMA_8AND16BIT (1<<0)
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#define IORESOURCE_DMA_16BIT (2<<0)
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#define IORESOURCE_DMA_MASTER (1<<2)
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#define IORESOURCE_DMA_BYTE (1<<3)
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#define IORESOURCE_DMA_WORD (1<<4)
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#define IORESOURCE_DMA_SPEED_MASK (3<<6)
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#define IORESOURCE_DMA_COMPATIBLE (0<<6)
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#define IORESOURCE_DMA_TYPEA (1<<6)
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#define IORESOURCE_DMA_TYPEB (2<<6)
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#define IORESOURCE_DMA_TYPEF (3<<6)
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/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */
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#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */
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#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */
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#define IORESOURCE_MEM_TYPE_MASK (3<<3)
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#define IORESOURCE_MEM_8BIT (0<<3)
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#define IORESOURCE_MEM_16BIT (1<<3)
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#define IORESOURCE_MEM_8AND16BIT (2<<3)
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#define IORESOURCE_MEM_32BIT (3<<3)
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#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */
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#define IORESOURCE_MEM_EXPANSIONROM (1<<6)
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/* PCI ROM control bits (IORESOURCE_BITS) */
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#define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
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#define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */
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#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */
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#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */
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/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
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#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
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/*
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* For PCI devices, the region numbers are assigned this way:
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*
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* 0-5 standard PCI regions
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* 6 expansion ROM
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* 7-10 bridges: address space assigned to buses behind the bridge
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*/
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#define PCI_ROM_RESOURCE 6
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#define PCI_BRIDGE_RESOURCES 7
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#define PCI_NUM_RESOURCES 11
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#ifndef PCI_BUS_NUM_RESOURCES
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#define PCI_BUS_NUM_RESOURCES 8
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#endif
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#define DEVICE_COUNT_RESOURCE 12
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/*
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* The pci_dev structure is used to describe PCI devices.
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*/
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struct pci_dev {
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// struct list_head bus_list; /* node in per-bus list */
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// struct pci_bus *bus; /* bus this device is on */
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// struct pci_bus *subordinate; /* bus this device bridges to */
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// void *sysdata; /* hook for sys-specific extension */
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// struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
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// struct pci_slot *slot; /* Physical slot this device is in */
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u32_t bus;
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u32_t devfn; /* encoded device & function index */
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u16_t vendor;
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u16_t device;
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u16_t subsystem_vendor;
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u16_t subsystem_device;
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u32_t class; /* 3 bytes: (base,sub,prog-if) */
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uint8_t revision; /* PCI revision, low byte of class word */
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uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */
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uint8_t pcie_type; /* PCI-E device/port type */
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uint8_t rom_base_reg; /* which config register controls the ROM */
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uint8_t pin; /* which interrupt pin this device uses */
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// struct pci_driver *driver; /* which driver has allocated this device */
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uint64_t dma_mask; /* Mask of the bits of bus address this
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device implements. Normally this is
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0xffffffff. You only need to change
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this if your device has broken DMA
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or supports 64-bit transfers. */
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// struct device_dma_parameters dma_parms;
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// pci_power_t current_state; /* Current operating state. In ACPI-speak,
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// this is D0-D3, D0 being fully functional,
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// and D3 being off. */
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// int pm_cap; /* PM capability offset in the
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// configuration space */
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unsigned int pme_support:5; /* Bitmask of states from which PME#
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can be generated */
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unsigned int d1_support:1; /* Low power state D1 is supported */
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unsigned int d2_support:1; /* Low power state D2 is supported */
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unsigned int no_d1d2:1; /* Only allow D0 and D3 */
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// pci_channel_state_t error_state; /* current connectivity state */
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struct device dev; /* Generic device interface */
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// int cfg_size; /* Size of configuration space */
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/*
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* Instead of touching interrupt line and base address registers
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* directly, use the values stored here. They might be different!
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*/
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unsigned int irq;
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struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
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/* These fields are used by common fixups */
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unsigned int transparent:1; /* Transparent PCI bridge */
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unsigned int multifunction:1;/* Part of multi-function device */
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/* keep track of device state */
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unsigned int is_added:1;
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unsigned int is_busmaster:1; /* device is busmaster */
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unsigned int no_msi:1; /* device may not use msi */
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unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
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unsigned int broken_parity_status:1; /* Device generates false positive parity */
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unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
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unsigned int msi_enabled:1;
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unsigned int msix_enabled:1;
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unsigned int ari_enabled:1; /* ARI forwarding */
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unsigned int is_managed:1;
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unsigned int is_pcie:1;
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unsigned int state_saved:1;
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unsigned int is_physfn:1;
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unsigned int is_virtfn:1;
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// pci_dev_flags_t dev_flags;
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// atomic_t enable_cnt; /* pci_enable_device has been called */
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// u32 saved_config_space[16]; /* config space saved at suspend time */
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// struct hlist_head saved_cap_space;
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// struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
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// int rom_attr_enabled; /* has display of the rom attribute been enabled? */
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// struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
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// struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
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};
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#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
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#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
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#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
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#define pci_resource_len(dev,bar) \
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((pci_resource_start((dev), (bar)) == 0 && \
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pci_resource_end((dev), (bar)) == \
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pci_resource_start((dev), (bar))) ? 0 : \
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\
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(pci_resource_end((dev), (bar)) - \
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pci_resource_start((dev), (bar)) + 1))
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typedef struct
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{
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struct list_head link;
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struct pci_dev pci_dev;
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}pci_dev_t;
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int enum_pci_devices(void);
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struct pci_device_id*
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find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist);
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#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
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int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
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#define pci_name(x) "radeon"
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#endif //__PCI__H__
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