forked from KolibriOS/kolibrios
1075 lines
30 KiB
C
1075 lines
30 KiB
C
#include <syscall.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/mod_devicetable.h>
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#include <linux/slab.h>
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#include <linux/pm.h>
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#include <linux/pci.h>
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extern int pci_scan_filter(u32 id, u32 busnr, u32 devfn);
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static LIST_HEAD(devices);
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/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
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#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
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#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
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#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */
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#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */
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/*
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* Translate the low bits of the PCI base
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* to the resource type
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*/
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static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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{
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if (flags & PCI_BASE_ADDRESS_SPACE_IO)
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return IORESOURCE_IO;
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if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
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return IORESOURCE_MEM | IORESOURCE_PREFETCH;
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return IORESOURCE_MEM;
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}
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static u32 pci_size(u32 base, u32 maxbase, u32 mask)
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{
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u32 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
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{
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u64 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static inline int is_64bit_memory(u32 mask)
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{
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if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
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return 1;
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return 0;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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u32 pos, reg, next;
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u32 l, sz;
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struct resource *res;
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for(pos=0; pos < howmany; pos = next)
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{
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u64 l64;
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u64 sz64;
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u32 raw_sz;
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next = pos + 1;
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res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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l = PciRead32(dev->busnr, dev->devfn, reg);
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PciWrite32(dev->busnr, dev->devfn, reg, ~0);
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sz = PciRead32(dev->busnr, dev->devfn, reg);
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PciWrite32(dev->busnr, dev->devfn, reg, l);
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if (!sz || sz == 0xffffffff)
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continue;
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if (l == 0xffffffff)
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l = 0;
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raw_sz = sz;
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if ((l & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY)
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{
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sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
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/*
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* For 64bit prefetchable memory sz could be 0, if the
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* real size is bigger than 4G, so we need to check
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* szhi for that.
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*/
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if (!is_64bit_memory(l) && !sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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else {
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sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
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if (!sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_IO_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
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}
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res->end = res->start + (unsigned long) sz;
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res->flags |= pci_calc_resource_flags(l);
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if (is_64bit_memory(l))
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{
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u32 szhi, lhi;
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lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
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PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
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szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
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PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
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sz64 = ((u64)szhi << 32) | raw_sz;
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l64 = ((u64)lhi << 32) | l;
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sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
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next++;
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#if BITS_PER_LONG == 64
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if (!sz64) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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continue;
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}
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res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
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res->end = res->start + sz64;
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#else
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if (sz64 > 0x100000000ULL) {
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printk(KERN_ERR "PCI: Unable to handle 64-bit "
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"BAR for device %s\n", pci_name(dev));
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res->start = 0;
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res->flags = 0;
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}
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else if (lhi)
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{
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/* 64-bit wide address, treat as disabled */
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PciWrite32(dev->busnr, dev->devfn, reg,
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l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
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PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
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res->start = 0;
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res->end = sz;
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}
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#endif
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}
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}
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if ( rom )
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{
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dev->rom_base_reg = rom;
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res = &dev->resource[PCI_ROM_RESOURCE];
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l = PciRead32(dev->busnr, dev->devfn, rom);
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PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
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sz = PciRead32(dev->busnr, dev->devfn, rom);
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PciWrite32(dev->busnr, dev->devfn, rom, l);
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if (l == 0xffffffff)
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l = 0;
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if (sz && sz != 0xffffffff)
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{
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sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
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if (sz)
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{
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res->flags = (l & IORESOURCE_ROM_ENABLE) |
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IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
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res->start = l & PCI_ROM_ADDRESS_MASK;
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res->end = res->start + (unsigned long) sz;
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}
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}
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}
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}
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static void pci_read_irq(struct pci_dev *dev)
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{
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u8 irq;
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irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
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dev->pin = irq;
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if (irq)
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irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
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dev->irq = irq;
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};
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int pci_setup_device(struct pci_dev *dev)
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{
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u32 class;
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class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
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dev->revision = class & 0xff;
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class >>= 8; /* upper 3 bytes */
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dev->class = class;
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/* "Unknown power state" */
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// dev->current_state = PCI_UNKNOWN;
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/* Early fixups, before probing the BARs */
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// pci_fixup_device(pci_fixup_early, dev);
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class = dev->class >> 8;
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switch (dev->hdr_type)
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{
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case PCI_HEADER_TYPE_NORMAL: /* standard header */
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if (class == PCI_CLASS_BRIDGE_PCI)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
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dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
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/*
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* Do the ugly legacy mode stuff here rather than broken chip
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* quirk code. Legacy mode ATA controllers have fixed
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* addresses. These are not always echoed in BAR0-3, and
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* BAR0-3 in a few cases contain junk!
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*/
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if (class == PCI_CLASS_STORAGE_IDE)
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{
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u8 progif;
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progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
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if ((progif & 1) == 0)
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{
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dev->resource[0].start = 0x1F0;
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dev->resource[0].end = 0x1F7;
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dev->resource[0].flags = LEGACY_IO_RESOURCE;
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dev->resource[1].start = 0x3F6;
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dev->resource[1].end = 0x3F6;
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dev->resource[1].flags = LEGACY_IO_RESOURCE;
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}
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if ((progif & 4) == 0)
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{
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dev->resource[2].start = 0x170;
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dev->resource[2].end = 0x177;
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dev->resource[2].flags = LEGACY_IO_RESOURCE;
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dev->resource[3].start = 0x376;
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dev->resource[3].end = 0x376;
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dev->resource[3].flags = LEGACY_IO_RESOURCE;
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};
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}
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
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if (class != PCI_CLASS_BRIDGE_PCI)
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goto bad;
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/* The PCI-to-PCI bridge spec requires that subtractive
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decoding (i.e. transparent) bridge must have programming
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interface code of 0x01. */
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pci_read_irq(dev);
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dev->transparent = ((dev->class & 0xff) == 1);
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pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
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if (class != PCI_CLASS_BRIDGE_CARDBUS)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 1, 0);
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dev->subsystem_vendor = PciRead16(dev->busnr,
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dev->devfn,
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PCI_CB_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->busnr,
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dev->devfn,
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PCI_CB_SUBSYSTEM_ID);
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break;
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default: /* unknown header */
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printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
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pci_name(dev), dev->hdr_type);
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return -1;
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bad:
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printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
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pci_name(dev), class, dev->hdr_type);
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dev->class = PCI_CLASS_NOT_DEFINED;
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}
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/* We found a fine healthy device, go go go... */
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return 0;
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};
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static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
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{
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pci_dev_t *dev;
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u32 id;
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u8 hdr;
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int timeout = 10;
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id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
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/* some broken boards return 0 or ~0 if a slot is empty: */
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000)
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return NULL;
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while (id == 0xffff0001)
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{
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delay(timeout/10);
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timeout *= 2;
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id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
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/* Card hasn't responded in 60 seconds? Must be stuck. */
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if (timeout > 60 * 100)
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{
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printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
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"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
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return NULL;
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}
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};
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if( pci_scan_filter(id, busnr, devfn) == 0)
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return NULL;
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hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
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dev = (pci_dev_t*)kzalloc(sizeof(pci_dev_t), 0);
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if(unlikely(dev == NULL))
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return NULL;
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INIT_LIST_HEAD(&dev->link);
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dev->pci_dev.busnr = busnr;
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dev->pci_dev.devfn = devfn;
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dev->pci_dev.hdr_type = hdr & 0x7f;
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dev->pci_dev.multifunction = !!(hdr & 0x80);
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dev->pci_dev.vendor = id & 0xffff;
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dev->pci_dev.device = (id >> 16) & 0xffff;
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pci_setup_device(&dev->pci_dev);
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return dev;
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};
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int _pci_scan_slot(u32 bus, int devfn)
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{
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int func, nr = 0;
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for (func = 0; func < 8; func++, devfn++)
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{
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pci_dev_t *dev;
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dev = pci_scan_device(bus, devfn);
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if( dev )
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{
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list_add(&dev->link, &devices);
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nr++;
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/*
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* If this is a single function device,
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* don't scan past the first function.
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*/
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if (!dev->pci_dev.multifunction)
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{
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if (func > 0) {
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dev->pci_dev.multifunction = 1;
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}
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else {
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break;
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}
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}
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}
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else {
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if (func == 0)
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break;
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}
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};
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return nr;
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};
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
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u8 pos, int cap, int *ttl)
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{
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u8 id;
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while ((*ttl)--) {
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pos = PciRead8(bus, devfn, pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
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u8 pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
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}
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static int __pci_bus_find_cap_start(unsigned int bus,
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unsigned int devfn, u8 hdr_type)
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{
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u16 status;
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status = PciRead16(bus, devfn, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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return PCI_CAPABILITY_LIST;
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case PCI_HEADER_TYPE_CARDBUS:
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return PCI_CB_CAPABILITY_LIST;
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default:
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return 0;
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}
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return 0;
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}
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int pci_find_capability(struct pci_dev *dev, int cap)
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{
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int pos;
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pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
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if (pos)
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pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
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return pos;
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}
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int enum_pci_devices()
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{
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pci_dev_t *dev;
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u32 last_bus;
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u32 bus = 0 , devfn = 0;
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last_bus = PciApi(1);
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if( unlikely(last_bus == -1))
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return -1;
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for(;bus <= last_bus; bus++)
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{
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for (devfn = 0; devfn < 0x100; devfn += 8)
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_pci_scan_slot(bus, devfn);
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}
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for(dev = (pci_dev_t*)devices.next;
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&dev->link != &devices;
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dev = (pci_dev_t*)dev->link.next)
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{
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dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
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dev->pci_dev.vendor,
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dev->pci_dev.device,
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dev->pci_dev.busnr,
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dev->pci_dev.devfn);
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}
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return 0;
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}
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const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
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{
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pci_dev_t *dev;
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const struct pci_device_id *ent;
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for(dev = (pci_dev_t*)devices.next;
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&dev->link != &devices;
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dev = (pci_dev_t*)dev->link.next)
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{
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if( dev->pci_dev.vendor != idlist->vendor )
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continue;
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for(ent = idlist; ent->vendor != 0; ent++)
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{
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if(unlikely(ent->device == dev->pci_dev.device))
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{
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pdev->pci_dev = dev->pci_dev;
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return ent;
|
|
}
|
|
};
|
|
}
|
|
|
|
return NULL;
|
|
};
|
|
|
|
struct pci_dev *
|
|
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
|
|
{
|
|
pci_dev_t *dev;
|
|
|
|
dev = (pci_dev_t*)devices.next;
|
|
|
|
if(from != NULL)
|
|
{
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( &dev->pci_dev == from)
|
|
{
|
|
dev = (pci_dev_t*)dev->link.next;
|
|
break;
|
|
};
|
|
}
|
|
};
|
|
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( dev->pci_dev.vendor != vendor )
|
|
continue;
|
|
|
|
if(dev->pci_dev.device == device)
|
|
{
|
|
return &dev->pci_dev;
|
|
}
|
|
}
|
|
return NULL;
|
|
};
|
|
|
|
|
|
struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
|
|
{
|
|
pci_dev_t *dev;
|
|
|
|
for(dev = (pci_dev_t*)devices.next;
|
|
&dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
|
|
return &dev->pci_dev;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
|
|
{
|
|
pci_dev_t *dev;
|
|
|
|
dev = (pci_dev_t*)devices.next;
|
|
|
|
if(from != NULL)
|
|
{
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( &dev->pci_dev == from)
|
|
{
|
|
dev = (pci_dev_t*)dev->link.next;
|
|
break;
|
|
};
|
|
}
|
|
};
|
|
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( dev->pci_dev.class == class)
|
|
{
|
|
return &dev->pci_dev;
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
|
|
#define PIO_OFFSET 0x10000UL
|
|
#define PIO_MASK 0x0ffffUL
|
|
#define PIO_RESERVED 0x40000UL
|
|
|
|
#define IO_COND(addr, is_pio, is_mmio) do { \
|
|
unsigned long port = (unsigned long __force)addr; \
|
|
if (port >= PIO_RESERVED) { \
|
|
is_mmio; \
|
|
} else if (port > PIO_OFFSET) { \
|
|
port &= PIO_MASK; \
|
|
is_pio; \
|
|
}; \
|
|
} while (0)
|
|
|
|
/* Create a virtual mapping cookie for an IO port range */
|
|
void __iomem *ioport_map(unsigned long port, unsigned int nr)
|
|
{
|
|
if (port > PIO_MASK)
|
|
return NULL;
|
|
return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
|
|
}
|
|
|
|
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
|
|
{
|
|
resource_size_t start = pci_resource_start(dev, bar);
|
|
resource_size_t len = pci_resource_len(dev, bar);
|
|
unsigned long flags = pci_resource_flags(dev, bar);
|
|
|
|
if (!len || !start)
|
|
return NULL;
|
|
if (maxlen && len > maxlen)
|
|
len = maxlen;
|
|
if (flags & IORESOURCE_IO)
|
|
return ioport_map(start, len);
|
|
if (flags & IORESOURCE_MEM) {
|
|
return ioremap(start, len);
|
|
}
|
|
/* What? */
|
|
return NULL;
|
|
}
|
|
|
|
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
|
|
{
|
|
IO_COND(addr, /* nothing */, iounmap(addr));
|
|
}
|
|
|
|
|
|
|
|
|
|
int pci_enable_rom(struct pci_dev *pdev)
|
|
{
|
|
struct resource *res = pdev->resource + PCI_ROM_RESOURCE;
|
|
struct pci_bus_region region;
|
|
u32 rom_addr;
|
|
|
|
if (!res->flags)
|
|
return -1;
|
|
|
|
_pcibios_resource_to_bus(pdev, ®ion, res);
|
|
pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
|
|
rom_addr &= ~PCI_ROM_ADDRESS_MASK;
|
|
rom_addr |= region.start | PCI_ROM_ADDRESS_ENABLE;
|
|
pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
|
|
return 0;
|
|
}
|
|
|
|
void pci_disable_rom(struct pci_dev *pdev)
|
|
{
|
|
u32 rom_addr;
|
|
pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_addr);
|
|
rom_addr &= ~PCI_ROM_ADDRESS_ENABLE;
|
|
pci_write_config_dword(pdev, pdev->rom_base_reg, rom_addr);
|
|
}
|
|
|
|
/**
|
|
* pci_get_rom_size - obtain the actual size of the ROM image
|
|
* @pdev: target PCI device
|
|
* @rom: kernel virtual pointer to image of ROM
|
|
* @size: size of PCI window
|
|
* return: size of actual ROM image
|
|
*
|
|
* Determine the actual length of the ROM image.
|
|
* The PCI window size could be much larger than the
|
|
* actual image size.
|
|
*/
|
|
size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
|
|
{
|
|
void __iomem *image;
|
|
int last_image;
|
|
|
|
image = rom;
|
|
do {
|
|
void __iomem *pds;
|
|
/* Standard PCI ROMs start out with these bytes 55 AA */
|
|
if (readb(image) != 0x55) {
|
|
dev_err(&pdev->dev, "Invalid ROM contents\n");
|
|
break;
|
|
}
|
|
if (readb(image + 1) != 0xAA)
|
|
break;
|
|
/* get the PCI data structure and check its signature */
|
|
pds = image + readw(image + 24);
|
|
if (readb(pds) != 'P')
|
|
break;
|
|
if (readb(pds + 1) != 'C')
|
|
break;
|
|
if (readb(pds + 2) != 'I')
|
|
break;
|
|
if (readb(pds + 3) != 'R')
|
|
break;
|
|
last_image = readb(pds + 21) & 0x80;
|
|
/* this length is reliable */
|
|
image += readw(pds + 16) * 512;
|
|
} while (!last_image);
|
|
|
|
/* never return a size larger than the PCI resource window */
|
|
/* there are known ROMs that get the size wrong */
|
|
return min((size_t)(image - rom), size);
|
|
}
|
|
|
|
|
|
/**
|
|
* pci_map_rom - map a PCI ROM to kernel space
|
|
* @pdev: pointer to pci device struct
|
|
* @size: pointer to receive size of pci window over ROM
|
|
*
|
|
* Return: kernel virtual pointer to image of ROM
|
|
*
|
|
* Map a PCI ROM into kernel space. If ROM is boot video ROM,
|
|
* the shadow BIOS copy will be returned instead of the
|
|
* actual ROM.
|
|
*/
|
|
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
|
|
{
|
|
struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
|
|
loff_t start;
|
|
void __iomem *rom;
|
|
|
|
/*
|
|
* IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
|
|
* memory map if the VGA enable bit of the Bridge Control register is
|
|
* set for embedded VGA.
|
|
*/
|
|
if (res->flags & IORESOURCE_ROM_SHADOW) {
|
|
/* primary video rom always starts here */
|
|
start = (loff_t)0xC0000;
|
|
*size = 0x20000; /* cover C000:0 through E000:0 */
|
|
} else {
|
|
if (res->flags &
|
|
(IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
|
|
*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
|
|
return (void __iomem *)(unsigned long)
|
|
pci_resource_start(pdev, PCI_ROM_RESOURCE);
|
|
} else {
|
|
start = (loff_t)0xC0000;
|
|
*size = 0x20000; /* cover C000:0 through E000:0 */
|
|
|
|
}
|
|
}
|
|
|
|
rom = ioremap(start, *size);
|
|
if (!rom) {
|
|
/* restore enable if ioremap fails */
|
|
if (!(res->flags & (IORESOURCE_ROM_ENABLE |
|
|
IORESOURCE_ROM_SHADOW |
|
|
IORESOURCE_ROM_COPY)))
|
|
pci_disable_rom(pdev);
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Try to find the true size of the ROM since sometimes the PCI window
|
|
* size is much larger than the actual size of the ROM.
|
|
* True size is important if the ROM is going to be copied.
|
|
*/
|
|
*size = pci_get_rom_size(pdev, rom, *size);
|
|
return rom;
|
|
}
|
|
|
|
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
|
|
{
|
|
struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
|
|
|
|
if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY))
|
|
return;
|
|
|
|
iounmap(rom);
|
|
|
|
/* Disable again before continuing, leave enabled if pci=rom */
|
|
if (!(res->flags & (IORESOURCE_ROM_ENABLE | IORESOURCE_ROM_SHADOW)))
|
|
pci_disable_rom(pdev);
|
|
}
|
|
|
|
static void __pci_set_master(struct pci_dev *dev, bool enable)
|
|
{
|
|
u16 old_cmd, cmd;
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
|
|
if (enable)
|
|
cmd = old_cmd | PCI_COMMAND_MASTER;
|
|
else
|
|
cmd = old_cmd & ~PCI_COMMAND_MASTER;
|
|
if (cmd != old_cmd) {
|
|
dbgprintf("%s bus mastering\n",
|
|
enable ? "enabling" : "disabling");
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
}
|
|
dev->is_busmaster = enable;
|
|
}
|
|
|
|
|
|
/* pci_set_master - enables bus-mastering for device dev
|
|
* @dev: the PCI device to enable
|
|
*
|
|
* Enables bus-mastering on the device and calls pcibios_set_master()
|
|
* to do the needed arch specific settings.
|
|
*/
|
|
void pci_set_master(struct pci_dev *dev)
|
|
{
|
|
__pci_set_master(dev, true);
|
|
// pcibios_set_master(dev);
|
|
}
|
|
|
|
/**
|
|
* pci_clear_master - disables bus-mastering for device dev
|
|
* @dev: the PCI device to disable
|
|
*/
|
|
void pci_clear_master(struct pci_dev *dev)
|
|
{
|
|
__pci_set_master(dev, false);
|
|
}
|
|
|
|
|
|
static inline int pcie_cap_version(const struct pci_dev *dev)
|
|
{
|
|
return dev->pcie_flags_reg & PCI_EXP_FLAGS_VERS;
|
|
}
|
|
|
|
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
|
|
{
|
|
int type = pci_pcie_type(dev);
|
|
|
|
return pcie_cap_version(dev) > 1 ||
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
type == PCI_EXP_TYPE_ENDPOINT ||
|
|
type == PCI_EXP_TYPE_LEG_END;
|
|
}
|
|
|
|
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
|
|
{
|
|
int type = pci_pcie_type(dev);
|
|
|
|
return pcie_cap_version(dev) > 1 ||
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
(type == PCI_EXP_TYPE_DOWNSTREAM &&
|
|
dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
|
|
}
|
|
|
|
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
|
|
{
|
|
int type = pci_pcie_type(dev);
|
|
|
|
return pcie_cap_version(dev) > 1 ||
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
type == PCI_EXP_TYPE_RC_EC;
|
|
}
|
|
|
|
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
|
|
{
|
|
if (!pci_is_pcie(dev))
|
|
return false;
|
|
|
|
switch (pos) {
|
|
case PCI_EXP_FLAGS_TYPE:
|
|
return true;
|
|
case PCI_EXP_DEVCAP:
|
|
case PCI_EXP_DEVCTL:
|
|
case PCI_EXP_DEVSTA:
|
|
return pcie_cap_has_devctl(dev);
|
|
case PCI_EXP_LNKCAP:
|
|
case PCI_EXP_LNKCTL:
|
|
case PCI_EXP_LNKSTA:
|
|
return pcie_cap_has_lnkctl(dev);
|
|
case PCI_EXP_SLTCAP:
|
|
case PCI_EXP_SLTCTL:
|
|
case PCI_EXP_SLTSTA:
|
|
return pcie_cap_has_sltctl(dev);
|
|
case PCI_EXP_RTCTL:
|
|
case PCI_EXP_RTCAP:
|
|
case PCI_EXP_RTSTA:
|
|
return pcie_cap_has_rtctl(dev);
|
|
case PCI_EXP_DEVCAP2:
|
|
case PCI_EXP_DEVCTL2:
|
|
case PCI_EXP_LNKCAP2:
|
|
case PCI_EXP_LNKCTL2:
|
|
case PCI_EXP_LNKSTA2:
|
|
return pcie_cap_version(dev) > 1;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Note that these accessor functions are only for the "PCI Express
|
|
* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
|
|
* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
|
|
*/
|
|
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
|
|
{
|
|
int ret;
|
|
|
|
*val = 0;
|
|
if (pos & 1)
|
|
return -EINVAL;
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
/*
|
|
* Reset *val to 0 if pci_read_config_word() fails, it may
|
|
* have been written as 0xFFFF if hardware error happens
|
|
* during pci_read_config_word().
|
|
*/
|
|
if (ret)
|
|
*val = 0;
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* For Functions that do not implement the Slot Capabilities,
|
|
* Slot Status, and Slot Control registers, these spaces must
|
|
* be hardwired to 0b, with the exception of the Presence Detect
|
|
* State bit in the Slot Status register of Downstream Ports,
|
|
* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
|
|
*/
|
|
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
|
|
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_read_word);
|
|
|
|
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
|
|
{
|
|
int ret;
|
|
|
|
*val = 0;
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
/*
|
|
* Reset *val to 0 if pci_read_config_dword() fails, it may
|
|
* have been written as 0xFFFFFFFF if hardware error happens
|
|
* during pci_read_config_dword().
|
|
*/
|
|
if (ret)
|
|
*val = 0;
|
|
return ret;
|
|
}
|
|
|
|
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
|
|
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_read_dword);
|
|
|
|
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
|
|
{
|
|
if (pos & 1)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_word);
|
|
|
|
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
|
|
{
|
|
if (pos & 3)
|
|
return -EINVAL;
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
return 0;
|
|
|
|
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
}
|
|
EXPORT_SYMBOL(pcie_capability_write_dword);
|
|
|
|
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
|
u16 clear, u16 set)
|
|
{
|
|
int ret;
|
|
u16 val;
|
|
|
|
ret = pcie_capability_read_word(dev, pos, &val);
|
|
if (!ret) {
|
|
val &= ~clear;
|
|
val |= set;
|
|
ret = pcie_capability_write_word(dev, pos, val);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
|
|
int pcie_get_readrq(struct pci_dev *dev)
|
|
{
|
|
u16 ctl;
|
|
|
|
pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
|
|
|
|
return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
|
|
}
|
|
EXPORT_SYMBOL(pcie_get_readrq);
|
|
|
|
/**
|
|
* pcie_set_readrq - set PCI Express maximum memory read request
|
|
* @dev: PCI device to query
|
|
* @rq: maximum memory read count in bytes
|
|
* valid values are 128, 256, 512, 1024, 2048, 4096
|
|
*
|
|
* If possible sets maximum memory read request in bytes
|
|
*/
|
|
int pcie_set_readrq(struct pci_dev *dev, int rq)
|
|
{
|
|
u16 v;
|
|
|
|
if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
|
|
return -EINVAL;
|
|
|
|
v = (ffs(rq) - 8) << 12;
|
|
|
|
return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
|
|
PCI_EXP_DEVCTL_READRQ, v);
|
|
}
|
|
|