forked from KolibriOS/kolibrios
314 lines
8.9 KiB
C++
314 lines
8.9 KiB
C++
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#include "r5xx_regs.h"
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#define RADEON_BUS_CNTL 0x0030
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# define RADEON_BUS_MASTER_DIS (1 << 6)
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#define RADEON_SCRATCH_UMSK 0x0770
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#define RADEON_SCRATCH_ADDR 0x0774
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#define RADEON_CP_ME_RAM_ADDR 0x07d4
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#define RADEON_CP_ME_RAM_RADDR 0x07d8
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#define RADEON_CP_ME_RAM_DATAH 0x07dc
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#define RADEON_CP_ME_RAM_DATAL 0x07e0
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#define RADEON_AIC_CNTL 0x01d0
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#define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
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#define RADEON_CP_RB_BASE 0x0700
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#define RADEON_CP_RB_CNTL 0x0704
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# define RADEON_BUF_SWAP_32BIT (2 << 16)
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# define RADEON_RB_NO_UPDATE (1 << 27)
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#define RADEON_CP_RB_RPTR_ADDR 0x070c
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#define RADEON_CP_RB_RPTR 0x0710
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#define RADEON_CP_RB_WPTR 0x0714
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#define RADEON_CP_RB_WPTR_DELAY 0x0718
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# define RADEON_PRE_WRITE_TIMER_SHIFT 0
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# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
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#define RADEON_CP_IB_BASE 0x0738
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#define RADEON_CP_CSQ_CNTL 0x0740
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# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
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# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
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# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
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# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
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# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
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# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
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# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
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#define RADEON_ISYNC_CNTL 0x1724
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# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
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# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
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# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
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# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
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# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
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# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
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#define R5XX_LOOP_COUNT 2000000
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#include "microcode.h"
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static Bool
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R5xxFIFOWaitLocal(CARD32 required) //R100-R500
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{
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int i;
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for (i = 0; i < R5XX_LOOP_COUNT; i++)
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if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
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return TRUE;
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dbgprintf("%s: Timeout 0x%08X.\n", __func__,
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(unsigned int) INREG(R5XX_RBBM_STATUS));
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return FALSE;
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}
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/*
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* Flush all dirty data in the Pixel Cache to memory.
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*/
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static Bool
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R5xx2DFlush()
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{
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int i;
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MASKREG(R5XX_DSTCACHE_CTLSTAT,
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R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);
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for (i = 0; i < R5XX_LOOP_COUNT; i++)
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if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
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return TRUE;
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dbgprintf("%s: Timeout 0x%08x.\n", __func__,
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(unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT));
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return FALSE;
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}
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static Bool
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R5xx2DIdleLocal() //R100-R500
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{
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int i;
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/* wait for fifo to clear */
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for (i = 0; i < R5XX_LOOP_COUNT; i++)
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if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
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break;
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if (i == R5XX_LOOP_COUNT) {
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dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
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return FALSE;
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}
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/* wait for engine to go idle */
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for (i = 0; i < R5XX_LOOP_COUNT; i++) {
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if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) {
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R5xx2DFlush();
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return TRUE;
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}
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}
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dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
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return FALSE;
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}
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static void
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R5xx2DReset()
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{
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CARD32 save, tmp;
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/* The following RBBM_SOFT_RESET sequence can help un-wedge
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* an R300 after the command processor got stuck. */
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save = INREG(R5XX_RBBM_SOFT_RESET);
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tmp = save | R5XX_SOFT_RESET_CP |
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R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE |
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R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP |
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R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB;
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OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
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INREG(R5XX_RBBM_SOFT_RESET);
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tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI |
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R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE |
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R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 |
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R5XX_SOFT_RESET_RB);
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OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
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INREG(R5XX_RBBM_SOFT_RESET);
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OUTREG(R5XX_RBBM_SOFT_RESET, save);
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INREG(R5XX_RBBM_SOFT_RESET);
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R5xx2DFlush();
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/* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
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* unexpected behaviour on some machines. Here we use
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* R5XX_HOST_PATH_CNTL to reset it. */
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save = INREG(R5XX_HOST_PATH_CNTL);
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tmp = INREG(R5XX_RBBM_SOFT_RESET);
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tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2;
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OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
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INREG(R5XX_RBBM_SOFT_RESET);
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OUTREG(R5XX_RBBM_SOFT_RESET, 0);
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MASKREG(R5XX_RB2D_DSTCACHE_MODE,
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R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE,
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R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE);
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OUTREG(R5XX_HOST_PATH_CNTL, save | R5XX_HDP_SOFT_RESET);
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INREG(R5XX_HOST_PATH_CNTL);
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OUTREG(R5XX_HOST_PATH_CNTL, save);
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}
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void
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R5xx2DSetup()
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{
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/* Setup engine location. This shouldn't be necessary since we
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* set them appropriately before any accel ops, but let's avoid
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* random bogus DMA in case we inadvertently trigger the engine
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* in the wrong place (happened). */
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R5xxFIFOWaitLocal(2);
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OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
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OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
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R5xxFIFOWaitLocal(1);
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MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
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OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
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R5xxFIFOWaitLocal(1);
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OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,
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R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX);
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R5xxFIFOWaitLocal(1);
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OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
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R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
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R5xxFIFOWaitLocal(5);
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OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
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OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);
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OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);
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OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000);
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OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
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R5xx2DIdleLocal();
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}
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void R5xxFIFOWait(CARD32 required)
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{
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if (!R5xxFIFOWaitLocal(required)) {
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R5xx2DReset();
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R5xx2DSetup();
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}
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}
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void R5xx2DIdle()
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{
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if (!R5xx2DIdleLocal()) {
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R5xx2DReset();
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R5xx2DSetup();
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}
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}
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static void load_microcode()
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{
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u32 ifl;
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int i;
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ifl = safe_cli();
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R5xx2DIdleLocal();
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OUTREG(RADEON_CP_ME_RAM_ADDR,0);
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for (i = 0; i < 256; i++)
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{
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OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
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OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
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}
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safe_sti(ifl);
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};
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void R5xx2DInit()
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{
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u32 base;
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rhd.displayWidth = INREG(D1GRPH_X_END);
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rhd.displayHeight = INREG(D1GRPH_Y_END);
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rhd.__xmin = 0;
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rhd.__ymin = 0;
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rhd.__xmax = rhd.displayWidth - 1;
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rhd.__ymax = rhd.displayHeight - 1;
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clip.xmin = 0;
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clip.ymin = 0;
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clip.xmax = rhd.displayWidth - 1;
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clip.ymax = rhd.displayHeight - 1;
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dbgprintf("width %d \n", rhd.displayWidth);
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dbgprintf("height %d \n", rhd.displayHeight);
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rhd.gui_control = (R5XX_DATATYPE_ARGB8888 << R5XX_GMC_DST_DATATYPE_SHIFT) |
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R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL;
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dbgprintf("gui_control %x \n", rhd.gui_control);
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rhd.surface_cntl = 0;
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rhd.dst_pitch_offset = (((rhd.displayWidth * 4) / 64) << 22) |
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((rhd.FbIntAddress + rhd.FbScanoutStart) >> 10);
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dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
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MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING);
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OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN);
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MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG);
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MASKREG(R5XX_RB2D_DSTCACHE_MODE,
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R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE,
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R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE);
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R5xx2DReset();
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R5xx2DSetup();
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MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN);
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load_microcode();
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rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE);
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dbgprintf("create cp ring buffer %x\n", rhd.ring_base);
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base = GetPgAddr(rhd.ring_base);
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OUTREG(RADEON_CP_RB_BASE, base);
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dbgprintf("ring base %x\n", base);
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OUTREG(RADEON_CP_RB_WPTR_DELAY, 0);
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rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
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OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp);
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OUTREG(RADEON_CP_RB_RPTR_ADDR, 0); // ring buffer read pointer no update
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OUTREG(RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE | 12);
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OUTREG(RADEON_SCRATCH_UMSK, 0); // no scratch update
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MASKREG(RADEON_BUS_CNTL,0,RADEON_BUS_MASTER_DIS);
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R5xx2DIdleLocal();
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OUTREG(RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D |
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RADEON_ISYNC_ANY3D_IDLE2D |
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RADEON_ISYNC_WAIT_IDLEGUI |
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RADEON_ISYNC_CPSCRATCH_IDLEGUI);
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OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); // run
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// OUTREG(D1CUR_SIZE, (31<<16)|31);
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// OUTREG(D1CUR_CONTROL, 0x300);
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}
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