forked from KolibriOS/kolibrios
653 lines
21 KiB
C
653 lines
21 KiB
C
/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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//#include <linux/device.h>
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include "intel_drv.h"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <errno-base.h>
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#include <linux/pci.h>
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#include <drm/drm_crtc_helper.h>
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#include <syscall.h>
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#define __read_mostly
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int init_display_kms(struct drm_device *dev);
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struct drm_device *main_device;
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static int i915_modeset __read_mostly = 1;
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MODULE_PARM_DESC(modeset,
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"Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
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"1=on, -1=force vga console preference [default])");
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int i915_panel_ignore_lid __read_mostly = 0;
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MODULE_PARM_DESC(panel_ignore_lid,
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"Override lid status (0=autodetect [default], 1=lid open, "
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"-1=lid closed)");
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unsigned int i915_powersave __read_mostly = 0;
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MODULE_PARM_DESC(powersave,
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"Enable powersavings, fbc, downclocking, etc. (default: true)");
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int i915_semaphores __read_mostly = -1;
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MODULE_PARM_DESC(semaphores,
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"Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
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int i915_enable_rc6 __read_mostly = 0;
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MODULE_PARM_DESC(i915_enable_rc6,
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"Enable power-saving render C-state 6. "
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"Different stages can be selected via bitmask values "
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"(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
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"For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
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"default: -1 (use per-chip default)");
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int i915_enable_fbc __read_mostly = 0;
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MODULE_PARM_DESC(i915_enable_fbc,
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"Enable frame buffer compression for power savings "
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"(default: -1 (use per-chip default))");
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unsigned int i915_lvds_downclock __read_mostly = 0;
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MODULE_PARM_DESC(lvds_downclock,
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"Use panel (LVDS/eDP) downclocking for power savings "
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"(default: false)");
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int i915_lvds_channel_mode __read_mostly;
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MODULE_PARM_DESC(lvds_channel_mode,
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"Specify LVDS channel mode "
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"(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
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int i915_panel_use_ssc __read_mostly = -1;
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MODULE_PARM_DESC(lvds_use_ssc,
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"Use Spread Spectrum Clock with panels [LVDS/eDP] "
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"(default: auto from VBT)");
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int i915_vbt_sdvo_panel_type __read_mostly = -1;
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MODULE_PARM_DESC(vbt_sdvo_panel_type,
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"Override/Ignore selection of SDVO panel mode in the VBT "
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"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
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static bool i915_try_reset __read_mostly = true;
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MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
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bool i915_enable_hangcheck __read_mostly = false;
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MODULE_PARM_DESC(enable_hangcheck,
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"Periodically check GPU activity for detecting hangs. "
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"WARNING: Disabling this can cause system wide hangs. "
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"(default: true)");
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int i915_enable_ppgtt __read_mostly = false;
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MODULE_PARM_DESC(i915_enable_ppgtt,
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"Enable PPGTT (default: true)");
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unsigned int i915_preliminary_hw_support __read_mostly = true;
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MODULE_PARM_DESC(preliminary_hw_support,
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"Enable preliminary hardware support. "
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"Enable Haswell and ValleyView Support. "
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"(default: false)");
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define INTEL_VGA_DEVICE(id, info) { \
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.class = PCI_BASE_CLASS_DISPLAY << 16, \
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.class_mask = 0xff0000, \
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.vendor = 0x8086, \
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.device = id, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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.driver_data = (unsigned long) info }
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static const struct intel_device_info intel_i915g_info = {
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.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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};
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static const struct intel_device_info intel_i915gm_info = {
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.gen = 3, .is_mobile = 1,
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.cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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};
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static const struct intel_device_info intel_i945g_info = {
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.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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};
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static const struct intel_device_info intel_i945gm_info = {
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.gen = 3, .is_i945gm = 1, .is_mobile = 1,
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.has_hotplug = 1, .cursor_needs_physical = 1,
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.has_overlay = 1, .overlay_needs_physical = 1,
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.supports_tv = 1,
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};
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static const struct intel_device_info intel_i965g_info = {
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.gen = 4, .is_broadwater = 1,
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.has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_i965gm_info = {
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.gen = 4, .is_crestline = 1,
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.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
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.has_overlay = 1,
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.supports_tv = 1,
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};
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static const struct intel_device_info intel_g33_info = {
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.gen = 3, .is_g33 = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_g45_info = {
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.gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
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.has_pipe_cxsr = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_gm45_info = {
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.gen = 4, .is_g4x = 1,
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.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
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.has_pipe_cxsr = 1, .has_hotplug = 1,
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.supports_tv = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_pineview_info = {
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.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_overlay = 1,
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};
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static const struct intel_device_info intel_ironlake_d_info = {
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.gen = 5,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_ironlake_m_info = {
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.gen = 5, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 1,
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.has_bsd_ring = 1,
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};
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static const struct intel_device_info intel_sandybridge_d_info = {
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.gen = 6,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_sandybridge_m_info = {
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.gen = 6, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_ivybridge_d_info = {
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.is_ivybridge = 1, .gen = 7,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_ivybridge_m_info = {
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.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_valleyview_m_info = {
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.gen = 7, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 0,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.is_valleyview = 1,
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};
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static const struct intel_device_info intel_valleyview_d_info = {
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.gen = 7,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_fbc = 0,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.is_valleyview = 1,
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};
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static const struct intel_device_info intel_haswell_d_info = {
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.is_haswell = 1, .gen = 7,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_force_wake = 1,
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};
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static const struct intel_device_info intel_haswell_m_info = {
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.is_haswell = 1, .gen = 7, .is_mobile = 1,
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.need_gfx_hws = 1, .has_hotplug = 1,
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.has_bsd_ring = 1,
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.has_blt_ring = 1,
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.has_llc = 1,
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.has_force_wake = 1,
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};
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static const struct pci_device_id pciidlist[] = { /* aka */
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INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
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INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
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INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
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INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
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INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
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INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
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INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
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INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
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INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
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INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
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INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
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INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
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INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
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INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
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INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
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INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
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INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
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INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
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INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
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INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
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INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
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INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
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INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
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INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
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INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
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INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
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INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
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INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
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INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
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INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
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INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
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INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
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INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
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INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
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INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
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INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
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INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
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INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
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INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
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INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
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INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
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INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
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INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
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INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
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INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
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INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
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INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
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INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
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INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
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INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
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INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
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INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
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INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
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INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
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INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
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INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
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INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
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INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
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INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
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INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
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INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
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INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
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INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
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INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
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INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
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INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
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{0, 0, 0}
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff00
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#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
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#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
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#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
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#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
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void intel_detect_pch(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct pci_dev *pch;
|
|
|
|
/*
|
|
* The reason to probe ISA bridge instead of Dev31:Fun0 is to
|
|
* make graphics device passthrough work easy for VMM, that only
|
|
* need to expose ISA bridge to let driver know the real hardware
|
|
* underneath. This is a requirement from virtualization team.
|
|
*/
|
|
pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
|
|
if (pch) {
|
|
if (pch->vendor == PCI_VENDOR_ID_INTEL) {
|
|
int id;
|
|
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
|
|
|
|
if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
|
|
dev_priv->pch_type = PCH_IBX;
|
|
dev_priv->num_pch_pll = 2;
|
|
DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
|
|
} else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
|
|
dev_priv->pch_type = PCH_CPT;
|
|
dev_priv->num_pch_pll = 2;
|
|
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
|
|
} else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
|
|
/* PantherPoint is CPT compatible */
|
|
dev_priv->pch_type = PCH_CPT;
|
|
dev_priv->num_pch_pll = 2;
|
|
DRM_DEBUG_KMS("Found PatherPoint PCH\n");
|
|
} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
|
|
dev_priv->pch_type = PCH_LPT;
|
|
dev_priv->num_pch_pll = 0;
|
|
DRM_DEBUG_KMS("Found LynxPoint PCH\n");
|
|
}
|
|
BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool i915_semaphore_is_enabled(struct drm_device *dev)
|
|
{
|
|
if (INTEL_INFO(dev)->gen < 6)
|
|
return 0;
|
|
|
|
if (i915_semaphores >= 0)
|
|
return i915_semaphores;
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
/* Enable semaphores on SNB when IO remapping is off */
|
|
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
|
|
return false;
|
|
#endif
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
|
|
|
|
int i915_init(void)
|
|
{
|
|
static pci_dev_t device;
|
|
const struct pci_device_id *ent;
|
|
int err;
|
|
|
|
ent = find_pci_device(&device, pciidlist);
|
|
if( unlikely(ent == NULL) )
|
|
{
|
|
dbgprintf("device not found\n");
|
|
return 0;
|
|
};
|
|
|
|
struct intel_device_info *intel_info =
|
|
(struct intel_device_info *) ent->driver_data;
|
|
|
|
if (intel_info->is_haswell || intel_info->is_valleyview)
|
|
if(!i915_preliminary_hw_support) {
|
|
DRM_ERROR("Preliminary hardware support disabled\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
|
|
device.pci_dev.device);
|
|
|
|
if (intel_info->gen != 3) {
|
|
|
|
} else if (init_agp() != 0) {
|
|
DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
err = drm_get_dev(&device.pci_dev, ent);
|
|
|
|
return err;
|
|
}
|
|
|
|
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct drm_device *dev;
|
|
int ret;
|
|
|
|
dev = kzalloc(sizeof(*dev), 0);
|
|
if (!dev)
|
|
return -ENOMEM;
|
|
|
|
// ret = pci_enable_device(pdev);
|
|
// if (ret)
|
|
// goto err_g1;
|
|
|
|
pci_set_master(pdev);
|
|
|
|
// if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
|
|
// printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
|
|
// goto err_g2;
|
|
// }
|
|
|
|
dev->pdev = pdev;
|
|
dev->pci_device = pdev->device;
|
|
dev->pci_vendor = pdev->vendor;
|
|
|
|
INIT_LIST_HEAD(&dev->filelist);
|
|
INIT_LIST_HEAD(&dev->ctxlist);
|
|
INIT_LIST_HEAD(&dev->vmalist);
|
|
INIT_LIST_HEAD(&dev->maplist);
|
|
|
|
spin_lock_init(&dev->count_lock);
|
|
mutex_init(&dev->struct_mutex);
|
|
mutex_init(&dev->ctxlist_mutex);
|
|
|
|
ret = i915_driver_load(dev, ent->driver_data );
|
|
|
|
if (ret)
|
|
goto err_g4;
|
|
|
|
ret = init_display_kms(dev);
|
|
|
|
if (ret)
|
|
goto err_g4;
|
|
|
|
return 0;
|
|
|
|
err_g4:
|
|
// drm_put_minor(&dev->primary);
|
|
//err_g3:
|
|
// if (drm_core_check_feature(dev, DRIVER_MODESET))
|
|
// drm_put_minor(&dev->control);
|
|
//err_g2:
|
|
// pci_disable_device(pdev);
|
|
//err_g1:
|
|
free(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* We give fast paths for the really cool registers */
|
|
#define NEEDS_FORCE_WAKE(dev_priv, reg) \
|
|
((HAS_FORCE_WAKE((dev_priv)->dev)) && \
|
|
((reg) < 0x40000) && \
|
|
((reg) != FORCEWAKE))
|
|
|
|
static bool IS_DISPLAYREG(u32 reg)
|
|
{
|
|
/*
|
|
* This should make it easier to transition modules over to the
|
|
* new register block scheme, since we can do it incrementally.
|
|
*/
|
|
if (reg >= VLV_DISPLAY_BASE)
|
|
return false;
|
|
|
|
if (reg >= RENDER_RING_BASE &&
|
|
reg < RENDER_RING_BASE + 0xff)
|
|
return false;
|
|
if (reg >= GEN6_BSD_RING_BASE &&
|
|
reg < GEN6_BSD_RING_BASE + 0xff)
|
|
return false;
|
|
if (reg >= BLT_RING_BASE &&
|
|
reg < BLT_RING_BASE + 0xff)
|
|
return false;
|
|
|
|
if (reg == PGTBL_ER)
|
|
return false;
|
|
|
|
if (reg >= IPEIR_I965 &&
|
|
reg < HWSTAM)
|
|
return false;
|
|
|
|
if (reg == MI_MODE)
|
|
return false;
|
|
|
|
if (reg == GFX_MODE_GEN7)
|
|
return false;
|
|
|
|
if (reg == RENDER_HWS_PGA_GEN7 ||
|
|
reg == BSD_HWS_PGA_GEN7 ||
|
|
reg == BLT_HWS_PGA_GEN7)
|
|
return false;
|
|
|
|
if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
|
|
reg == GEN6_BSD_RNCID)
|
|
return false;
|
|
|
|
if (reg == GEN6_BLITTER_ECOSKPD)
|
|
return false;
|
|
|
|
if (reg >= 0x4000c &&
|
|
reg <= 0x4002c)
|
|
return false;
|
|
|
|
if (reg >= 0x4f000 &&
|
|
reg <= 0x4f08f)
|
|
return false;
|
|
|
|
if (reg >= 0x4f100 &&
|
|
reg <= 0x4f11f)
|
|
return false;
|
|
|
|
if (reg >= VLV_MASTER_IER &&
|
|
reg <= GEN6_PMIER)
|
|
return false;
|
|
|
|
if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
|
|
reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
|
|
return false;
|
|
|
|
if (reg >= VLV_IIR_RW &&
|
|
reg <= VLV_ISR)
|
|
return false;
|
|
|
|
if (reg == FORCEWAKE_VLV ||
|
|
reg == FORCEWAKE_ACK_VLV)
|
|
return false;
|
|
|
|
if (reg == GEN6_GDRST)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
#define __i915_read(x, y) \
|
|
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
|
|
u##x val = 0; \
|
|
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
|
unsigned long irqflags; \
|
|
spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
|
|
if (dev_priv->forcewake_count == 0) \
|
|
dev_priv->gt.force_wake_get(dev_priv); \
|
|
val = read##y(dev_priv->regs + reg); \
|
|
if (dev_priv->forcewake_count == 0) \
|
|
dev_priv->gt.force_wake_put(dev_priv); \
|
|
spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
|
|
} else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
|
|
val = read##y(dev_priv->regs + reg + 0x180000); \
|
|
} else { \
|
|
val = read##y(dev_priv->regs + reg); \
|
|
} \
|
|
return val; \
|
|
}
|
|
|
|
__i915_read(8, b)
|
|
__i915_read(16, w)
|
|
__i915_read(32, l)
|
|
__i915_read(64, q)
|
|
#undef __i915_read
|
|
|
|
#define __i915_write(x, y) \
|
|
void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
|
|
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
|
|
__gen6_gt_wait_for_fifo(dev_priv); \
|
|
} \
|
|
write##y(val, dev_priv->regs + reg); \
|
|
}
|
|
__i915_write(8, b)
|
|
__i915_write(16, w)
|
|
__i915_write(32, l)
|
|
__i915_write(64, q)
|
|
#undef __i915_write
|