forked from KolibriOS/kolibrios
443 lines
13 KiB
C
443 lines
13 KiB
C
/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
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*/
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/irqreturn.h>
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//#include <linux/slab.h>
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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#define MAX_NOPID ((u32)~0)
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/**
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* Interrupts that are always left unmasked.
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*
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* Since pipe events are edge-triggered from the PIPESTAT register to IIR,
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* we leave them always unmasked in IMR and then control enabling them through
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* PIPESTAT alone.
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*/
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#define I915_INTERRUPT_ENABLE_FIX \
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(I915_ASLE_INTERRUPT | \
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
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/** Interrupts that we mask and unmask at runtime. */
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
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#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
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PIPE_VBLANK_INTERRUPT_STATUS)
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#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
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PIPE_VBLANK_INTERRUPT_ENABLE)
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#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
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DRM_I915_VBLANK_PIPE_B)
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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask & mask) != 0) {
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dev_priv->irq_mask &= ~mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask);
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POSTING_READ(DEIMR);
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}
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}
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static inline void
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ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask & mask) != mask) {
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dev_priv->irq_mask |= mask;
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I915_WRITE(DEIMR, dev_priv->irq_mask);
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POSTING_READ(DEIMR);
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}
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}
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static int ironlake_irq_handler(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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int ret = IRQ_NONE;
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u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
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u32 hotplug_mask;
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struct drm_i915_master_private *master_priv;
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u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
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atomic_inc(&dev_priv->irq_received);
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if (IS_GEN6(dev))
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bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
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/* disable master interrupt before clearing iir */
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de_ier = I915_READ(DEIER);
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I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
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POSTING_READ(DEIER);
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de_iir = I915_READ(DEIIR);
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gt_iir = I915_READ(GTIIR);
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pch_iir = I915_READ(SDEIIR);
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pm_iir = I915_READ(GEN6_PMIIR);
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if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
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(!IS_GEN6(dev) || pm_iir == 0))
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goto done;
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if (HAS_PCH_CPT(dev))
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hotplug_mask = SDE_HOTPLUG_MASK_CPT;
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else
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hotplug_mask = SDE_HOTPLUG_MASK;
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ret = IRQ_HANDLED;
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// if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
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// notify_ring(dev, &dev_priv->ring[RCS]);
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// if (gt_iir & bsd_usr_interrupt)
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// notify_ring(dev, &dev_priv->ring[VCS]);
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// if (gt_iir & GT_BLT_USER_INTERRUPT)
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// notify_ring(dev, &dev_priv->ring[BCS]);
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// if (de_iir & DE_GSE)
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// intel_opregion_gse_intr(dev);
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// if (de_iir & DE_PLANEA_FLIP_DONE) {
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// intel_prepare_page_flip(dev, 0);
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// intel_finish_page_flip_plane(dev, 0);
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// }
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// if (de_iir & DE_PLANEB_FLIP_DONE) {
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// intel_prepare_page_flip(dev, 1);
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// intel_finish_page_flip_plane(dev, 1);
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// }
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// if (de_iir & DE_PIPEA_VBLANK)
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// drm_handle_vblank(dev, 0);
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// if (de_iir & DE_PIPEB_VBLANK)
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// drm_handle_vblank(dev, 1);
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/* check event from PCH */
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// if (de_iir & DE_PCH_EVENT) {
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// if (pch_iir & hotplug_mask)
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// queue_work(dev_priv->wq, &dev_priv->hotplug_work);
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// pch_irq_handler(dev);
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// }
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// if (de_iir & DE_PCU_EVENT) {
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// I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
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// i915_handle_rps_change(dev);
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// }
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if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
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/*
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* IIR bits should never already be set because IMR should
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* prevent an interrupt from being shown in IIR. The warning
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* displays a case where we've unsafely cleared
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* dev_priv->pm_iir. Although missing an interrupt of the same
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* type is not a problem, it displays a problem in the logic.
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*
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* The mask bit in IMR is cleared by rps_work.
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*/
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->rps_lock, flags);
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WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
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dev_priv->pm_iir |= pm_iir;
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I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
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POSTING_READ(GEN6_PMIMR);
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spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
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// queue_work(dev_priv->wq, &dev_priv->rps_work);
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}
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/* should clear PCH hotplug event before clear CPU irq */
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I915_WRITE(SDEIIR, pch_iir);
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I915_WRITE(GTIIR, gt_iir);
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I915_WRITE(DEIIR, de_iir);
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I915_WRITE(GEN6_PMIIR, pm_iir);
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done:
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I915_WRITE(DEIER, de_ier);
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POSTING_READ(DEIER);
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return ret;
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}
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/* drm_dma.h hooks
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*/
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static void ironlake_irq_preinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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atomic_set(&dev_priv->irq_received, 0);
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// INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
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// INIT_WORK(&dev_priv->error_work, i915_error_work_func);
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// if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
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// INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
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I915_WRITE(HWSTAM, 0xeffe);
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if (IS_GEN6(dev)) {
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/* Workaround stalls observed on Sandy Bridge GPUs by
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* making the blitter command streamer generate a
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* write to the Hardware Status Page for
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* MI_USER_INTERRUPT. This appears to serialize the
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* previous seqno write out before the interrupt
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* happens.
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*/
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I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
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I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
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}
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/* XXX hotplug from PCH */
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I915_WRITE(DEIMR, 0xffffffff);
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I915_WRITE(DEIER, 0x0);
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POSTING_READ(DEIER);
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/* and GT */
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I915_WRITE(GTIMR, 0xffffffff);
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I915_WRITE(GTIER, 0x0);
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POSTING_READ(GTIER);
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/* south display irq */
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I915_WRITE(SDEIMR, 0xffffffff);
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I915_WRITE(SDEIER, 0x0);
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POSTING_READ(SDEIER);
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}
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/*
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* Enable digital hotplug on the PCH, and configure the DP short pulse
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* duration to 2ms (which is the minimum in the Display Port spec)
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*
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* This register is the same on all known PCH chips.
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*/
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static void ironlake_enable_pch_hotplug(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 hotplug;
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hotplug = I915_READ(PCH_PORT_HOTPLUG);
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hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
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hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
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hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
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hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
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I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
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}
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static int ironlake_irq_postinstall(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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/* enable kind of interrupts always enabled */
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u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
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DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
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u32 render_irqs;
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u32 hotplug_mask;
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// DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
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// if (HAS_BSD(dev))
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// DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
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// if (HAS_BLT(dev))
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// DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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dev_priv->irq_mask = ~display_mask;
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/* should always can generate irq */
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I915_WRITE(DEIIR, I915_READ(DEIIR));
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I915_WRITE(DEIMR, dev_priv->irq_mask);
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I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
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POSTING_READ(DEIER);
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dev_priv->gt_irq_mask = ~0;
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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if (IS_GEN6(dev))
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render_irqs =
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GT_USER_INTERRUPT |
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GT_GEN6_BSD_USER_INTERRUPT |
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GT_BLT_USER_INTERRUPT;
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else
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render_irqs =
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GT_USER_INTERRUPT |
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GT_PIPE_NOTIFY |
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GT_BSD_USER_INTERRUPT;
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I915_WRITE(GTIER, render_irqs);
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POSTING_READ(GTIER);
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if (HAS_PCH_CPT(dev)) {
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hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
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SDE_PORTB_HOTPLUG_CPT |
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SDE_PORTC_HOTPLUG_CPT |
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SDE_PORTD_HOTPLUG_CPT);
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} else {
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hotplug_mask = (SDE_CRT_HOTPLUG |
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SDE_PORTB_HOTPLUG |
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SDE_PORTC_HOTPLUG |
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SDE_PORTD_HOTPLUG |
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SDE_AUX_MASK);
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}
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dev_priv->pch_irq_mask = ~hotplug_mask;
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I915_WRITE(SDEIIR, I915_READ(SDEIIR));
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I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
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I915_WRITE(SDEIER, hotplug_mask);
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POSTING_READ(SDEIER);
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ironlake_enable_pch_hotplug(dev);
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if (IS_IRONLAKE_M(dev)) {
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/* Clear & enable PCU event interrupts */
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I915_WRITE(DEIIR, DE_PCU_EVENT);
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I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
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ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
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}
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return 0;
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}
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void intel_irq_init(struct drm_device *dev)
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{
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#if 0
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if (IS_IVYBRIDGE(dev)) {
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/* Share pre & uninstall handlers with ILK/SNB */
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dev->driver->irq_handler = ivybridge_irq_handler;
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dev->driver->irq_preinstall = ironlake_irq_preinstall;
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dev->driver->irq_postinstall = ivybridge_irq_postinstall;
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dev->driver->irq_uninstall = ironlake_irq_uninstall;
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dev->driver->enable_vblank = ivybridge_enable_vblank;
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dev->driver->disable_vblank = ivybridge_disable_vblank;
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} else if (HAS_PCH_SPLIT(dev)) {
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dev->driver->irq_handler = ironlake_irq_handler;
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dev->driver->irq_preinstall = ironlake_irq_preinstall;
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dev->driver->irq_postinstall = ironlake_irq_postinstall;
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dev->driver->irq_uninstall = ironlake_irq_uninstall;
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dev->driver->enable_vblank = ironlake_enable_vblank;
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dev->driver->disable_vblank = ironlake_disable_vblank;
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} else {
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dev->driver->irq_preinstall = i915_driver_irq_preinstall;
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dev->driver->irq_postinstall = i915_driver_irq_postinstall;
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dev->driver->irq_uninstall = i915_driver_irq_uninstall;
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dev->driver->irq_handler = i915_driver_irq_handler;
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dev->driver->enable_vblank = i915_enable_vblank;
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dev->driver->disable_vblank = i915_disable_vblank;
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}
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#endif
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}
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static struct drm_device *irq_device;
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void irq_handler_kms()
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{
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// printf("%s\n",__FUNCTION__);
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ironlake_irq_handler(irq_device);
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}
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int drm_irq_install(struct drm_device *dev)
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{
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int irq_line;
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int ret = 0;
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ENTER();
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mutex_lock(&dev->struct_mutex);
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/* Driver must have been initialized */
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if (!dev->dev_private) {
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mutex_unlock(&dev->struct_mutex);
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return -EINVAL;
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}
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if (dev->irq_enabled) {
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mutex_unlock(&dev->struct_mutex);
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return -EBUSY;
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}
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dev->irq_enabled = 1;
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mutex_unlock(&dev->struct_mutex);
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irq_device = dev;
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irq_line = drm_dev_to_irq(dev);
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DRM_DEBUG("irq=%d\n", drm_dev_to_irq(dev));
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ironlake_irq_preinstall(dev);
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ret = AttachIntHandler(irq_line, irq_handler_kms, 2);
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if (ret == 0) {
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mutex_lock(&dev->struct_mutex);
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dev->irq_enabled = 0;
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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ret = ironlake_irq_postinstall(dev);
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// if (ret < 0) {
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// mutex_lock(&dev->struct_mutex);
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// dev->irq_enabled = 0;
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// mutex_unlock(&dev->struct_mutex);
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// free_irq(drm_dev_to_irq(dev), dev);
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// }
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u16_t cmd = PciRead16(dev->pdev->busnr, dev->pdev->devfn, 4);
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cmd&= ~(1<<10);
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PciWrite16(dev->pdev->busnr, dev->pdev->devfn, 4, cmd);
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dbgprintf("PCI_CMD: %04x\n", cmd);
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DRM_INFO("i915: irq initialized.\n");
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LEAVE();
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return ret;
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}
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