forked from KolibriOS/kolibrios
379 lines
14 KiB
C
379 lines
14 KiB
C
/* Opcode table header for m680[01234]0/m6888[12]/m68851.
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
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2003, 2004, 2006, 2010 Free Software Foundation, Inc.
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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/* These are used as bit flags for the arch field in the m68k_opcode
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structure. */
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#define _m68k_undef 0
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#define m68000 0x001
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#define m68010 0x002
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#define m68020 0x004
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#define m68030 0x008
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#define m68040 0x010
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#define m68060 0x020
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#define m68881 0x040
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#define m68851 0x080
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#define cpu32 0x100 /* e.g., 68332 */
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#define fido_a 0x200
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#define m68k_mask 0x3ff
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#define mcfmac 0x400 /* ColdFire MAC. */
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#define mcfemac 0x800 /* ColdFire EMAC. */
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#define cfloat 0x1000 /* ColdFire FPU. */
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#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */
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#define mcfisa_a 0x4000 /* ColdFire ISA_A. */
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#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */
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#define mcfisa_b 0x10000 /* ColdFire ISA_B. */
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#define mcfisa_c 0x20000 /* ColdFire ISA_C. */
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#define mcfusp 0x40000 /* ColdFire USP instructions. */
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#define mcf_mask 0x7e400
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/* Handy aliases. */
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#define m68040up (m68040 | m68060)
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#define m68030up (m68030 | m68040up)
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#define m68020up (m68020 | m68030up)
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#define m68010up (m68010 | cpu32 | fido_a | m68020up)
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#define m68000up (m68000 | m68010up)
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#define mfloat (m68881 | m68040 | m68060)
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#define mmmu (m68851 | m68030 | m68040 | m68060)
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/* The structure used to hold information for an opcode. */
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struct m68k_opcode
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{
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/* The opcode name. */
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const char *name;
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/* The pseudo-size of the instruction(in bytes). Used to determine
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number of bytes necessary to disassemble the instruction. */
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unsigned int size;
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/* The opcode itself. */
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unsigned long opcode;
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/* The mask used by the disassembler. */
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unsigned long match;
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/* The arguments. */
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const char *args;
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/* The architectures which support this opcode. */
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unsigned int arch;
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};
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/* The structure used to hold information for an opcode alias. */
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struct m68k_opcode_alias
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{
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/* The alias name. */
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const char *alias;
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/* The instruction for which this is an alias. */
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const char *primary;
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};
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/* We store four bytes of opcode for all opcodes because that is the
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most any of them need. The actual length of an instruction is
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always at least 2 bytes, and is as much longer as necessary to hold
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the operands it has.
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The match field is a mask saying which bits must match particular
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opcode in order for an instruction to be an instance of that
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opcode.
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The args field is a string containing two characters for each
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operand of the instruction. The first specifies the kind of
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operand; the second, the place it is stored.
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If the first char of args is '.', it indicates that the opcode is
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two words. This is only necessary when the match field does not
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have any bits set in the second opcode word. Such a '.' is skipped
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for operand processing. */
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/* Kinds of operands:
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Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+-
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D data register only. Stored as 3 bits.
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A address register only. Stored as 3 bits.
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a address register indirect only. Stored as 3 bits.
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R either kind of register. Stored as 4 bits.
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r either kind of register indirect only. Stored as 4 bits.
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At the moment, used only for cas2 instruction.
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F floating point coprocessor register only. Stored as 3 bits.
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O an offset (or width): immediate data 0-31 or data register.
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Stored as 6 bits in special format for BF... insns.
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+ autoincrement only. Stored as 3 bits (number of the address register).
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- autodecrement only. Stored as 3 bits (number of the address register).
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Q quick immediate data. Stored as 3 bits.
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This matches an immediate operand only when value is in range 1 .. 8.
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M moveq immediate data. Stored as 8 bits.
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This matches an immediate operand only when value is in range -128..127
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T trap vector immediate data. Stored as 4 bits.
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k K-factor for fmove.p instruction. Stored as a 7-bit constant or
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a three bit register offset, depending on the field type.
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# immediate data. Stored in special places (b, w or l)
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which say how many bits to store.
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^ immediate data for floating point instructions. Special places
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are offset by 2 bytes from '#'...
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B pc-relative address, converted to an offset
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that is treated as immediate data.
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d displacement and register. Stores the register as 3 bits
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and stores the displacement in the entire second word.
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C the CCR. No need to store it; this is just for filtering validity.
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S the SR. No need to store, just as with CCR.
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U the USP. No need to store, just as with CCR.
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E the MAC ACC. No need to store, just as with CCR.
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e the EMAC ACC[0123].
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G the MAC/EMAC MACSR. No need to store, just as with CCR.
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g the EMAC ACCEXT{01,23}.
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H the MASK. No need to store, just as with CCR.
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i the MAC/EMAC scale factor.
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I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
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extracted from the 'd' field of word one, which means that an extended
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coprocessor opcode can be skipped using the 'i' place, if needed.
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s System Control register for the floating point coprocessor.
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J Misc register for movec instruction, stored in 'j' format.
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Possible values:
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0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
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0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
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0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
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0x003 TC MMU Translation Control [60, 40]
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0x004 ITT0 Instruction Transparent
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Translation reg 0 [60, 40]
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0x005 ITT1 Instruction Transparent
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Translation reg 1 [60, 40]
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0x006 DTT0 Data Transparent
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Translation reg 0 [60, 40]
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0x007 DTT1 Data Transparent
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Translation reg 1 [60, 40]
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0x008 BUSCR Bus Control Register [60]
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0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
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0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
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0x802 CAAR Cache Address Register [ 30, 20]
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0x803 MSP Master Stack Pointer [ 40, 30, 20]
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0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
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0x805 MMUSR MMU Status reg [ 40]
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0x806 URP User Root Pointer [60, 40]
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0x807 SRP Supervisor Root Pointer [60, 40]
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0x808 PCR Processor Configuration reg [60]
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0xC00 ROMBAR ROM Base Address Register [520X]
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0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
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0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
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0xC0F MBAR0 RAM Base Address Register 0 [520X]
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0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
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0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
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L Register list of the type d0-d7/a0-a7 etc.
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(New! Improved! Can also hold fp0-fp7, as well!)
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The assembler tries to see if the registers match the insn by
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looking at where the insn wants them stored.
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l Register list like L, but with all the bits reversed.
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Used for going the other way. . .
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c cache identifier which may be "nc" for no cache, "ic"
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for instruction cache, "dc" for data cache, or "bc"
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for both caches. Used in cinv and cpush. Always
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stored in position "d".
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u Any register, with ``upper'' or ``lower'' specification. Used
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in the mac instructions with size word.
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The remainder are all stored as 6 bits using an address mode and a
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register number; they differ in which addressing modes they match.
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* all (modes 0-6,7.0-4)
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~ alterable memory (modes 2-6,7.0,7.1)
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(not 0,1,7.2-4)
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% alterable (modes 0-6,7.0,7.1)
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(not 7.2-4)
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; data (modes 0,2-6,7.0-4)
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(not 1)
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@ data, but not immediate (modes 0,2-6,7.0-3)
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(not 1,7.4)
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! control (modes 2,5,6,7.0-3)
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(not 0,1,3,4,7.4)
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& alterable control (modes 2,5,6,7.0,7.1)
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(not 0,1,3,4,7.2-4)
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$ alterable data (modes 0,2-6,7.0,7.1)
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(not 1,7.2-4)
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? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
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(not 1,3,4,7.2-4)
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/ control, or data register (modes 0,2,5,6,7.0-3)
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(not 1,3,4,7.4)
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> *save operands (modes 2,4,5,6,7.0,7.1)
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(not 0,1,3,7.2-4)
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< *restore operands (modes 2,3,5,6,7.0-3)
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(not 0,1,4,7.4)
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coldfire move operands:
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m (modes 0-4)
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n (modes 5,7.2)
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o (modes 6,7.0,7.1,7.3,7.4)
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p (modes 0-5)
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coldfire bset/bclr/btst/mulsl/mulul operands:
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q (modes 0,2-5)
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v (modes 0,2-5,7.0,7.1)
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b (modes 0,2-5,7.2)
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w (modes 2-5,7.2)
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y (modes 2,5)
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z (modes 2,5,7.2)
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x mov3q immediate operand.
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j coprocessor ET operand.
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K coprocessor command number.
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4 (modes 2,3,4,5)
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*/
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/* For the 68851: */
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/* I didn't use much imagination in choosing the
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following codes, so many of them aren't very
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mnemonic. -rab
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0 32 bit pmmu register
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Possible values:
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000 TC Translation Control Register (68030, 68851)
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1 16 bit pmmu register
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111 AC Access Control (68851)
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2 8 bit pmmu register
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100 CAL Current Access Level (68851)
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101 VAL Validate Access Level (68851)
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110 SCC Stack Change Control (68851)
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3 68030-only pmmu registers (32 bit)
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010 TT0 Transparent Translation reg 0
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(aka Access Control reg 0 -- AC0 -- on 68ec030)
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011 TT1 Transparent Translation reg 1
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(aka Access Control reg 1 -- AC1 -- on 68ec030)
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W wide pmmu registers
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Possible values:
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001 DRP Dma Root Pointer (68851)
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010 SRP Supervisor Root Pointer (68030, 68851)
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011 CRP Cpu Root Pointer (68030, 68851)
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f function code register (68030, 68851)
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0 SFC
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1 DFC
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V VAL register only (68851)
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X BADx, BACx (16 bit)
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100 BAD Breakpoint Acknowledge Data (68851)
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101 BAC Breakpoint Acknowledge Control (68851)
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Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
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Z PCSR (68851)
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| memory (modes 2-6, 7.*)
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t address test level (68030 only)
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Stored as 3 bits, range 0-7.
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Also used for breakpoint instruction now.
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*/
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/* Places to put an operand, for non-general operands:
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Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
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s source, low bits of first word.
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d dest, shifted 9 in first word
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1 second word, shifted 12
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2 second word, shifted 6
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3 second word, shifted 0
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4 third word, shifted 12
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5 third word, shifted 6
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6 third word, shifted 0
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7 second word, shifted 7
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8 second word, shifted 10
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9 second word, shifted 5
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E second word, shifted 9
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D store in both place 1 and place 3; for divul and divsl.
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B first word, low byte, for branch displacements
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W second word (entire), for branch displacements
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L second and third words (entire), for branch displacements
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(also overloaded for move16)
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b second word, low byte
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w second word (entire) [variable word/long branch offset for dbra]
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W second word (entire) (must be signed 16 bit value)
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l second and third word (entire)
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g variable branch offset for bra and similar instructions.
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The place to store depends on the magnitude of offset.
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t store in both place 7 and place 8; for floating point operations
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c branch offset for cpBcc operations.
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The place to store is word two if bit six of word one is zero,
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and words two and three if bit six of word one is one.
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i Increment by two, to skip over coprocessor extended operands. Only
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works with the 'I' format.
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k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
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Also used for dynamic fmovem instruction.
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C floating point coprocessor constant - 7 bits. Also used for static
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K-factors...
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j Movec register #, stored in 12 low bits of second word.
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m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
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and remaining 3 bits of register shifted 9 bits in first word.
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Indicate upper/lower in 1 bit shifted 7 bits in second word.
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Use with `R' or `u' format.
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n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
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with MSB shifted 6 bits in first word and remaining 3 bits of
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register shifted 9 bits in first word. No upper/lower
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indication is done.) Use with `R' or `u' format.
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o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
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Indicate upper/lower in 1 bit shifted 7 bits in second word.
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Use with `R' or `u' format.
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M For M[S]ACw; 4 bits in low bits of first word. Indicate
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upper/lower in 1 bit shifted 6 bits in second word. Use with
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`R' or `u' format.
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N For M[S]ACw; 4 bits in low bits of second word. Indicate
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upper/lower in 1 bit shifted 6 bits in second word. Use with
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`R' or `u' format.
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h shift indicator (scale factor), 1 bit shifted 10 in second word
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Places to put operand, for general operands:
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d destination, shifted 6 bits in first word
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b source, at low bit of first word, and immediate uses one byte
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w source, at low bit of first word, and immediate uses two bytes
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l source, at low bit of first word, and immediate uses four bytes
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s source, at low bit of first word.
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Used sometimes in contexts where immediate is not allowed anyway.
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f single precision float, low bit of 1st word, immediate uses 4 bytes
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F double precision float, low bit of 1st word, immediate uses 8 bytes
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x extended precision float, low bit of 1st word, immediate uses 12 bytes
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p packed float, low bit of 1st word, immediate uses 12 bytes
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G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
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H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
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F EMAC ACCx
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f EMAC ACCy
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I MAC/EMAC scale factor
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/ Like 's', but set 2nd word, bit 5 if trailing_ampersand set
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] first word, bit 10
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*/
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extern const struct m68k_opcode m68k_opcodes[];
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extern const struct m68k_opcode_alias m68k_opcode_aliases[];
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extern const int m68k_numopcodes, m68k_numaliases;
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/* end of m68k-opcode.h */
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