forked from KolibriOS/kolibrios
627 lines
25 KiB
Plaintext
627 lines
25 KiB
Plaintext
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_____ __
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/ ___/__ __ ____ / /___ ___ ___ ___________________
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/ /__ / // // __// // _ \ / _ \/ -_) ___________________
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\___/ \_, / \__//_/ \___//_//_/\__/ ___________________
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/___/
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___________________ ____ ___ ___ ___ ___
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___________________ / __// _ \ / _ \ / _ \ / _ \
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___________________ / _ \/ _ // // // // // // /
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\___/\___/ \___/ \___/ \___/
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___________________________________________________________________________
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Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
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Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)
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This code is licensed under the GNU General Public License version 2.0 and the MAME License.
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You can choose the license that has the most advantages for you.
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Homepage: http://code.google.com/p/cyclone68000/
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___________________________________________________________________________
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About
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-----
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Cyclone 68000 is an emulator for the 68000 microprocessor, written in ARM 32-bit assembly.
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It is aimed at chips such as ARM7 and ARM9 cores, StrongARM and XScale, to interpret 68000
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code as fast as possible. It can emulate all 68000 instructions quite accurately, instruction
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timing was synchronized with MAME's Musashi. Most 68k features are emulated (trace mode,
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address errors), but prefetch is not emulated.
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How to Compile
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--------------
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Like Starscream and A68K, Cyclone uses a 'Core Creator' program which calculates and outputs
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all possible 68000 Opcodes and a jump table into file called Cyclone.s or Cyclone.asm.
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Only Cyclone.h and the mentioned .s or .asm file will be needed for your project, other files
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are here to produce or test it.
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First unzip "Cyclone.zip" into a "Cyclone" directory. The next thing to do is to edit config.h
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file to tune Cyclone for your project. There are lots of options in config.h, but all of them
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are documented and have defaults. You should set a define value to 1 to enable option, and
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to 0 to disable.
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After you are done with config.h, save it and compile Cyclone. If you are using Linux, Cygwin,
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mingw or similar, you can simply cd to Cyclone/proj and type "make". If you are under Windows
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and have Visual Studio installed, you can import cyclone.dsp in the proj/ directory and compile
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it from there (this will produce cyclone.exe which you will have to run to get .s or .asm).
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You can also use Microsoft command line compile tools by entering Cyclone/proj directory and
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typing "nmake -f Makefile.win". Note that this step is done only to produce .s or .asm, and it
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is done using native tools on your PC (not using cross-compiler or similar).
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The .s file is meant to be compiled with GNU assembler, and .asm with ARMASM.EXE
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(the Microsoft ARM assembler). Once you have the file, you can add it to your
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Makefile/project/whatever.
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Adding to your project
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----------------------
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Compiling the .s or .asm (from previous step) for your target platform may require custom
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build rules in your Makefile/project.
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If you use some gcc-based toolchain, you will need to add Cyclone.o to an object list in
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the Makefile. GNU make will use "as" to build Cyclone.o from Cyclone.s by default, so
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you may need to define correct cross-assembler by setting AS variable like this:
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AS = arm-linux-as
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This might be different in your case, basically it should be same prefix as for gcc.
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You may also need to specify floating point type in your assembler flags for Cyclone.o
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to link properly. This is done like this:
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ASFLAGS = -mfloat-abi=soft
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Note that Cyclone does not use floating points, this is just to make the linker happy.
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If you are using Visual Studio, you may need to add "custom build step", which creates
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Cyclone.obj from Cyclone.asm (asmasm.exe Cyclone.asm). Alternatively you can create
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Cyclone.obj by using armasm once and then just add it to you project.
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Don't worry if this seem very minimal - its all you need to run as many 68000s as you want.
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It works with both C and C++.
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Byteswapped Memory
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------------------
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If you have used Starscream, A68K or Turbo68K or similar emulators you'll be familiar with this!
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Any memory which the 68000 can access directly must be have every two bytes swapped around.
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This is to speed up 16-bit memory accesses, because the 68000 has Big-Endian memory
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and ARM has Little-Endian memory (in most cases).
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Now you may think you only technically have to byteswap ROM, not RAM, because
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16-bit RAM reads go through a memory handler and you could just return (mem[a]<<8) | mem[a+1].
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This would work, but remember some systems can execute code from RAM as well as ROM, and
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that would fail.
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So it's best to use byteswapped ROM and RAM if the 68000 can access it directly.
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It's also faster for the memory handlers, because you can do this:
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return *(unsigned short *)(mem+a)
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Declaring Memory handlers
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-------------------------
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Before you can reset or execute 68000 opcodes you must first set up a set of memory handlers.
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There are 7 functions you have to set up per CPU, like this:
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static unsigned int MyCheckPc(unsigned int pc)
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static unsigned char MyRead8 (unsigned int a)
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static unsigned short MyRead16 (unsigned int a)
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static unsigned int MyRead32 (unsigned int a)
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static void MyWrite8 (unsigned int a,unsigned char d)
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static void MyWrite16(unsigned int a,unsigned short d)
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static void MyWrite32(unsigned int a,unsigned int d)
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You can think of these functions representing the 68000's memory bus.
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The Read and Write functions are called whenever the 68000 reads or writes memory.
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For example you might set MyRead8 like this:
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unsigned char MyRead8(unsigned int a)
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{
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a&=0xffffff; // Clip address to 24-bits
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if (a<RomLength) return RomData[a^1]; // ^1 because the memory is byteswapped
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if (a>=0xe00000) return RamData[(a^1)&0xffff];
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return 0xff; // Out of range memory access
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}
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The other 5 read/write functions are similar. I'll describe the CheckPc function later on.
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Declaring a CPU Context
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-----------------------
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To declare a CPU simple declare a struct Cyclone in your code (don't forget to include Cyclone.h).
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For example to declare two 68000s:
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struct Cyclone MyCpu;
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struct Cyclone MyCpu2;
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It's probably a good idea to initialize the memory to zero:
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memset(&MyCpu, 0,sizeof(MyCpu));
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memset(&MyCpu2,0,sizeof(MyCpu2));
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Next point to your memory handlers:
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MyCpu.checkpc=MyCheckPc;
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MyCpu.read8 =MyRead8;
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MyCpu.read16 =MyRead16;
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MyCpu.read32 =MyRead32;
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MyCpu.write8 =MyWrite8;
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MyCpu.write16=MyWrite16;
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MyCpu.write32=MyWrite32;
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You also need to point the fetch handlers - for most systems out there you can just
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point them at the read handlers:
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MyCpu.fetch8 =MyRead8;
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MyCpu.fetch16 =MyRead16;
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MyCpu.fetch32 =MyRead32;
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( Why a different set of function pointers for fetch?
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Well there are some systems, the main one being CPS2, which return different data
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depending on whether the 'fetch' line on the 68000 bus is high or low.
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If this is the case, you can set up different functions for fetch reads.
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Generally though you don't need to. )
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Now you are nearly ready to reset the 68000, except a few more functions,
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one of them is: checkpc().
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The checkpc() function
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----------------------
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When Cyclone reads opcodes, it doesn't use a memory handler every time, this would be
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far too slow, instead it uses a direct pointer to ARM memory.
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For example if your Rom image was at 0x3000000 and the program counter was $206,
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Cyclone's program counter would be 0x3000206.
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The difference between an ARM address and a 68000 address is also stored in a variable called
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'membase'. In the above example it's 0x3000000. To retrieve the real 68k PC, Cyclone just
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subtracts 'membase'.
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When a long jump happens, Cyclone calls checkpc(). If the PC is in a different bank,
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for example Ram instead of Rom, change 'membase', recalculate the new PC and return it:
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static int MyCheckPc(unsigned int pc)
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{
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pc-=MyCpu.membase; // Get the real program counter
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if (pc<RomLength) MyCpu.membase=(int)RomMem; // Jump to Rom
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if (pc>=0xff0000) MyCpu.membase=(int)RamMem-0xff0000; // Jump to Ram
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return MyCpu.membase+pc; // New program counter
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}
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Notice that the membase is always ARM address minus 68000 address.
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The above example doesn't consider mirrored ram, but for an example of what to do see
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PicoDrive (in Memory.c).
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The exact cases when checkpc() is called can be configured in config.h.
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Initialization
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--------------
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Add a call to CycloneInit(). This is really only needed to be called once at startup
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if you enabled COMPRESS_JUMPTABLE in config.h, but you can add this in any case,
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it won't hurt.
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Almost there - Reset the 68000!
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-------------------------------
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Cyclone doesn't provide a reset function, so next we need to Reset the 68000 to get
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the initial Program Counter and Stack Pointer. This is obtained from addresses
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000000 and 000004.
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Here is code which resets the 68000 (using your memory handlers):
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MyCpu.state_flags=0; // Go to default state (not stopped, halted, etc.)
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MyCpu.srh=0x27; // Set supervisor mode
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MyCpu.a[7]=MyCpu.read32(0); // Get Stack Pointer
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MyCpu.membase=0; // Will be set by checkpc()
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MyCpu.pc=MyCpu.checkpc(MyCpu.read32(4)); // Get Program Counter
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And that's ready to go.
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Executing the 68000
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-------------------
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To execute the 68000, set the 'cycles' variable to the number of cycles you wish to execute,
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and then call CycloneRun with a pointer to the Cyclone structure.
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e.g.:
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// Execute 1000 cycles on the 68000:
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MyCpu.cycles=1000; CycloneRun(&MyCpu);
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For each opcode, the number of cycles it took is subtracted and the function returns when
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it reaches negative number. The result is stored back to MyCpu.cycles.
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e.g.
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// Execute one instruction on the 68000:
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MyCpu.cycles=0; CycloneRun(&MyCpu);
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printf(" The opcode took %d cycles\n", -MyCpu.cycles);
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You should try to execute as many cycles as you can for maximum speed.
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The number actually executed may be slightly more than requested, i.e. cycles may come
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out with a small negative value:
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e.g.
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int todo=12000000/60; // 12Mhz, for one 60hz frame
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MyCpu.cycles=todo; CycloneRun(&MyCpu);
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printf(" Actually executed %d cycles\n", todo-MyCpu.cycles);
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To calculate the number of cycles executed, use this formula:
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Number of cycles requested - Cycle counter at the end
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Interrupts
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----------
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Causing an interrupt is very simple, simply set the irq variable in the Cyclone structure
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to the IRQ number.
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To lower the IRQ line, set it to zero.
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e.g:
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MyCpu.irq=6; // Interrupt level 6
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MyCpu.cycles=20000; CycloneRun(&MyCpu);
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Note that the interrupt is not actually processed until the next call to CycloneRun,
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and the interrupt may not be taken until the 68000 interrupt mask is changed to allow it.
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If you need to force interrupt processing, you can use CycloneFlushIrq() function.
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It is the same as doing
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MyCpu.cycles=0; CycloneRun(&MyCpu);
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but is better optimized and doesn't update .cycles (returns them instead).
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This function can't be used from memory handlers and has no effect if interrupt is masked.
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The IRQ isn't checked on exiting from a memory handler. If you need to cause interrupt
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check immediately, you should change cycle counter to 0 to cause a return from CycloneRun(),
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and then call CycloneRun() again or just call CycloneFlushIrq(). Note that you need to
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enable MEMHANDLERS_CHANGE_CYCLES in config.h for this to work.
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If you need to do something during the interrupt acknowledge (the moment when interrupt
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is taken), you can set USE_INT_ACK_CALLBACK in config.h and specify IrqCallback function.
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This function should update the IRQ level (.irq variable in context) and return the
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interrupt vector number. But for most cases it should return special constant
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CYCLONE_INT_ACK_AUTOVECTOR so that Cyclone uses autovectors, which is what most real
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systems were doing. Another less commonly used option is to return CYCLONE_INT_ACK_SPURIOUS
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for spurious interrupt.
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Accessing Program Counter and registers
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---------------------------------------
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You can read most Cyclone's registers directly from the structure at any time.
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However, the PC value, CCR and cycle counter are cached in ARM registers and can't
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be accessed from memory handlers by default. They are written back and can be
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accessed after execution.
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But if you need to access the mentioned registers during execution, you can set
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MEMHANDLERS_NEED_* and MEMHANDLERS_CHANGE_* options in config.h
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The Program Counter, should you need to read or write it, is stored with membase
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added on. So use this formula to calculate the real 68000 program counter:
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pc = MyCpu.pc - MyCpu.membase;
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For performance reasons Cyclone keeps the status register split into .srh
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(status register "high" supervisor byte), .xc for the X flag, and .flags for remaining
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CCR flags (in ARM order). To easily read/write the status register as normal 68k
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16bit SR register, use CycloneGetSr() and CycloneSetSr() utility functions.
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Emulating more than one CPU
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---------------------------
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Since everything is based on the structures, emulating more than one cpu at the same time
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is just a matter of declaring more than one structures and timeslicing. You can emulate
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as many 68000s as you want.
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Just set up the memory handlers for each cpu and run each cpu for a certain number of cycles.
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e.g.
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// Execute 1000 cycles on 68000 #1:
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MyCpu.cycles=1000; CycloneRun(&MyCpu);
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// Execute 1000 cycles on 68000 #2:
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MyCpu2.cycles=1000; CycloneRun(&MyCpu2);
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Quick API reference
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-------------------
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void CycloneInit(void);
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Initializes Cyclone. Must be called if the jumptable is compressed,
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doesn't matter otherwise.
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void CycloneRun(struct Cyclone *pcy);
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Runs cyclone for pcy->cycles. Writes amount of cycles left back to
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pcy->cycles (always negative).
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unsigned int CycloneGetSr(const struct Cyclone *pcy);
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Reads status register in internal form from pcy, converts to standard 68k SR and returns it.
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void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);
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Takes standard 68k status register (sr), and updates Cyclone context with it.
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int CycloneFlushIrq(struct Cyclone *pcy);
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If .irq is greater than IRQ mask in SR, or it is equal to 7 (NMI), processes interrupt
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exception and returns number of cycles used. Otherwise, does nothing and returns 0.
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void CyclonePack(const struct Cyclone *pcy, void *save_buffer);
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Writes Cyclone state to save_buffer. This allows to avoid all the trouble figuring what
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actually needs to be saved from the Cyclone structure, as saving whole struct Cyclone
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to a file will also save various pointers, which may become invalid after your program
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is restarted, so simply reloading the structure will cause a crash. save_buffer size
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should be 128 bytes (now it is really using less, but this allows future expansion).
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void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);
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Reloads Cyclone state from save_buffer, which was previously saved by CyclonePack().
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This function uses checkpc() callback to rebase the PC, so .checkpc must be initialized
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before calling it.
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Callbacks:
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.checkpc
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unsigned int (*checkpc)(unsigned int pc);
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This function is called when PC changes are performed in 68k code or because of exceptions.
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It is passed ARM pointer and should return ARM pointer casted to int. It must also update
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.membase if needed. See "The checkpc() function" section above.
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unsigned int (*read8 )(unsigned int a);
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unsigned int (*read16 )(unsigned int a);
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unsigned int (*read32 )(unsigned int a);
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These are the read memory handler callbacks. They are called when 68k code reads from memory.
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The parameter is a 68k address in data space, return value is a data value read. Data value
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doesn't have to be masked to 8 or 16 bits for read8 or read16, Cyclone will do that itself
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if needed.
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unsigned int (*fetch8 )(unsigned int a);
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unsigned int (*fetch16)(unsigned int a);
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unsigned int (*fetch32)(unsigned int a);
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Same as above, but these are reads from program space (PC relative reads mostly).
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void (*write8 )(unsigned int a,unsigned char d);
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void (*write16)(unsigned int a,unsigned short d);
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void (*write32)(unsigned int a,unsigned int d);
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These are called when 68k code writes to data space. d is the data value.
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int (*IrqCallback)(int int_level);
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This function is called when Cyclone acknowledges an interrupt. The parameter is the IRQ
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level being acknowledged, and return value is exception vector to use, or one of these special
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values: CYCLONE_INT_ACK_AUTOVECTOR or CYCLONE_INT_ACK_SPURIOUS. Can be disabled in config.h.
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See "Interrupts" section for more information.
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void (*ResetCallback)(void);
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Cyclone will call this function if it encounters RESET 68k instruction.
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Can be disabled in config.h.
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int (*UnrecognizedCallback)(void);
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Cyclone will call this function if it encounters illegal instructions (including A-line and
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F-line ones). Can be tuned / disabled in config.h.
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Function codes
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--------------
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Cyclone doesn't pass function codes to it's memory handlers, but they can be calculated:
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FC2: just use supervisor state bit from status register (eg. (MyCpu.srh & 0x20) >> 5)
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FC1: if we are in fetch* function, then 1, else 0.
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FC0: if we are in read* or write*, then 1, else 0.
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CPU state (all FC bits set) is active in IrqCallback function.
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References
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----------
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These documents were used while writing Cyclone and should be useful for those who want to
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understand deeper how the 68000 works.
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MOTOROLA M68000 FAMILY Programmer's Reference Manual
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common name: 68kPM.pdf
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M68000 8-/16-/32-Bit Microprocessors User's Manual
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common name: MC68000UM.pdf
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68000 Undocumented Behavior Notes by Bart Trzynadlowski
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http://www.trzy.org/files/68knotes.txt
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Instruction prefetch on the Motorola 68000 processor by Jorge Cwik
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http://pasti.fxatari.com/68kdocs/68kPrefetch.html
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ARM Register Usage
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------------------
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See source code for up to date of register usage, however a summary is here:
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r0-3: Temporary registers
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r4 : Current PC + Memory Base (i.e. pointer to next opcode)
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r5 : Cycles remaining
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r6 : Pointer to Opcode Jump table
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r7 : Pointer to Cpu Context
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r8 : Current Opcode
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r10 : Flags (NZCV) in highest four bits
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(r11 : Temporary register)
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Flags are mapped onto ARM flags whenever possible, which speeds up the processing of opcode.
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r9 is not used intentionally, because AAPCS defines it as "platform register", so it's
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reserved in some systems.
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Thanks to...
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------------
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* All the previous code-generating assembler cpu core guys!
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Who are iirc... Neill Corlett, Neil Bradley, Mike Coates, Darren Olafson
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Karl Stenerud and Bart Trzynadlowski
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* Charles Macdonald, for researching just about every console ever
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* MameDev+FBA, for keeping on going and going and going
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What's New
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----------
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v0.0099
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* Cyclone no longer uses r9, because AAPCS defines it as "platform register",
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so it's reserved in some systems.
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* Made SPLIT_MOVEL_PD to affect MOVEM too.
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v0.0088
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- Reduced amount of code in opcode handlers by ~23% by doing the following:
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- Removed duplicate opcode handlers
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- Optimized code to use less ARM instructions
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- Merged some duplicate handler endings
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+ Cyclone now does better job avoiding pipeline interlocks.
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+ Replaced incorrect handler of DBT with proper one.
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+ Changed "MOVEA (An)+ An" behavior.
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+ Fixed flag behavior of ROXR, ASL, LSR and NBCD in certain situations.
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Hopefully got them right now.
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+ Cyclone no longer sets most significant bits while pushing PC to stack.
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Amiga Kickstart depends on this.
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+ Added optional trace mode emulation.
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+ Added optional address error emulation.
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+ Additional functionality added for MAME and other ports (see config.h).
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+ Added return value for IrqCallback to make it suitable for emulating devices which
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pass the vector number during interrupt acknowledge cycle. For usual autovector
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processing this function must return CYCLONE_INT_ACK_AUTOVECTOR, so those who are
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upgrading must add "return CYCLONE_INT_ACK_AUTOVECTOR;" to their IrqCallback functions.
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* Updated documentation.
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v0.0086
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+ Cyclone now can be customized to better suit your project, see config.h .
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+ Added an option to compress the jumptable at compile-time. Must call CycloneInit()
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at runtime to decompress it if enabled (see config.h).
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+ Added missing CHK opcode handler (used by SeaQuest DSV).
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+ Added missing TAS opcode handler (Gargoyles,Bubba N Stix,...). As in real genesis,
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memory write-back phase is ignored (but can be enabled in config.h if needed).
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+ Added missing NBCD and TRAPV opcode handlers.
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+ Added missing addressing mode for CMP/EOR.
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+ Added some minor optimizations.
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- Removed 216 handlers for 2927 opcodes which were generated for invalid addressing modes.
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+ Fixed flags for ASL, NEG, NEGX, DIVU, ADDX, SUBX, ROXR.
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+ Bugs fixed in MOVEP, LINK, ADDQ, DIVS handlers.
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* Undocumented flags for CHK, ABCD, SBCD and NBCD are now emulated the same way as in Musashi.
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+ Added Uninitialized Interrupt emulation.
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+ Altered timing for about half of opcodes to match Musashi's.
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v0.0082
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+ Change cyclone to clear cycles before returning when halted
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+ Added Irq call back function. This allows emulators to be notified
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when cyclone has taken an interrupt allowing them to set internal flags
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which can help fix timing problems.
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v0.0081
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+ .asm version was broken and did not compile with armasm. Fixed.
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+ Finished implementing Stop opcode. Now it really stops the processor.
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v0.0080
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+ Added real cmpm opcode, it was using eor handler before this.
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Fixes Dune and Sensible Soccer.
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v0.0078
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note: these bugs were actually found Reesy, I reimplemented these by
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using his changelog as a guide.
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+ Fixed a problem with divu which was using long divisor instead of word.
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Fixes gear switching in Top Gear 2.
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+ Fixed btst opcode, The bit to test should shifted a max of 31 or 7
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depending on if a register or memory location is being tested.
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+ Fixed abcd,sbcd. They did bad decimal correction on invalid BCD numbers
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Score counters in Streets of Rage level end work now.
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+ Changed flag handling of abcd,sbcd,addx,subx,asl,lsl,...
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Some ops did not have flag handling at all.
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Some ops must not change Z flag when result is zero, but they did.
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Shift ops must not change X if shift count is zero, but they did.
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There are probably still some flag problems left.
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+ Patially implemented Stop and Reset opcodes - Fixes Thunderforce IV
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v0.0075
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+ Added missing displacement addressing mode for movem (Fantastic Dizzy)
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+ Added OSP <-> A7 swapping code in opcodes, which change privilege mode
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+ Implemented privilege violation, line emulator and divide by zero exceptions
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+ Added negx opcode (Shining Force works!)
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+ Added overflow detection for divs/divu
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v0.0072
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note: I could only get v0.0069 cyclone, so I had to implement these myself using Dave's
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changelog as a guide.
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+ Fixed a problem with divs - remainder should be negative when divident is negative
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+ Added movep opcode (Sonic 3 works)
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+ Fixed a problem with DBcc incorrectly decrementing if the condition is true (Shadow of the Beast)
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v0.0069
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+ Added SBCD and the flags for ABCD/SBCD. Score and time now works in games such as
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Rolling Thunder 2, Ghouls 'N Ghosts
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+ Fixed a problem with addx and subx with 8-bit and 16-bit values.
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Ghouls 'N' Ghosts now works!
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v0.0068
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+ Added ABCD opcode (Streets of Rage works now!)
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v0.0067
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+ Added dbCC (After Burner)
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+ Added asr EA (Sonic 1 Boss/Labyrinth Zone)
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+ Added andi/ori/eori ccr (Altered Beast)
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+ Added trap (After Burner)
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+ Added special case for move.b (a7)+ and -(a7), stepping by 2
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After Burner is playable! Eternal Champions shows more
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+ Fixed lsr.b/w zero flag (Ghostbusters)
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Rolling Thunder 2 now works!
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+ Fixed N flag for .b and .w arithmetic. Golden Axe works!
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v0.0066
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+ Fixed a stupid typo for exg (orr r10,r10, not orr r10,r8), which caused alignment
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crashes on Strider
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v0.0065
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+ Fixed a problem with immediate values - they weren't being shifted up correctly for some
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opcodes. Spiderman works, After Burner shows a bit of graphics.
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+ Fixed a problem with EA:"110nnn" extension word. 32-bit offsets were being decoded as 8-bit
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offsets by mistake. Castlevania Bloodlines seems fine now.
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+ Added exg opcode
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+ Fixed asr opcode (Sonic jumping left is fixed)
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+ Fixed a problem with the carry bit in rol.b (Marble Madness)
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v0.0064
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+ Added rtr
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+ Fixed addq/subq.l (all An opcodes are 32-bit) (Road Rash)
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+ Fixed various little timings
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v0.0063
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+ Added link/unlk opcodes
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+ Fixed various little timings
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+ Fixed a problem with dbCC opcode being emitted at set opcodes
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+ Improved long register access, the EA fetch now does ldr r0,[r7,r0,lsl #2] whenever
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possible, saving 1 or 2 cycles on many opcodes, which should give a nice speed up.
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+ May have fixed N flag on ext opcode?
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+ Added dasm for link opcode.
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v0.0062
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* I was a bit too keen with the Arithmetic opcodes! Some of them should have been abcd,
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exg and addx. Removed the incorrect opcodes, pending re-adding them as abcd, exg and addx.
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+ Changed unknown opcodes to act as nops.
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Not very technical, but fun - a few more games show more graphics ;)
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v0.0060
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+ Fixed divu (EA intro)
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+ Added sf (set false) opcode - SOR2
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* Todo: pea/link/unlk opcodes
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v0.0059: Added remainder to divide opcodes.
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