aabc2/KOS_qrcodes
1
0
Fork 0
forked from KolibriOS/kolibrios
Code Pull Requests Activity

binutils-2.26

Browse Source 
git-svn-id: svn://kolibrios.org@6324 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
2016-03-12 03:07:23 +00:00
parent d818239c29
commit 3b53803119
572 changed files with 128744 additions and 64154 deletions
Download Patch File Download Diff File Expand all files Collapse all files

272
contrib/toolchain/binutils/include/opcode/mips.h
View File

@@ -1,7 +1,5 @@
/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003, 2004, 2005, 2008, 2009, 2010, 2013
Free Software Foundation, Inc.
Copyright (C) 1993-2015 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -413,7 +411,23 @@ enum mips_operand_type {
/* Like OP_VU0_SUFFIX, but used when the operand's value has already
been set. Any suffix used here must match the previous value. */
OP_VU0_MATCH_SUFFIX
OP_VU0_MATCH_SUFFIX,
/* An index selected by an integer, e.g. [1]. */
OP_IMM_INDEX,
/* An index selected by a register, e.g. [$2]. */
OP_REG_INDEX,
/* The operand spans two 5-bit register fields, both of which must be set to
the source register. */
OP_SAME_RS_RT,
/* Described by mips_prev_operand. */
OP_CHECK_PREV,
/* A register operand that must not be zero. */
OP_NON_ZERO_REG
};
/* Enumerates the types of MIPS register. */
@@ -454,7 +468,13 @@ enum mips_reg_operand_type {
OP_REG_R5900_I,
OP_REG_R5900_Q,
OP_REG_R5900_R,
OP_REG_R5900_ACC
OP_REG_R5900_ACC,
/* MSA registers $w0-$w31. */
OP_REG_MSA,
/* MSA control registers $0-$31. */
OP_REG_MSA_CTRL
};
/* Base class for all operands. */
@@ -543,6 +563,18 @@ struct mips_reg_operand
const unsigned char *reg_map;
};
/* Describes an operand that which must match a condition based on the
previous operand. */
struct mips_check_prev_operand
{
struct mips_operand root;
bfd_boolean greater_than_ok;
bfd_boolean less_than_ok;
bfd_boolean equal_ok;
bfd_boolean zero_ok;
};
/* Describes an operand that encodes a pair of registers. */
struct mips_reg_pair_operand
{
@@ -891,6 +923,54 @@ struct mips_opcode
Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
MSA Extension:
"+d" 5-bit MSA register (FD)
"+e" 5-bit MSA register (FS)
"+h" 5-bit MSA register (FT)
"+k" 5-bit GPR at bit 6
"+l" 5-bit MSA control register at bit 6
"+n" 5-bit MSA control register at bit 11
"+o" 4-bit vector element index at bit 16
"+u" 3-bit vector element index at bit 16
"+v" 2-bit vector element index at bit 16
"+w" 1-bit vector element index at bit 16
"+T" (-512 .. 511) << 0 at bit 16
"+U" (-512 .. 511) << 1 at bit 16
"+V" (-512 .. 511) << 2 at bit 16
"+W" (-512 .. 511) << 3 at bit 16
"+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
"+!" 3 bit unsigned bit position at bit 16
"+@" 4 bit unsigned bit position at bit 16
"+#" 6 bit unsigned bit position at bit 16
"+$" 5 bit unsigned immediate at bit 16
"+%" 5 bit signed immediate at bit 16
"+^" 10 bit signed immediate at bit 11
"+&" 0 vector element index
"+*" 5-bit register vector element index at bit 16
"+|" 8-bit mask at bit 16
MIPS R6:
"+:" 11-bit mask at bit 0
"+'" 26 bit PC relative branch target address
"+"" 21 bit PC relative branch target address
"+;" 5 bit same register in both OP_*_RS and OP_*_RT
"+I" 2bit unsigned bit position at bit 6
"+O" 3bit unsigned bit position at bit 6
"+R" must be program counter
"-a" (-262144 .. 262143) << 2 at bit 0
"-b" (-131072 .. 131071) << 3 at bit 0
"-d" Same as destination register GP
"-s" 5 bit source register specifier (OP_*_RS) not $0
"-t" 5 bit source register specifier (OP_*_RT) not $0
"-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS
"-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS
"-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS
"-x" 5 bit source register specifier (OP_*_RT) greater than or
equal to OP_*_RS
"-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS
"-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
"-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
Other:
"()" parens surrounding optional value
"," separates operands
@@ -898,15 +978,21 @@ struct mips_opcode
Characters used so far, for quick reference when adding more:
"1234567890"
"%[]<>(),+:'@!#$*&\~"
"%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234567890"
"ABCEFGHJKLMNPQSXZ"
"abcfgijmpqrstxyz"
"~!@#$%^&*|:'";"
"ABCEFGHIJKLMNOPQRSTUVWXZ"
"abcdefghijklmnopqrstuvwxyz"
Extension character sequences used so far ("-" followed by the
following), for quick reference when adding more:
"AB"
"abdstuvwxy"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -934,18 +1020,18 @@ struct mips_opcode
#define INSN_TLB 0x00000200
/* Reads coprocessor register other than floating point register. */
#define INSN_COP 0x00000400
/* Instruction loads value from memory, requiring delay. */
#define INSN_LOAD_MEMORY_DELAY 0x00000800
/* Instruction loads value from coprocessor, requiring delay. */
#define INSN_LOAD_COPROC_DELAY 0x00001000
/* Instruction loads value from memory. */
#define INSN_LOAD_MEMORY 0x00000800
/* Instruction loads value from coprocessor, (may require delay). */
#define INSN_LOAD_COPROC 0x00001000
/* Instruction has unconditional branch delay slot. */
#define INSN_UNCOND_BRANCH_DELAY 0x00002000
/* Instruction has conditional branch delay slot. */
#define INSN_COND_BRANCH_DELAY 0x00004000
/* Conditional branch likely: if branch not taken, insn nullified. */
#define INSN_COND_BRANCH_LIKELY 0x00008000
/* Moves to coprocessor register, requiring delay. */
#define INSN_COPROC_MOVE_DELAY 0x00010000
/* Moves to coprocessor register, (may require delay). */
#define INSN_COPROC_MOVE 0x00010000
/* Loads coprocessor register from memory, requiring delay. */
#define INSN_COPROC_MEMORY_DELAY 0x00020000
/* Reads the HI register. */
@@ -1014,6 +1100,8 @@ struct mips_opcode
#define INSN2_READ_GPR_16 0x00002000
/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
/* Instruction has a forbidden slot. */
#define INSN2_FORBIDDEN_SLOT 0x00008000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
@@ -1021,7 +1109,7 @@ struct mips_opcode
word constructed using these macros is a bitmask of the remaining
INSN_* values below. */
#define INSN_ISA_MASK 0x0000000ful
#define INSN_ISA_MASK 0x0000001ful
/* We cannot start at zero due to ISA_UNKNOWN below. */
#define INSN_ISA1 1
@@ -1031,28 +1119,75 @@ struct mips_opcode
#define INSN_ISA5 5
#define INSN_ISA32 6
#define INSN_ISA32R2 7
#define INSN_ISA64 8
#define INSN_ISA64R2 9
#define INSN_ISA32R3 8
#define INSN_ISA32R5 9
#define INSN_ISA32R6 10
#define INSN_ISA64 11
#define INSN_ISA64R2 12
#define INSN_ISA64R3 13
#define INSN_ISA64R5 14
#define INSN_ISA64R6 15
/* Below this point the INSN_* values correspond to combinations of ISAs.
They are only for use in the opcodes table to indicate membership of
a combination of ISAs that cannot be expressed using the usual inclusion
ordering on the above INSN_* values. */
#define INSN_ISA3_32 10
#define INSN_ISA3_32R2 11
#define INSN_ISA4_32 12
#define INSN_ISA4_32R2 13
#define INSN_ISA5_32R2 14
#define INSN_ISA3_32 16
#define INSN_ISA3_32R2 17
#define INSN_ISA4_32 18
#define INSN_ISA4_32R2 19
#define INSN_ISA5_32R2 20
/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
this table describes whether at least one of the ISAs described by X
is/are implemented by ISA Y. (Think of Y as the ISA level supported by
a particular core and X as the ISA level(s) at which a certain instruction
is defined.) The ISA(s) described by X is/are implemented by Y iff
(mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
is non-zero. */
static const unsigned int mips_isa_table[] =
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
/* The R6 definitions shown below state that they support all previous ISAs.
This is not actually true as some instructions are removed in R6.
The problem is that the removed instructions in R6 come from different
ISAs. One approach to solve this would be to describe in the membership
field of the opcode table the different ISAs an instruction belongs to.
This would require us to create a large amount of different ISA
combinations which is hard to manage. A cleaner approach (which is
implemented here) is to say that R6 is an extension of R5 and then to
deal with the removed instructions by adding instruction exclusions
for R6 in the opcode table. */
/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
#define ISAF(X) (1 << (INSN_ISA##X - 1))
#define INSN_UPTO1 ISAF(1)
#define INSN_UPTO2 INSN_UPTO1 | ISAF(2)
#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
| ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)
#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)
/* The same information in table form: bit INSN_ISA<X> - 1 of index
INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
static const unsigned int mips_isa_table[] = {
INSN_UPTO1,
INSN_UPTO2,
INSN_UPTO3,
INSN_UPTO4,
INSN_UPTO5,
INSN_UPTO32,
INSN_UPTO32R2,
INSN_UPTO32R3,
INSN_UPTO32R5,
INSN_UPTO32R6,
INSN_UPTO64,
INSN_UPTO64R2,
INSN_UPTO64R3,
INSN_UPTO64R5,
INSN_UPTO64R6
};
#undef ISAF
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0f20
@@ -1061,6 +1196,7 @@ static const unsigned int mips_isa_table[] =
#define INSN_OCTEON 0x00000800
#define INSN_OCTEONP 0x00000200
#define INSN_OCTEON2 0x00000100
#define INSN_OCTEON3 0x00000040
/* MIPS R5900 instruction */
#define INSN_5900 0x00004000
@@ -1115,6 +1251,11 @@ static const unsigned int mips_isa_table[] =
/* Virtualization ASE */
#define ASE_VIRT 0x00000200
#define ASE_VIRT64 0x00000400
/* MSA Extension */
#define ASE_MSA 0x00000800
#define ASE_MSA64 0x00001000
/* eXtended Physical Address (XPA) Extension. */
#define ASE_XPA 0x00002000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -1129,8 +1270,14 @@ static const unsigned int mips_isa_table[] =
#define ISA_MIPS64 INSN_ISA64
#define ISA_MIPS32R2 INSN_ISA32R2
#define ISA_MIPS32R3 INSN_ISA32R3
#define ISA_MIPS32R5 INSN_ISA32R5
#define ISA_MIPS64R2 INSN_ISA64R2
#define ISA_MIPS64R3 INSN_ISA64R3
#define ISA_MIPS64R5 INSN_ISA64R5
#define ISA_MIPS32R6 INSN_ISA32R6
#define ISA_MIPS64R6 INSN_ISA64R6
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
@@ -1161,9 +1308,15 @@ static const unsigned int mips_isa_table[] =
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
#define CPU_MIPS32R3 34
#define CPU_MIPS32R5 36
#define CPU_MIPS32R6 37
#define CPU_MIPS5 5
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
#define CPU_MIPS64R3 66
#define CPU_MIPS64R5 68
#define CPU_MIPS64R6 69
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
@@ -1171,6 +1324,7 @@ static const unsigned int mips_isa_table[] =
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
#define CPU_OCTEON3 6503
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Return true if the given CPU is included in INSN_* mask MASK. */
@@ -1236,9 +1390,19 @@ cpu_is_member (int cpu, unsigned int mask)
case CPU_OCTEON2:
return (mask & INSN_OCTEON2) != 0;
case CPU_OCTEON3:
return (mask & INSN_OCTEON3) != 0;
case CPU_XLR:
return (mask & INSN_XLR) != 0;
case CPU_MIPS32R6:
return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
case CPU_MIPS64R6:
return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
|| ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
default:
return FALSE;
}
@@ -1976,7 +2140,6 @@ extern const int bfd_mips16_num_opcodes;
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
"B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
@@ -2001,6 +2164,8 @@ extern const int bfd_mips16_num_opcodes;
"+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code
(MICROMIPSOP_*_CODE10)
PC-relative addition (ADDIUPC) instruction:
"mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
@@ -2044,6 +2209,33 @@ extern const int bfd_mips16_num_opcodes;
microMIPS Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
MSA Extension:
"+d" 5-bit MSA register (FD)
"+e" 5-bit MSA register (FS)
"+h" 5-bit MSA register (FT)
"+k" 5-bit GPR at bit 6
"+l" 5-bit MSA control register at bit 6
"+n" 5-bit MSA control register at bit 11
"+o" 4-bit vector element index at bit 16
"+u" 3-bit vector element index at bit 16
"+v" 2-bit vector element index at bit 16
"+w" 1-bit vector element index at bit 16
"+x" 5-bit shift amount at bit 16
"+T" (-512 .. 511) << 0 at bit 16
"+U" (-512 .. 511) << 1 at bit 16
"+V" (-512 .. 511) << 2 at bit 16
"+W" (-512 .. 511) << 3 at bit 16
"+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
"+!" 3 bit unsigned bit position at bit 16
"+@" 4 bit unsigned bit position at bit 16
"+#" 6 bit unsigned bit position at bit 16
"+$" 5 bit unsigned immediate at bit 16
"+%" 5 bit signed immediate at bit 16
"+^" 10 bit signed immediate at bit 11
"+&" 0 vector element index
"+*" 5-bit register vector element index at bit 16
"+|" 8-bit mask at bit 16
Other:
"()" parens surrounding optional value
"," separates operands
@@ -2052,16 +2244,16 @@ extern const int bfd_mips16_num_opcodes;
Characters used so far, for quick reference when adding more:
"12345678 0"
"<>(),+.@\^|~"
"<>(),+-.@\^|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
""
"ABCEFGH"
"ij"
"~!@#$%^&*|"
"ABCEFGHJTUVW"
"dehijklnouvwx"
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more:
@@ -2069,6 +2261,12 @@ extern const int bfd_mips16_num_opcodes;
""
" BCDEFGHIJ LMNOPQ U WXYZ"
" bcdefghij lmn pq st xyz"
Extension character sequences used so far ("-" followed by the
following), for quick reference when adding more:
""
""
<none so far>
*/
extern const struct mips_operand *decode_micromips_operand (const char *);