forked from KolibriOS/kolibrios
ddk: 4.4
git-svn-id: svn://kolibrios.org@6082 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
@@ -2,6 +2,426 @@
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#ifndef _LINUX_ATOMIC_H
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#define _LINUX_ATOMIC_H
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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/*
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* Relaxed variants of xchg, cmpxchg and some atomic operations.
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*
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* We support four variants:
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*
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* - Fully ordered: The default implementation, no suffix required.
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* - Acquire: Provides ACQUIRE semantics, _acquire suffix.
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* - Release: Provides RELEASE semantics, _release suffix.
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* - Relaxed: No ordering guarantees, _relaxed suffix.
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*
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* For compound atomics performing both a load and a store, ACQUIRE
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* semantics apply only to the load and RELEASE semantics only to the
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* store portion of the operation. Note that a failed cmpxchg_acquire
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* does -not- imply any memory ordering constraints.
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*
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* See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions.
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*/
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#ifndef atomic_read_acquire
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#define atomic_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic_set_release
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#define atomic_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/*
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* The idea here is to build acquire/release variants by adding explicit
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* barriers on top of the relaxed variant. In the case where the relaxed
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* variant is already fully ordered, no additional barriers are needed.
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*/
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#define __atomic_op_acquire(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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#define __atomic_op_release(op, args...) \
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({ \
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smp_mb__before_atomic(); \
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op##_relaxed(args); \
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})
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#define __atomic_op_fence(op, args...) \
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({ \
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typeof(op##_relaxed(args)) __ret; \
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smp_mb__before_atomic(); \
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__ret = op##_relaxed(args); \
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smp_mb__after_atomic(); \
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__ret; \
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})
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/* atomic_add_return_relaxed */
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#ifndef atomic_add_return_relaxed
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#define atomic_add_return_relaxed atomic_add_return
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#define atomic_add_return_acquire atomic_add_return
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#define atomic_add_return_release atomic_add_return
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#else /* atomic_add_return_relaxed */
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#ifndef atomic_add_return_acquire
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#define atomic_add_return_acquire(...) \
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__atomic_op_acquire(atomic_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic_add_return_release
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#define atomic_add_return_release(...) \
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__atomic_op_release(atomic_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic_add_return
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#define atomic_add_return(...) \
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__atomic_op_fence(atomic_add_return, __VA_ARGS__)
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#endif
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#endif /* atomic_add_return_relaxed */
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/* atomic_inc_return_relaxed */
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#ifndef atomic_inc_return_relaxed
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#define atomic_inc_return_relaxed atomic_inc_return
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#define atomic_inc_return_acquire atomic_inc_return
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#define atomic_inc_return_release atomic_inc_return
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#else /* atomic_inc_return_relaxed */
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#ifndef atomic_inc_return_acquire
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#define atomic_inc_return_acquire(...) \
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__atomic_op_acquire(atomic_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic_inc_return_release
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#define atomic_inc_return_release(...) \
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__atomic_op_release(atomic_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic_inc_return
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#define atomic_inc_return(...) \
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__atomic_op_fence(atomic_inc_return, __VA_ARGS__)
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#endif
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#endif /* atomic_inc_return_relaxed */
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/* atomic_sub_return_relaxed */
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#ifndef atomic_sub_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return
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#define atomic_sub_return_acquire atomic_sub_return
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#define atomic_sub_return_release atomic_sub_return
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#else /* atomic_sub_return_relaxed */
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#ifndef atomic_sub_return_acquire
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#define atomic_sub_return_acquire(...) \
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__atomic_op_acquire(atomic_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic_sub_return_release
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#define atomic_sub_return_release(...) \
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__atomic_op_release(atomic_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic_sub_return
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#define atomic_sub_return(...) \
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__atomic_op_fence(atomic_sub_return, __VA_ARGS__)
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#endif
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#endif /* atomic_sub_return_relaxed */
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/* atomic_dec_return_relaxed */
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#ifndef atomic_dec_return_relaxed
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#define atomic_dec_return_relaxed atomic_dec_return
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#define atomic_dec_return_acquire atomic_dec_return
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#define atomic_dec_return_release atomic_dec_return
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#else /* atomic_dec_return_relaxed */
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#ifndef atomic_dec_return_acquire
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#define atomic_dec_return_acquire(...) \
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__atomic_op_acquire(atomic_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic_dec_return_release
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#define atomic_dec_return_release(...) \
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__atomic_op_release(atomic_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic_dec_return
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#define atomic_dec_return(...) \
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__atomic_op_fence(atomic_dec_return, __VA_ARGS__)
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#endif
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#endif /* atomic_dec_return_relaxed */
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/* atomic_xchg_relaxed */
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#ifndef atomic_xchg_relaxed
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#define atomic_xchg_relaxed atomic_xchg
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#define atomic_xchg_acquire atomic_xchg
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#define atomic_xchg_release atomic_xchg
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#else /* atomic_xchg_relaxed */
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#ifndef atomic_xchg_acquire
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#define atomic_xchg_acquire(...) \
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__atomic_op_acquire(atomic_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic_xchg_release
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#define atomic_xchg_release(...) \
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__atomic_op_release(atomic_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic_xchg
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#define atomic_xchg(...) \
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__atomic_op_fence(atomic_xchg, __VA_ARGS__)
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#endif
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#endif /* atomic_xchg_relaxed */
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/* atomic_cmpxchg_relaxed */
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#ifndef atomic_cmpxchg_relaxed
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#define atomic_cmpxchg_relaxed atomic_cmpxchg
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#define atomic_cmpxchg_acquire atomic_cmpxchg
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#define atomic_cmpxchg_release atomic_cmpxchg
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#else /* atomic_cmpxchg_relaxed */
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#ifndef atomic_cmpxchg_acquire
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#define atomic_cmpxchg_acquire(...) \
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__atomic_op_acquire(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic_cmpxchg_release
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#define atomic_cmpxchg_release(...) \
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__atomic_op_release(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic_cmpxchg
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#define atomic_cmpxchg(...) \
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__atomic_op_fence(atomic_cmpxchg, __VA_ARGS__)
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#endif
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#endif /* atomic_cmpxchg_relaxed */
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#ifndef atomic64_read_acquire
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#define atomic64_read_acquire(v) smp_load_acquire(&(v)->counter)
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#endif
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#ifndef atomic64_set_release
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#define atomic64_set_release(v, i) smp_store_release(&(v)->counter, (i))
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#endif
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/* atomic64_add_return_relaxed */
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#ifndef atomic64_add_return_relaxed
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#define atomic64_add_return_relaxed atomic64_add_return
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#define atomic64_add_return_acquire atomic64_add_return
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#define atomic64_add_return_release atomic64_add_return
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#else /* atomic64_add_return_relaxed */
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#ifndef atomic64_add_return_acquire
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#define atomic64_add_return_acquire(...) \
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__atomic_op_acquire(atomic64_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_add_return_release
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#define atomic64_add_return_release(...) \
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__atomic_op_release(atomic64_add_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_add_return
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#define atomic64_add_return(...) \
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__atomic_op_fence(atomic64_add_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_add_return_relaxed */
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/* atomic64_inc_return_relaxed */
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#ifndef atomic64_inc_return_relaxed
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#define atomic64_inc_return_relaxed atomic64_inc_return
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#define atomic64_inc_return_acquire atomic64_inc_return
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#define atomic64_inc_return_release atomic64_inc_return
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#else /* atomic64_inc_return_relaxed */
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#ifndef atomic64_inc_return_acquire
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#define atomic64_inc_return_acquire(...) \
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__atomic_op_acquire(atomic64_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_inc_return_release
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#define atomic64_inc_return_release(...) \
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__atomic_op_release(atomic64_inc_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_inc_return
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#define atomic64_inc_return(...) \
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__atomic_op_fence(atomic64_inc_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_inc_return_relaxed */
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/* atomic64_sub_return_relaxed */
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#ifndef atomic64_sub_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return
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#define atomic64_sub_return_acquire atomic64_sub_return
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#define atomic64_sub_return_release atomic64_sub_return
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#else /* atomic64_sub_return_relaxed */
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#ifndef atomic64_sub_return_acquire
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#define atomic64_sub_return_acquire(...) \
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__atomic_op_acquire(atomic64_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_sub_return_release
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#define atomic64_sub_return_release(...) \
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__atomic_op_release(atomic64_sub_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_sub_return
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#define atomic64_sub_return(...) \
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__atomic_op_fence(atomic64_sub_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_sub_return_relaxed */
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/* atomic64_dec_return_relaxed */
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#ifndef atomic64_dec_return_relaxed
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#define atomic64_dec_return_relaxed atomic64_dec_return
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#define atomic64_dec_return_acquire atomic64_dec_return
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#define atomic64_dec_return_release atomic64_dec_return
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#else /* atomic64_dec_return_relaxed */
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#ifndef atomic64_dec_return_acquire
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#define atomic64_dec_return_acquire(...) \
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__atomic_op_acquire(atomic64_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_dec_return_release
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#define atomic64_dec_return_release(...) \
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__atomic_op_release(atomic64_dec_return, __VA_ARGS__)
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#endif
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#ifndef atomic64_dec_return
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#define atomic64_dec_return(...) \
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__atomic_op_fence(atomic64_dec_return, __VA_ARGS__)
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#endif
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#endif /* atomic64_dec_return_relaxed */
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/* atomic64_xchg_relaxed */
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#ifndef atomic64_xchg_relaxed
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#define atomic64_xchg_relaxed atomic64_xchg
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#define atomic64_xchg_acquire atomic64_xchg
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#define atomic64_xchg_release atomic64_xchg
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#else /* atomic64_xchg_relaxed */
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#ifndef atomic64_xchg_acquire
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#define atomic64_xchg_acquire(...) \
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__atomic_op_acquire(atomic64_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_xchg_release
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#define atomic64_xchg_release(...) \
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__atomic_op_release(atomic64_xchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_xchg
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#define atomic64_xchg(...) \
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__atomic_op_fence(atomic64_xchg, __VA_ARGS__)
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#endif
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#endif /* atomic64_xchg_relaxed */
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/* atomic64_cmpxchg_relaxed */
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#ifndef atomic64_cmpxchg_relaxed
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#define atomic64_cmpxchg_relaxed atomic64_cmpxchg
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#define atomic64_cmpxchg_acquire atomic64_cmpxchg
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#define atomic64_cmpxchg_release atomic64_cmpxchg
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#else /* atomic64_cmpxchg_relaxed */
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#ifndef atomic64_cmpxchg_acquire
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#define atomic64_cmpxchg_acquire(...) \
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__atomic_op_acquire(atomic64_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_cmpxchg_release
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#define atomic64_cmpxchg_release(...) \
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__atomic_op_release(atomic64_cmpxchg, __VA_ARGS__)
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#endif
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#ifndef atomic64_cmpxchg
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#define atomic64_cmpxchg(...) \
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__atomic_op_fence(atomic64_cmpxchg, __VA_ARGS__)
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#endif
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#endif /* atomic64_cmpxchg_relaxed */
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/* cmpxchg_relaxed */
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#ifndef cmpxchg_relaxed
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#define cmpxchg_relaxed cmpxchg
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#define cmpxchg_acquire cmpxchg
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#define cmpxchg_release cmpxchg
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#else /* cmpxchg_relaxed */
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#ifndef cmpxchg_acquire
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#define cmpxchg_acquire(...) \
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__atomic_op_acquire(cmpxchg, __VA_ARGS__)
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#endif
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#ifndef cmpxchg_release
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#define cmpxchg_release(...) \
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__atomic_op_release(cmpxchg, __VA_ARGS__)
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#endif
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#ifndef cmpxchg
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#define cmpxchg(...) \
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__atomic_op_fence(cmpxchg, __VA_ARGS__)
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#endif
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#endif /* cmpxchg_relaxed */
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/* cmpxchg64_relaxed */
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#ifndef cmpxchg64_relaxed
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#define cmpxchg64_relaxed cmpxchg64
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#define cmpxchg64_acquire cmpxchg64
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#define cmpxchg64_release cmpxchg64
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#else /* cmpxchg64_relaxed */
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#ifndef cmpxchg64_acquire
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#define cmpxchg64_acquire(...) \
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__atomic_op_acquire(cmpxchg64, __VA_ARGS__)
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#endif
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#ifndef cmpxchg64_release
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#define cmpxchg64_release(...) \
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__atomic_op_release(cmpxchg64, __VA_ARGS__)
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#endif
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#ifndef cmpxchg64
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#define cmpxchg64(...) \
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__atomic_op_fence(cmpxchg64, __VA_ARGS__)
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#endif
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#endif /* cmpxchg64_relaxed */
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/* xchg_relaxed */
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#ifndef xchg_relaxed
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#define xchg_relaxed xchg
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#define xchg_acquire xchg
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#define xchg_release xchg
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#else /* xchg_relaxed */
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#ifndef xchg_acquire
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#define xchg_acquire(...) __atomic_op_acquire(xchg, __VA_ARGS__)
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#endif
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#ifndef xchg_release
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#define xchg_release(...) __atomic_op_release(xchg, __VA_ARGS__)
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#endif
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#ifndef xchg
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#define xchg(...) __atomic_op_fence(xchg, __VA_ARGS__)
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#endif
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#endif /* xchg_relaxed */
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/**
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* atomic_add_unless - add unless the number is already a given value
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@@ -28,6 +448,23 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#endif
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#ifndef atomic_andnot
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static inline void atomic_andnot(int i, atomic_t *v)
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{
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atomic_and(~i, v);
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}
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#endif
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||||
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static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t *v)
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||||
{
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atomic_andnot(mask, v);
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}
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||||
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static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
|
||||
{
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atomic_or(mask, v);
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}
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|
||||
/**
|
||||
* atomic_inc_not_zero_hint - increment if not null
|
||||
* @v: pointer of type atomic_t
|
||||
@@ -111,21 +548,17 @@ static inline int atomic_dec_if_positive(atomic_t *v)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ARCH_HAS_ATOMIC_OR
|
||||
static inline void atomic_or(int i, atomic_t *v)
|
||||
{
|
||||
int old;
|
||||
int new;
|
||||
|
||||
do {
|
||||
old = atomic_read(v);
|
||||
new = old | i;
|
||||
} while (atomic_cmpxchg(v, old, new) != old);
|
||||
}
|
||||
#endif /* #ifndef CONFIG_ARCH_HAS_ATOMIC_OR */
|
||||
|
||||
#include <asm-generic/atomic-long.h>
|
||||
#ifdef CONFIG_GENERIC_ATOMIC64
|
||||
#include <asm-generic/atomic64.h>
|
||||
#endif
|
||||
|
||||
#ifndef atomic64_andnot
|
||||
static inline void atomic64_andnot(long long i, atomic64_t *v)
|
||||
{
|
||||
atomic64_and(~i, v);
|
||||
}
|
||||
#endif
|
||||
|
||||
#include <asm-generic/atomic-long.h>
|
||||
|
||||
#endif /* _LINUX_ATOMIC_H */
|
||||
|
||||
Reference in New Issue
Block a user