forked from KolibriOS/kolibrios
video/drm: batch update
git-svn-id: svn://kolibrios.org@3031 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
@@ -6,7 +6,7 @@
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#include <asm/required-features.h>
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#define NCAPINTS 9 /* N 32-bit words worth of info */
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#define NCAPINTS 10 /* N 32-bit words worth of info */
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/*
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* Note: If the comment begins with a quoted string, that string is used
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@@ -89,7 +89,7 @@
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
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#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
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#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */
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/* 21 available, was AMD_C1E */
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#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
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#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
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#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
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@@ -97,6 +97,7 @@
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#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */
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#define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */
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#define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
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@@ -114,16 +115,20 @@
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
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#define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
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#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
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#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
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#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
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#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */
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#define X86_FEATURE_AES (4*32+25) /* AES instructions */
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#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
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#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
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#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
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#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
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#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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@@ -150,23 +155,62 @@
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#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
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#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
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#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
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#define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */
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#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
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#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
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#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
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#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
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#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
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#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */
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#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
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#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
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#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
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#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
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/*
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* Auxiliary flags: Linux defined - For features scattered in various
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* CPUID levels like 0x6, 0xA etc
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* CPUID levels like 0x6, 0xA etc, word 7
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*/
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#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */
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#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */
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#define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */
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#define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
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#define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */
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#define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */
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#define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */
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#define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */
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#define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */
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/* Virtualization flags: Linux defined */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */
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#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */
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#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
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#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */
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#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */
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#define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */
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#define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */
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#define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
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#define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
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#define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
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#define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
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#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */
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#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */
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#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */
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#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
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#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
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#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
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#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */
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#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
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#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
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#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
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#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
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#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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@@ -178,8 +222,7 @@ extern const char * const x86_power_flags[32];
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#define test_cpu_cap(c, bit) \
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test_bit(bit, (unsigned long *)((c)->x86_capability))
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && \
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#define REQUIRED_MASK_BIT_SET(bit) \
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( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
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(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
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(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
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@@ -187,10 +230,18 @@ extern const char * const x86_power_flags[32];
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(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
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(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
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(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
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(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
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? 1 : \
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(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \
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(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \
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(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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test_cpu_cap(c, bit))
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#define this_cpu_has(bit) \
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(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
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x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
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#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
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#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
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@@ -219,7 +270,9 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
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#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
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#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
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#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3)
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#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
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#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
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#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
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#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
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#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
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@@ -247,8 +300,14 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
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#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
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#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
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#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT)
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#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE)
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#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
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#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
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#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
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#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
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#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
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#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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