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git-svn-id: svn://kolibrios.org@5191 a494cfbc-eb01-0410-851d-a64ba20cac60
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Sergey Semyonov (Serge)
2014-11-28 06:08:38 +00:00
parent d6244d0651
commit bf3c2fabd6
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/* AArch64 assembler/disassembler support.
Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GNU Binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#ifndef OPCODE_AARCH64_H
#define OPCODE_AARCH64_H
#include "bfd.h"
#include "bfd_stdint.h"
#include <assert.h>
#include <stdlib.h>
/* The offset for pc-relative addressing is currently defined to be 0. */
#define AARCH64_PCREL_OFFSET 0
typedef uint32_t aarch64_insn;
/* The following bitmasks control CPU features. */
#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
AARCH64_FEATURE_FP \
| AARCH64_FEATURE_SIMD)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
/* CPU-specific features. */
typedef unsigned long aarch64_feature_set;
#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
(((CPU) & (FEAT)) != 0)
#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
do \
{ \
(TARG) = (F1) | (F2); \
} \
while (0)
#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
do \
{ \
(TARG) = (F1) &~ (F2); \
} \
while (0)
#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
#define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
(((OPC) & (FEAT)) != 0)
enum aarch64_operand_class
{
AARCH64_OPND_CLASS_NIL,
AARCH64_OPND_CLASS_INT_REG,
AARCH64_OPND_CLASS_MODIFIED_REG,
AARCH64_OPND_CLASS_FP_REG,
AARCH64_OPND_CLASS_SIMD_REG,
AARCH64_OPND_CLASS_SIMD_ELEMENT,
AARCH64_OPND_CLASS_SISD_REG,
AARCH64_OPND_CLASS_SIMD_REGLIST,
AARCH64_OPND_CLASS_CP_REG,
AARCH64_OPND_CLASS_ADDRESS,
AARCH64_OPND_CLASS_IMMEDIATE,
AARCH64_OPND_CLASS_SYSTEM,
AARCH64_OPND_CLASS_COND,
};
/* Operand code that helps both parsing and coding.
Keep AARCH64_OPERANDS synced. */
enum aarch64_opnd
{
AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
AARCH64_OPND_Rd, /* Integer register as destination. */
AARCH64_OPND_Rn, /* Integer register as source. */
AARCH64_OPND_Rm, /* Integer register as source. */
AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
AARCH64_OPND_Fd, /* Floating-point Fd. */
AARCH64_OPND_Fn, /* Floating-point Fn. */
AARCH64_OPND_Fm, /* Floating-point Fm. */
AARCH64_OPND_Fa, /* Floating-point Fa. */
AARCH64_OPND_Ft, /* Floating-point Ft. */
AARCH64_OPND_Ft2, /* Floating-point Ft2. */
AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
structure to all lanes. */
AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
AARCH64_OPND_Cn, /* Co-processor register in CRn field. */
AARCH64_OPND_Cm, /* Co-processor register in CRm field. */
AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
(no encoding). */
AARCH64_OPND_IMM0, /* Immediate for #0. */
AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
AARCH64_OPND_IMM, /* Immediate. */
AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
AARCH64_OPND_BIT_NUM, /* Immediate. */
AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
each condition flag. */
AARCH64_OPND_LIMM, /* Logical Immediate. */
AARCH64_OPND_AIMM, /* Arithmetic immediate. */
AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
AARCH64_OPND_COND, /* Standard condition as the last operand. */
AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
negative or unaligned and there is
no writeback allowed. This operand code
is only used to support the programmer-
friendly feature of using LDR/STR as the
the mnemonic name for LDUR/STUR instructions
wherever there is no ambiguity. */
AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
AARCH64_OPND_SYSREG, /* System register operand. */
AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
};
/* Qualifier constrains an operand. It either specifies a variant of an
operand type or limits values available to an operand type.
N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
enum aarch64_opnd_qualifier
{
/* Indicating no further qualification on an operand. */
AARCH64_OPND_QLF_NIL,
/* Qualifying an operand which is a general purpose (integer) register;
indicating the operand data size or a specific register. */
AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
AARCH64_OPND_QLF_WSP, /* WSP. */
AARCH64_OPND_QLF_SP, /* SP. */
/* Qualifying an operand which is a floating-point register, a SIMD
vector element or a SIMD vector element list; indicating operand data
size or the size of each SIMD vector element in the case of a SIMD
vector element list.
These qualifiers are also used to qualify an address operand to
indicate the size of data element a load/store instruction is
accessing.
They are also used for the immediate shift operand in e.g. SSHR. Such
a use is only for the ease of operand encoding/decoding and qualifier
sequence matching; such a use should not be applied widely; use the value
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_S_B,
AARCH64_OPND_QLF_S_H,
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
/* Qualifying an operand which is a SIMD vector register or a SIMD vector
register list; indicating register shape.
They are also used for the immediate shift operand in e.g. SSHR. Such
a use is only for the ease of operand encoding/decoding and qualifier
sequence matching; such a use should not be applied widely; use the value
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_V_8B,
AARCH64_OPND_QLF_V_16B,
AARCH64_OPND_QLF_V_4H,
AARCH64_OPND_QLF_V_8H,
AARCH64_OPND_QLF_V_2S,
AARCH64_OPND_QLF_V_4S,
AARCH64_OPND_QLF_V_1D,
AARCH64_OPND_QLF_V_2D,
AARCH64_OPND_QLF_V_1Q,
/* Constraint on value. */
AARCH64_OPND_QLF_imm_0_7,
AARCH64_OPND_QLF_imm_0_15,
AARCH64_OPND_QLF_imm_0_31,
AARCH64_OPND_QLF_imm_0_63,
AARCH64_OPND_QLF_imm_1_32,
AARCH64_OPND_QLF_imm_1_64,
/* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
or shift-ones. */
AARCH64_OPND_QLF_LSL,
AARCH64_OPND_QLF_MSL,
/* Special qualifier helping retrieve qualifier information during the
decoding time (currently not in use). */
AARCH64_OPND_QLF_RETRIEVE,
};
/* Instruction class. */
enum aarch64_insn_class
{
addsub_carry,
addsub_ext,
addsub_imm,
addsub_shift,
asimdall,
asimddiff,
asimdelem,
asimdext,
asimdimm,
asimdins,
asimdmisc,
asimdperm,
asimdsame,
asimdshf,
asimdtbl,
asisddiff,
asisdelem,
asisdlse,
asisdlsep,
asisdlso,
asisdlsop,
asisdmisc,
asisdone,
asisdpair,
asisdsame,
asisdshf,
bitfield,
branch_imm,
branch_reg,
compbranch,
condbranch,
condcmp_imm,
condcmp_reg,
condsel,
cryptoaes,
cryptosha2,
cryptosha3,
dp_1src,
dp_2src,
dp_3src,
exception,
extract,
float2fix,
float2int,
floatccmp,
floatcmp,
floatdp1,
floatdp2,
floatdp3,
floatimm,
floatsel,
ldst_immpost,
ldst_immpre,
ldst_imm9, /* immpost or immpre */
ldst_pos,
ldst_regoff,
ldst_unpriv,
ldst_unscaled,
ldstexcl,
ldstnapair_offs,
ldstpair_off,
ldstpair_indexed,
loadlit,
log_imm,
log_shift,
movewide,
pcreladdr,
ic_system,
testbranch,
};
/* Opcode enumerators. */
enum aarch64_op
{
OP_NIL,
OP_STRB_POS,
OP_LDRB_POS,
OP_LDRSB_POS,
OP_STRH_POS,
OP_LDRH_POS,
OP_LDRSH_POS,
OP_STR_POS,
OP_LDR_POS,
OP_STRF_POS,
OP_LDRF_POS,
OP_LDRSW_POS,
OP_PRFM_POS,
OP_STURB,
OP_LDURB,
OP_LDURSB,
OP_STURH,
OP_LDURH,
OP_LDURSH,
OP_STUR,
OP_LDUR,
OP_STURV,
OP_LDURV,
OP_LDURSW,
OP_PRFUM,
OP_LDR_LIT,
OP_LDRV_LIT,
OP_LDRSW_LIT,
OP_PRFM_LIT,
OP_ADD,
OP_B,
OP_BL,
OP_MOVN,
OP_MOVZ,
OP_MOVK,
OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
OP_MOV_V, /* MOV alias for moving vector register. */
OP_ASR_IMM,
OP_LSR_IMM,
OP_LSL_IMM,
OP_BIC,
OP_UBFX,
OP_BFXIL,
OP_SBFX,
OP_SBFIZ,
OP_BFI,
OP_UBFIZ,
OP_UXTB,
OP_UXTH,
OP_UXTW,
OP_CINC,
OP_CINV,
OP_CNEG,
OP_CSET,
OP_CSETM,
OP_FCVT,
OP_FCVTN,
OP_FCVTN2,
OP_FCVTL,
OP_FCVTL2,
OP_FCVTXN_S, /* Scalar version. */
OP_ROR_IMM,
OP_SXTL,
OP_SXTL2,
OP_UXTL,
OP_UXTL2,
OP_TOTAL_NUM, /* Pseudo. */
};
/* Maximum number of operands an instruction can have. */
#define AARCH64_MAX_OPND_NUM 6
/* Maximum number of qualifier sequences an instruction can have. */
#define AARCH64_MAX_QLF_SEQ_NUM 10
/* Operand qualifier typedef; optimized for the size. */
typedef unsigned char aarch64_opnd_qualifier_t;
/* Operand qualifier sequence typedef. */
typedef aarch64_opnd_qualifier_t \
aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
/* FIXME: improve the efficiency. */
static inline bfd_boolean
empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
{
int i;
for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
return FALSE;
return TRUE;
}
/* This structure holds information for a particular opcode. */
struct aarch64_opcode
{
/* The name of the mnemonic. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
aarch64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
aarch64_insn mask;
/* Instruction class. */
enum aarch64_insn_class iclass;
/* Enumerator identifier. */
enum aarch64_op op;
/* Which architecture variant provides this instruction. */
const aarch64_feature_set *avariant;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
/* A list of operand qualifier code sequence. Each operand qualifier
code qualifies the corresponding operand code. Each operand
qualifier sequence specifies a valid opcode variant and related
constraint on operands. */
aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
/* Flags providing information about this instruction */
uint32_t flags;
};
typedef struct aarch64_opcode aarch64_opcode;
/* Table describing all the AArch64 opcodes. */
extern aarch64_opcode aarch64_opcode_table[];
/* Opcode flags. */
#define F_ALIAS (1 << 0)
#define F_HAS_ALIAS (1 << 1)
/* Disassembly preference priority 1-3 (the larger the higher). If nothing
is specified, it is the priority 0 by default, i.e. the lowest priority. */
#define F_P1 (1 << 2)
#define F_P2 (2 << 2)
#define F_P3 (3 << 2)
/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
#define F_COND (1 << 4)
/* Instruction has the field of 'sf'. */
#define F_SF (1 << 5)
/* Instruction has the field of 'size:Q'. */
#define F_SIZEQ (1 << 6)
/* Floating-point instruction has the field of 'type'. */
#define F_FPTYPE (1 << 7)
/* AdvSIMD scalar instruction has the field of 'size'. */
#define F_SSIZE (1 << 8)
/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
#define F_T (1 << 9)
/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
#define F_GPRSIZE_IN_Q (1 << 10)
/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
#define F_LDS_SIZE (1 << 11)
/* Optional operand; assume maximum of 1 operand can be optional. */
#define F_OPD0_OPT (1 << 12)
#define F_OPD1_OPT (2 << 12)
#define F_OPD2_OPT (3 << 12)
#define F_OPD3_OPT (4 << 12)
#define F_OPD4_OPT (5 << 12)
/* Default value for the optional operand when omitted from the assembly. */
#define F_DEFAULT(X) (((X) & 0x1f) << 15)
/* Instruction that is an alias of another instruction needs to be
encoded/decoded by converting it to/from the real form, followed by
the encoding/decoding according to the rules of the real opcode.
This compares to the direct coding using the alias's information.
N.B. this flag requires F_ALIAS to be used together. */
#define F_CONV (1 << 20)
/* Use together with F_ALIAS to indicate an alias opcode is a programmer
friendly pseudo instruction available only in the assembly code (thus will
not show up in the disassembly). */
#define F_PSEUDO (1 << 21)
/* Instruction has miscellaneous encoding/decoding rules. */
#define F_MISC (1 << 22)
/* Instruction has the field of 'N'; used in conjunction with F_SF. */
#define F_N (1 << 23)
/* Opcode dependent field. */
#define F_OD(X) (((X) & 0x7) << 24)
/* Next bit is 27. */
static inline bfd_boolean
alias_opcode_p (const aarch64_opcode *opcode)
{
return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
}
static inline bfd_boolean
opcode_has_alias (const aarch64_opcode *opcode)
{
return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
}
/* Priority for disassembling preference. */
static inline int
opcode_priority (const aarch64_opcode *opcode)
{
return (opcode->flags >> 2) & 0x3;
}
static inline bfd_boolean
pseudo_opcode_p (const aarch64_opcode *opcode)
{
return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
}
static inline bfd_boolean
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
{
return (((opcode->flags >> 12) & 0x7) == idx + 1)
? TRUE : FALSE;
}
static inline aarch64_insn
get_optional_operand_default_value (const aarch64_opcode *opcode)
{
return (opcode->flags >> 15) & 0x1f;
}
static inline unsigned int
get_opcode_dependent_value (const aarch64_opcode *opcode)
{
return (opcode->flags >> 24) & 0x7;
}
static inline bfd_boolean
opcode_has_special_coder (const aarch64_opcode *opcode)
{
return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
| F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
: FALSE;
}
struct aarch64_name_value_pair
{
const char * name;
aarch64_insn value;
};
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
typedef struct
{
const char * name;
aarch64_insn value;
uint32_t flags;
} aarch64_sys_reg;
extern const aarch64_sys_reg aarch64_sys_regs [];
extern const aarch64_sys_reg aarch64_pstatefields [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
typedef struct
{
const char *template;
uint32_t value;
int has_xt;
} aarch64_sys_ins_reg;
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
/* Shift/extending operator kinds.
N.B. order is important; keep aarch64_operand_modifiers synced. */
enum aarch64_modifier_kind
{
AARCH64_MOD_NONE,
AARCH64_MOD_MSL,
AARCH64_MOD_ROR,
AARCH64_MOD_ASR,
AARCH64_MOD_LSR,
AARCH64_MOD_LSL,
AARCH64_MOD_UXTB,
AARCH64_MOD_UXTH,
AARCH64_MOD_UXTW,
AARCH64_MOD_UXTX,
AARCH64_MOD_SXTB,
AARCH64_MOD_SXTH,
AARCH64_MOD_SXTW,
AARCH64_MOD_SXTX,
};
bfd_boolean
aarch64_extend_operator_p (enum aarch64_modifier_kind);
enum aarch64_modifier_kind
aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
/* Condition. */
typedef struct
{
/* A list of names with the first one as the disassembly preference;
terminated by NULL if fewer than 3. */
const char *names[3];
aarch64_insn value;
} aarch64_cond;
extern const aarch64_cond aarch64_conds[16];
const aarch64_cond* get_cond_from_value (aarch64_insn value);
const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
/* Structure representing an operand. */
struct aarch64_opnd_info
{
enum aarch64_opnd type;
aarch64_opnd_qualifier_t qualifier;
int idx;
union
{
struct
{
unsigned regno;
} reg;
struct
{
unsigned regno : 5;
unsigned index : 4;
} reglane;
/* e.g. LVn. */
struct
{
unsigned first_regno : 5;
unsigned num_regs : 3;
/* 1 if it is a list of reg element. */
unsigned has_index : 1;
/* Lane index; valid only when has_index is 1. */
unsigned index : 4;
} reglist;
/* e.g. immediate or pc relative address offset. */
struct
{
int64_t value;
unsigned is_fp : 1;
} imm;
/* e.g. address in STR (register offset). */
struct
{
unsigned base_regno;
struct
{
union
{
int imm;
unsigned regno;
};
unsigned is_reg;
} offset;
unsigned pcrel : 1; /* PC-relative. */
unsigned writeback : 1;
unsigned preind : 1; /* Pre-indexed. */
unsigned postind : 1; /* Post-indexed. */
} addr;
const aarch64_cond *cond;
/* The encoding of the system register. */
aarch64_insn sysreg;
/* The encoding of the PSTATE field. */
aarch64_insn pstatefield;
const aarch64_sys_ins_reg *sysins_op;
const struct aarch64_name_value_pair *barrier;
const struct aarch64_name_value_pair *prfop;
};
/* Operand shifter; in use when the operand is a register offset address,
add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
struct
{
enum aarch64_modifier_kind kind;
int amount;
unsigned operator_present: 1; /* Only valid during encoding. */
/* Value of the 'S' field in ld/st reg offset; used only in decoding. */
unsigned amount_present: 1;
} shifter;
unsigned skip:1; /* Operand is not completed if there is a fixup needed
to be done on it. In some (but not all) of these
cases, we need to tell libopcodes to skip the
constraint checking and the encoding for this
operand, so that the libopcodes can pick up the
right opcode before the operand is fixed-up. This
flag should only be used during the
assembling/encoding. */
unsigned present:1; /* Whether this operand is present in the assembly
line; not used during the disassembly. */
};
typedef struct aarch64_opnd_info aarch64_opnd_info;
/* Structure representing an instruction.
It is used during both the assembling and disassembling. The assembler
fills an aarch64_inst after a successful parsing and then passes it to the
encoding routine to do the encoding. During the disassembling, the
disassembler calls the decoding routine to decode a binary instruction; on a
successful return, such a structure will be filled with information of the
instruction; then the disassembler uses the information to print out the
instruction. */
struct aarch64_inst
{
/* The value of the binary instruction. */
aarch64_insn value;
/* Corresponding opcode entry. */
const aarch64_opcode *opcode;
/* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
const aarch64_cond *cond;
/* Operands information. */
aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
};
typedef struct aarch64_inst aarch64_inst;
/* Diagnosis related declaration and interface. */
/* Operand error kind enumerators.
AARCH64_OPDE_RECOVERABLE
Less severe error found during the parsing, very possibly because that
GAS has picked up a wrong instruction template for the parsing.
AARCH64_OPDE_SYNTAX_ERROR
General syntax error; it can be either a user error, or simply because
that GAS is trying a wrong instruction template.
AARCH64_OPDE_FATAL_SYNTAX_ERROR
Definitely a user syntax error.
AARCH64_OPDE_INVALID_VARIANT
No syntax error, but the operands are not a valid combination, e.g.
FMOV D0,S0
AARCH64_OPDE_OUT_OF_RANGE
Error about some immediate value out of a valid range.
AARCH64_OPDE_UNALIGNED
Error about some immediate value not properly aligned (i.e. not being a
multiple times of a certain value).
AARCH64_OPDE_REG_LIST
Error about the register list operand having unexpected number of
registers.
AARCH64_OPDE_OTHER_ERROR
Error of the highest severity and used for any severe issue that does not
fall into any of the above categories.
The enumerators are only interesting to GAS. They are declared here (in
libopcodes) because that some errors are detected (and then notified to GAS)
by libopcodes (rather than by GAS solely).
The first three errors are only deteced by GAS while the
AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
only libopcodes has the information about the valid variants of each
instruction.
The enumerators have an increasing severity. This is helpful when there are
multiple instruction templates available for a given mnemonic name (e.g.
FMOV); this mechanism will help choose the most suitable template from which
the generated diagnostics can most closely describe the issues, if any. */
enum aarch64_operand_error_kind
{
AARCH64_OPDE_NIL,
AARCH64_OPDE_RECOVERABLE,
AARCH64_OPDE_SYNTAX_ERROR,
AARCH64_OPDE_FATAL_SYNTAX_ERROR,
AARCH64_OPDE_INVALID_VARIANT,
AARCH64_OPDE_OUT_OF_RANGE,
AARCH64_OPDE_UNALIGNED,
AARCH64_OPDE_REG_LIST,
AARCH64_OPDE_OTHER_ERROR
};
/* N.B. GAS assumes that this structure work well with shallow copy. */
struct aarch64_operand_error
{
enum aarch64_operand_error_kind kind;
int index;
const char *error;
int data[3]; /* Some data for extra information. */
};
typedef struct aarch64_operand_error aarch64_operand_error;
/* Encoding entrypoint. */
extern int
aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
aarch64_insn *, aarch64_opnd_qualifier_t *,
aarch64_operand_error *);
extern const aarch64_opcode *
aarch64_replace_opcode (struct aarch64_inst *,
const aarch64_opcode *);
/* Given the opcode enumerator OP, return the pointer to the corresponding
opcode entry. */
extern const aarch64_opcode *
aarch64_get_opcode (enum aarch64_op);
/* Generate the string representation of an operand. */
extern void
aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
const aarch64_opnd_info *, int, int *, bfd_vma *);
/* Miscellaneous interface. */
extern int
aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
extern aarch64_opnd_qualifier_t
aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
const aarch64_opnd_qualifier_t, int);
extern int
aarch64_num_of_operands (const aarch64_opcode *);
extern int
aarch64_stack_pointer_p (const aarch64_opnd_info *);
extern
int aarch64_zero_register_p (const aarch64_opnd_info *);
/* Given an operand qualifier, return the expected data element size
of a qualified operand. */
extern unsigned char
aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
extern enum aarch64_operand_class
aarch64_get_operand_class (enum aarch64_opnd);
extern const char *
aarch64_get_operand_name (enum aarch64_opnd);
extern const char *
aarch64_get_operand_desc (enum aarch64_opnd);
#ifdef DEBUG_AARCH64
extern int debug_dump;
extern void
aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
#define DEBUG_TRACE(M, ...) \
{ \
if (debug_dump) \
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
}
#define DEBUG_TRACE_IF(C, M, ...) \
{ \
if (debug_dump && (C)) \
aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
}
#else /* !DEBUG_AARCH64 */
#define DEBUG_TRACE(M, ...) ;
#define DEBUG_TRACE_IF(C, M, ...) ;
#endif /* DEBUG_AARCH64 */
#endif /* OPCODE_AARCH64_H */

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/* alpha.h -- Header file for Alpha opcode table
Copyright 1996, 1999, 2001, 2003, 2010 Free Software Foundation, Inc.
Contributed by Richard Henderson <rth@tamu.edu>,
patterned after the PPC opcode table written by Ian Lance Taylor.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef OPCODE_ALPHA_H
#define OPCODE_ALPHA_H
/* The opcode table is an array of struct alpha_opcode. */
struct alpha_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned mask;
/* One bit flags for the opcode. These are primarily used to
indicate specific processors and environments support the
instructions. The defined values are listed below. */
unsigned flags;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[4];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct alpha_opcode alpha_opcodes[];
extern const unsigned alpha_num_opcodes;
/* Values defined for the flags field of a struct alpha_opcode. */
/* CPU Availability */
#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
/* A macro to extract the major opcode from an instruction. */
#define AXP_OP(i) (((i) >> 26) & 0x3F)
/* The total number of major opcodes. */
#define AXP_NOPS 0x40
/* The operands table is an array of struct alpha_operand. */
struct alpha_operand
{
/* The number of bits in the operand. */
unsigned int bits : 5;
/* How far the operand is left shifted in the instruction. */
unsigned int shift : 5;
/* The default relocation type for this operand. */
signed int default_reloc : 16;
/* One bit syntax flags. */
unsigned int flags : 16;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & AXP_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
int (*extract) (unsigned instruction, int *invalid);
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the alpha_opcodes table. */
extern const struct alpha_operand alpha_operands[];
extern const unsigned alpha_num_operands;
/* Values defined for the flags field of a struct alpha_operand. */
/* Mask for selecting the type for typecheck purposes */
#define AXP_OPERAND_TYPECHECK_MASK \
(AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \
AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \
AXP_OPERAND_UNSIGNED)
/* This operand does not actually exist in the assembler input. This
is used to support extended mnemonics, for which two operands fields
are identical. The assembler should call the insert function with
any op value. The disassembler should call the extract function,
ignore the return value, and check the value placed in the invalid
argument. */
#define AXP_OPERAND_FAKE 01
/* The operand should be wrapped in parentheses rather than separated
from the previous by a comma. This is used for the load and store
instructions which want their operands to look like "Ra,disp(Rb)". */
#define AXP_OPERAND_PARENS 02
/* Used in combination with PARENS, this supresses the supression of
the comma. This is used for "jmp Ra,(Rb),hint". */
#define AXP_OPERAND_COMMA 04
/* This operand names an integer register. */
#define AXP_OPERAND_IR 010
/* This operand names a floating point register. */
#define AXP_OPERAND_FPR 020
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define AXP_OPERAND_RELATIVE 040
/* This operand takes signed values. */
#define AXP_OPERAND_SIGNED 0100
/* This operand takes unsigned values. This exists primarily so that
a flags value of 0 can be treated as end-of-arguments. */
#define AXP_OPERAND_UNSIGNED 0200
/* Supress overflow detection on this field. This is used for hints. */
#define AXP_OPERAND_NOOVERFLOW 0400
/* Mask for optional argument default value. */
#define AXP_OPERAND_OPTIONAL_MASK 07000
/* This operand defaults to zero. This is used for jump hints. */
#define AXP_OPERAND_DEFAULT_ZERO 01000
/* This operand should default to the first (real) operand and is used
in conjunction with AXP_OPERAND_OPTIONAL. This allows
"and $0,3,$0" to be written as "and $0,3", etc. I don't like
it, but it's what DEC does. */
#define AXP_OPERAND_DEFAULT_FIRST 02000
/* Similarly, this operand should default to the second (real) operand.
This allows "negl $0" instead of "negl $0,$0". */
#define AXP_OPERAND_DEFAULT_SECOND 04000
/* Register common names */
#define AXP_REG_V0 0
#define AXP_REG_T0 1
#define AXP_REG_T1 2
#define AXP_REG_T2 3
#define AXP_REG_T3 4
#define AXP_REG_T4 5
#define AXP_REG_T5 6
#define AXP_REG_T6 7
#define AXP_REG_T7 8
#define AXP_REG_S0 9
#define AXP_REG_S1 10
#define AXP_REG_S2 11
#define AXP_REG_S3 12
#define AXP_REG_S4 13
#define AXP_REG_S5 14
#define AXP_REG_FP 15
#define AXP_REG_A0 16
#define AXP_REG_A1 17
#define AXP_REG_A2 18
#define AXP_REG_A3 19
#define AXP_REG_A4 20
#define AXP_REG_A5 21
#define AXP_REG_T8 22
#define AXP_REG_T9 23
#define AXP_REG_T10 24
#define AXP_REG_T11 25
#define AXP_REG_RA 26
#define AXP_REG_PV 27
#define AXP_REG_T12 27
#define AXP_REG_AT 28
#define AXP_REG_GP 29
#define AXP_REG_SP 30
#define AXP_REG_ZERO 31
#endif /* OPCODE_ALPHA_H */

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/* Opcode table for the ARC.
Copyright 1994, 1995, 1997, 2001, 2002, 2003, 2010
Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* List of the various cpu types.
The tables currently use bit masks to say whether the instruction or
whatever is supported by a particular cpu. This lets us have one entry
apply to several cpus.
The `base' cpu must be 0. The cpu type is treated independently of
endianness. The complete `mach' number includes endianness.
These values are internal to opcodes/bfd/binutils/gas. */
#define ARC_MACH_5 0
#define ARC_MACH_6 1
#define ARC_MACH_7 2
#define ARC_MACH_8 4
/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */
#define ARC_MACH_BIG 16
/* Mask of number of bits necessary to record cpu type. */
#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1)
/* Mask of number of bits necessary to record cpu type + endianness. */
#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1)
/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */
typedef unsigned int arc_insn;
struct arc_opcode {
char *syntax; /* syntax of insn */
unsigned long mask, value; /* recognize insn if (op&mask) == value */
int flags; /* various flag bits */
/* Values for `flags'. */
/* Return CPU number, given flag bits. */
#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
/* Return MACH number, given flag bits. */
#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
/* First opcode flag bit available after machine mask. */
#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1)
/* This insn is a conditional branch. */
#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1)
#define SYNTAX_LENGTH (SYNTAX_3OP )
#define SYNTAX_2OP (SYNTAX_3OP << 1)
#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1)
#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1)
#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1)
#define I(x) (((x) & 31) << 27)
#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
/* These values are used to optimize assembly and disassembly. Each insn
is on a list of related insns (same first letter for assembly, same
insn code for disassembly). */
struct arc_opcode *next_asm; /* Next instr to try during assembly. */
struct arc_opcode *next_dis; /* Next instr to try during disassembly. */
/* Macros to create the hash values for the lists. */
#define ARC_HASH_OPCODE(string) \
((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
#define ARC_HASH_ICODE(insn) \
((unsigned int) (insn) >> 27)
/* Macros to access `next_asm', `next_dis' so users needn't care about the
underlying mechanism. */
#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
};
/* this is an "insert at front" linked list per Metaware spec
that new definitions override older ones. */
extern struct arc_opcode *arc_ext_opcodes;
struct arc_operand_value {
char *name; /* eg: "eq" */
short value; /* eg: 1 */
unsigned char type; /* index into `arc_operands' */
unsigned char flags; /* various flag bits */
/* Values for `flags'. */
/* Return CPU number, given flag bits. */
#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
/* Return MACH number, given flag bits. */
#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
};
struct arc_ext_operand_value {
struct arc_ext_operand_value *next;
struct arc_operand_value operand;
};
extern struct arc_ext_operand_value *arc_ext_operands;
struct arc_operand {
/* One of the insn format chars. */
unsigned char fmt;
/* The number of bits in the operand (may be unused for a modifier). */
unsigned char bits;
/* How far the operand is left shifted in the instruction, or
the modifier's flag bit (may be unused for a modifier. */
unsigned char shift;
/* Various flag bits. */
int flags;
/* Values for `flags'. */
/* This operand is a suffix to the opcode. */
#define ARC_OPERAND_SUFFIX 1
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define ARC_OPERAND_RELATIVE_BRANCH 2
/* This operand is an absolute branch address. The disassembler
prints these symbolically if possible. */
#define ARC_OPERAND_ABSOLUTE_BRANCH 4
/* This operand is an address. The disassembler
prints these symbolically if possible. */
#define ARC_OPERAND_ADDRESS 8
/* This operand is a long immediate value. */
#define ARC_OPERAND_LIMM 0x10
/* This operand takes signed values. */
#define ARC_OPERAND_SIGNED 0x20
/* This operand takes signed values, but also accepts a full positive
range of values. That is, if bits is 16, it takes any value from
-0x8000 to 0xffff. */
#define ARC_OPERAND_SIGNOPT 0x40
/* This operand should be regarded as a negative number for the
purposes of overflow checking (i.e., the normal most negative
number is disallowed and one more than the normal most positive
number is allowed). This flag will only be set for a signed
operand. */
#define ARC_OPERAND_NEGATIVE 0x80
/* This operand doesn't really exist. The program uses these operands
in special ways. */
#define ARC_OPERAND_FAKE 0x100
/* separate flags operand for j and jl instructions */
#define ARC_OPERAND_JUMPFLAGS 0x200
/* allow warnings and errors to be issued after call to insert_xxxxxx */
#define ARC_OPERAND_WARN 0x400
#define ARC_OPERAND_ERROR 0x800
/* this is a load operand */
#define ARC_OPERAND_LOAD 0x8000
/* this is a store operand */
#define ARC_OPERAND_STORE 0x10000
/* Modifier values. */
/* A dot is required before a suffix. Eg: .le */
#define ARC_MOD_DOT 0x1000
/* A normal register is allowed (not used, but here for completeness). */
#define ARC_MOD_REG 0x2000
/* An auxiliary register name is expected. */
#define ARC_MOD_AUXREG 0x4000
/* Sum of all ARC_MOD_XXX bits. */
#define ARC_MOD_BITS 0x7000
/* Non-zero if the operand type is really a modifier. */
#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
/* enforce read/write only register restrictions */
#define ARC_REGISTER_READONLY 0x01
#define ARC_REGISTER_WRITEONLY 0x02
#define ARC_REGISTER_NOSHORT_CUT 0x04
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (p & ((1 << o->bits) - 1)) << o->shift;
(I is the instruction which we are filling in, O is a pointer to
this structure, and OP is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged.
REG is non-NULL when inserting a register value. */
arc_insn (*insert)
(arc_insn insn, const struct arc_operand *operand, int mods,
const struct arc_operand_value *reg, long value, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & ARC_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(I is the instruction, O is a pointer to this structure, and OP
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed.
INSN is a pointer to an array of two `arc_insn's. The first element is
the insn, the second is the limm if present.
Operands that have a printable form like registers and suffixes have
their struct arc_operand_value pointer stored in OPVAL. */
long (*extract)
(arc_insn *insn, const struct arc_operand *operand, int mods,
const struct arc_operand_value **opval, int *invalid);
};
/* Bits that say what version of cpu we have. These should be passed to
arc_init_opcode_tables. At present, all there is is the cpu type. */
/* CPU number, given value passed to `arc_init_opcode_tables'. */
#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
/* MACH number, given value passed to `arc_init_opcode_tables'. */
#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
/* Special register values: */
#define ARC_REG_SHIMM_UPDATE 61
#define ARC_REG_SHIMM 63
#define ARC_REG_LIMM 62
/* Non-zero if REG is a constant marker. */
#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
/* Positions and masks of various fields: */
#define ARC_SHIFT_REGA 21
#define ARC_SHIFT_REGB 15
#define ARC_SHIFT_REGC 9
#define ARC_MASK_REG 63
/* Delay slot types. */
#define ARC_DELAY_NONE 0 /* no delay slot */
#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */
#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */
/* Non-zero if X will fit in a signed 9 bit field. */
#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
extern const struct arc_operand arc_operands[];
extern const int arc_operand_count;
extern struct arc_opcode arc_opcodes[];
extern const int arc_opcodes_count;
extern const struct arc_operand_value arc_suffixes[];
extern const int arc_suffixes_count;
extern const struct arc_operand_value arc_reg_names[];
extern const int arc_reg_names_count;
extern unsigned char arc_operand_map[];
/* Utility fns in arc-opc.c. */
int arc_get_opcode_mach (int, int);
/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */
void arc_opcode_init_tables (int);
void arc_opcode_init_insert (void);
void arc_opcode_init_extract (void);
const struct arc_opcode *arc_opcode_lookup_asm (const char *);
const struct arc_opcode *arc_opcode_lookup_dis (unsigned int);
int arc_opcode_limm_p (long *);
const struct arc_operand_value *arc_opcode_lookup_suffix
(const struct arc_operand *type, int value);
int arc_opcode_supported (const struct arc_opcode *);
int arc_opval_supported (const struct arc_operand_value *);
int arc_limm_fixup_adjust (arc_insn);
int arc_insn_is_j (arc_insn);
int arc_insn_not_jl (arc_insn);
int arc_operand_type (int);
struct arc_operand_value *get_ext_suffix (char *);
int arc_get_noshortcut_flag (void);

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/* ARM assembler/disassembler support.
Copyright 2004, 2010, 2011 Free Software Foundation, Inc.
This file is part of GDB and GAS.
GDB and GAS are free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3, or (at
your option) any later version.
GDB and GAS are distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB or GAS; see the file COPYING3. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* The following bitmasks control CPU extensions: */
#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
#define ARM_EXT_V4T 0x00000040 /* Thumb. */
#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
#define ARM_EXT_V6 0x00001000 /* ARM V6. */
#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
/* 0x00004000 Was ARM V6Z. */
#define ARM_EXT_V8 0x00004000 /* is now ARMv8. */
#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
#define ARM_EXT_DIV 0x00010000 /* Integer division. */
/* The 'M' in Arm V7M stands for Microcontroller.
On earlier architecture variants it stands for Multiply. */
#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
#define ARM_EXT_V7 0x00080000 /* Arm V7. */
#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
not in v7-M. */
#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
state. */
#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
#define FPU_VFP_EXT_ARMV8 0x00020000 /* FP for ARMv8. */
#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */
#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
three more to cover cores prior to ARM6. Finally, there are cores which
implement further extensions in the co-processor space. */
#define ARM_AEXT_V1 ARM_EXT_V1
#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2)
#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S)
#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3)
#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
| ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
| ARM_EXT_V6_DSP )
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \
| ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
(ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
| ARM_EXT_V6_DSP )
#define ARM_AEXT_V6M_ONLY \
((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V6M \
((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
#define ARM_AEXT_V7M \
((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
& ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
#define ARM_AEXT_V7EM \
(ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
#define ARM_AEXT_V8A \
(ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
| ARM_EXT_VIRT | ARM_EXT_V8)
/* Processors with specific extensions in the co-processor space. */
#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
#define ARM_ARCH_IWMMXT \
ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
#define ARM_ARCH_IWMMXT2 \
ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
#define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8)
#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8)
#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
| FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
/* Deprecated. */
#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
#define FPU_ARCH_VFP_V3D16_FP16 \
ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD)
#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16)
#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
#define FPU_ARCH_NEON_FP16 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
#define FPU_ARCH_NEON_VFP_V4 \
ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE(0, FPU_VFP_ARMV8)
#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE(0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
ARM_FEATURE(0, FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define ARCH_CRC_ARMV8 ARM_FEATURE(0, CRC_EXT_ARMV8)
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0)
#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
#define ARM_ARCH_V7VE ARM_FEATURE (ARM_AEXT_V7VE, 0)
#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0)
#define ARM_ARCH_V8A ARM_FEATURE (ARM_AEXT_V8A, 0)
/* Some useful combinations: */
#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
#define FPU_NONE ARM_FEATURE (0, 0)
#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
/* v7-a+sec. */
#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
/* v7-a+mp+sec. */
#define ARM_ARCH_V7A_MP_SEC \
ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
0)
/* v7-r+idiv. */
#define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0)
/* Features that are present in v6M and v6S-M but not other v6 cores. */
#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0)
/* v8-a+fp. */
#define ARM_ARCH_V8A_FP ARM_FEATURE (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
/* v8-a+simd (implies fp). */
#define ARM_ARCH_V8A_SIMD ARM_FEATURE (ARM_AEXT_V8A, \
FPU_ARCH_NEON_VFP_ARMV8)
/* v8-a+crypto (implies simd+fp). */
#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, \
FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and
everything else in the other. */
typedef struct
{
unsigned long core;
unsigned long coproc;
} arm_feature_set;
#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
(((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
#define ARM_CPU_IS_ANY(CPU) \
((CPU).core == ((arm_feature_set)ARM_ANY).core)
#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
do { \
(TARG).core = (F1).core | (F2).core; \
(TARG).coproc = (F1).coproc | (F2).coproc; \
} while (0)
#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
do { \
(TARG).core = (F1).core &~ (F2).core; \
(TARG).coproc = (F1).coproc &~ (F2).coproc; \
} while (0)
#define ARM_FEATURE(core, coproc) {(core), (coproc)}

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/* Opcode table for the Atmel AVR micro controllers.
Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc.
Contributed by Denis Chertykov <denisc@overta.ru>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#define AVR_ISA_1200 0x0001 /* In the beginning there was ... */
#define AVR_ISA_LPM 0x0002 /* device has LPM */
#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */
#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL
supported, no 8K wrap on RJMP and RCALL) */
#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */
#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */
#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */
#define AVR_ISA_SPM 0x0200 /* device can program itself */
#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */
#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */
#define AVR_ISA_MOVW 0x1000 /* device has MOVW */
#define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */
#define AVR_ISA_DES 0x4000 /* device has DES */
#define AVR_ISA_RMW 0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */
#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
/* For the attiny26 which is missing LPM Rd,Z+. */
#define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX)
#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \
AVR_ISA_SPM | AVR_ISA_BRK)
#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA)
#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM)
#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_PWMx (AVR_ISA_M8 | AVR_ISA_BRK)
#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM)
#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX)
#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK)
#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
#define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND)
#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
#define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW)
#define AVR_ISA_AVR1 AVR_ISA_TINY1
#define AVR_ISA_AVR2 AVR_ISA_2xxx
#define AVR_ISA_AVR25 AVR_ISA_TINY2
#define AVR_ISA_AVR3 AVR_ISA_M603
#define AVR_ISA_AVR31 AVR_ISA_M103
#define AVR_ISA_AVR35 (AVR_ISA_AVR3 | AVR_ISA_MOVW | \
AVR_ISA_LPMX | AVR_ISA_SPM | AVR_ISA_BRK)
#define AVR_ISA_AVR3_ALL (AVR_ISA_AVR3 | AVR_ISA_AVR31 | AVR_ISA_AVR35)
#define AVR_ISA_AVR4 AVR_ISA_PWMx
#define AVR_ISA_AVR5 AVR_ISA_M323
#define AVR_ISA_AVR51 AVR_ISA_M128
#define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \
AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \
AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW)
#define REGISTER_P(x) ((x) == 'r' \
|| (x) == 'd' \
|| (x) == 'w' \
|| (x) == 'a' \
|| (x) == 'v')
/* Undefined combination of operands - does the register
operand overlap with pre-decremented or post-incremented
pointer register (like ld r31,Z+)? */
#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \
((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \
((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \
((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2)
/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */
#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \
((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00)
/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as
`ld r,b' or `st b,r' respectively - next opcode entry)? */
#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
/* constraint letters
r - any register
d - `ldi' register (r16-r31)
v - `movw' even register (r0, r2, ..., r28, r30)
a - `fmul' register (r16-r23)
w - `adiw' register (r24,r26,r28,r30)
e - pointer registers (X,Y,Z)
b - base pointer register and displacement ([YZ]+disp)
z - Z pointer register (for [e]lpm Rd,Z[+])
M - immediate value from 0 to 255
n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
s - immediate value from 0 to 7
P - Port address value from 0 to 63. (in, out)
p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
K - immediate value from 0 to 63 (used in `adiw', `sbiw')
i - immediate value
l - signed pc relative offset from -64 to 63
L - signed pc relative offset from -2048 to 2047
h - absolute code address (call, jmp)
S - immediate value from 0 to 7 (S = s << 4)
E - immediate value from 0 to 15, shifted left by 4 (des)
? - use this opcode entry if no parameters, else use next opcode entry
Order is important - some binary opcodes have more than one name,
the disassembler will only see the first match.
Remaining undefined opcodes (1699 total - some of them might work
as normal instructions if not all of the bits are decoded):
0x0001...0x00ff (255) (known to be decoded as `nop' by the old core)
"100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b]
"100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8
"1001010xxxxx0100" (32) 0x9[45][0-9a-f]4
"1001010x001x1001" (4) 0x9[45][23]9
"1001010x01xx1001" (8) 0x9[45][4-7]9
"1001010x1xxx1001" (16) 0x9[45][8-9a-f]9
"1001010xxxxx1011" (32) 0x9[45][0-9a-f]b
"10010101001x1000" (2) 0x95[23]8
"1001010101xx1000" (4) 0x95[4-7]8
"1001010110111000" (1) 0x95b8
"1001010111111000" (1) 0x95f8 (`espm' removed in databook update)
"11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f]
*/
AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488)
AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8)
AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8)
AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8)
AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8)
AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8)
AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8)
AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498)
AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408)
AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458)
AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478)
AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428)
AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448)
AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468)
AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438)
AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418)
/* Same as {cl,se}[chinstvz] above. */
AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8)
AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006)
AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000)
AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508)
AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518)
AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588)
AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598)
AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8)
AVR_INSN (spm, "?", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8)
AVR_INSN (spm, "z", "10010101111+1000", 1, AVR_ISA_SPMX, 0x95e8)
AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400)
AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400)
AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000)
AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00)
AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00)
AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800)
AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800)
AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800)
/* Shorthand for {eor,add,adc,and} r,r above. */
AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400)
AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00)
AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00)
AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000)
AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
/*XXX special case*/
AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000)
AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f)
AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000)
AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000)
AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000)
AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000)
AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00)
AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00)
AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800)
AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00)
AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000)
AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800)
AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600)
AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700)
AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800)
AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00)
AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900)
AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00)
AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001)
AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404)
AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405)
AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005)
AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407)
AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007)
AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000)
AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004)
AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002)
AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401)
AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402)
AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400)
AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406)
AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006)
AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403)
AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003)
/* Same as br?? above. */
AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400)
AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000)
AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000)
AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000)
AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e)
AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c)
AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405)
AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400)
AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
/* Atomic memory operations for XMEGA. List before `sts'. */
AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204)
AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205)
AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206)
AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207)
/* Known to be decoded as `nop' by the old core. */
AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)
AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200)
AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300)
AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308)
AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380)
AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388)
AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
/* Special case for b+0, `e' must be next entry after `b',
b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */
AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000)
AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000)
AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200)
AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
/* These are for devices that don't exist yet
(>128K program memory, PC = EIND:Z). */
AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
/* DES instruction for encryption and decryption */
AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B)

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/* cr16.h -- Header file for CR16 opcode and register tables.
Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc.
Contributed by M R Swami Reddy
This file is part of GAS, GDB and the GNU binutils.
GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3, or (at your
option) any later version.
GAS, GDB, and GNU binutils are distributed in the hope that they will be
useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef _CR16_H_
#define _CR16_H_
/* CR16 core Registers :
The enums are used as indices to CR16 registers table (cr16_regtab).
Therefore, order MUST be preserved. */
typedef enum
{
/* 16-bit general purpose registers. */
r0, r1, r2, r3,
r4, r5, r6, r7,
r8, r9, r10, r11,
r12_L = 12, r13_L = 13, ra = 14, sp_L = 15,
/* 32-bit general purpose registers. */
r12 = 12, r13 = 13, r14 = 14, r15 = 15,
era = 14, sp = 15, RA,
/* Not a register. */
nullregister,
MAX_REG
}
reg;
/* CR16 processor registers and special registers :
The enums are used as indices to CR16 processor registers table
(cr16_pregtab). Therefore, order MUST be preserved. */
typedef enum
{
/* processor registers. */
dbs = MAX_REG,
dsr, dcrl, dcrh,
car0l, car0h, car1l, car1h,
cfg, psr, intbasel, intbaseh,
ispl, isph, uspl, usph,
dcr = dcrl,
car0 = car0l,
car1 = car1l,
intbase = intbasel,
isp = ispl,
usp = uspl,
/* Not a processor register. */
nullpregister = usph + 1,
MAX_PREG
}
preg;
/* CR16 Register types. */
typedef enum
{
CR16_R_REGTYPE, /* r<N> */
CR16_RP_REGTYPE, /* reg pair */
CR16_P_REGTYPE /* Processor register */
}
reg_type;
/* CR16 argument types :
The argument types correspond to instructions operands
Argument types :
r - register
rp - register pair
c - constant
i - immediate
idxr - index with register
idxrp - index with register pair
rbase - register base
rpbase - register pair base
pr - processor register. */
typedef enum
{
arg_r,
arg_c,
arg_cr,
arg_crp,
arg_ic,
arg_icr,
arg_idxr,
arg_idxrp,
arg_rbase,
arg_rpbase,
arg_rp,
arg_pr,
arg_prp,
arg_cc,
arg_ra,
/* Not an argument. */
nullargs
}
argtype;
/* CR16 operand types:The operand types correspond to instructions operands. */
typedef enum
{
dummy,
/* N-bit signed immediate. */
imm3, imm4, imm5, imm6, imm16, imm20, imm32,
/* N-bit unsigned immediate. */
uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32,
/* N-bit signed displacement. */
disps5, disps17, disps25,
/* N-bit unsigned displacement. */
dispe9,
/* N-bit absolute address. */
abs20, abs24,
/* Register relative. */
rra, rbase, rbase_disps20, rbase_dispe20,
/* Register pair relative. */
rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16,
rpbase_disps20, rpbase_dispe20,
/* Register index. */
rindex7_abs20, rindex8_abs20,
/* Register pair index. */
rpindex_disps0, rpindex_disps14, rpindex_disps20,
/* register. */
regr,
/* register pair. */
regp,
/* processor register. */
pregr,
/* processor register 32 bit. */
pregrp,
/* condition code - 4 bit. */
cc,
/* Not an operand. */
nulloperand,
/* Maximum supported operand. */
MAX_OPRD
}
operand_type;
/* CR16 instruction types. */
#define NO_TYPE_INS 0
#define ARITH_INS 1
#define LD_STOR_INS 2
#define BRANCH_INS 3
#define ARITH_BYTE_INS 4
#define SHIFT_INS 5
#define BRANCH_NEQ_INS 6
#define LD_STOR_INS_INC 7
#define STOR_IMM_INS 8
#define CSTBIT_INS 9
/* Maximum value supported for instruction types. */
#define CR16_INS_MAX (1 << 4)
/* Mask to record an instruction type. */
#define CR16_INS_MASK (CR16_INS_MAX - 1)
/* Return instruction type, given instruction's attributes. */
#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK)
/* Indicates whether this instruction has a register list as parameter. */
#define REG_LIST CR16_INS_MAX
/* The operands in binary and assembly are placed in reverse order.
load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
#define REVERSE_MATCH (1 << 5)
/* Printing formats, where the instruction prefix isn't consecutive. */
#define FMT_1 (1 << 9) /* 0xF0F00000 */
#define FMT_2 (1 << 10) /* 0xFFF0FF00 */
#define FMT_3 (1 << 11) /* 0xFFF00F00 */
#define FMT_4 (1 << 12) /* 0xFFF0F000 */
#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */
#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
/* Indicates whether this instruction can be relaxed. */
#define RELAXABLE (1 << 14)
/* Indicates that instruction uses user registers (and not
general-purpose registers) as operands. */
#define USER_REG (1 << 15)
/* Instruction shouldn't allow 'sp' usage. */
#define NO_SP (1 << 17)
/* Instruction shouldn't allow to push a register which is used as a rptr. */
#define NO_RPTR (1 << 18)
/* Maximum operands per instruction. */
#define MAX_OPERANDS 5
/* Maximum register name length. */
#define MAX_REGNAME_LEN 10
/* Maximum instruction length. */
#define MAX_INST_LEN 256
/* Values defined for the flags field of a struct operand_entry. */
/* Operand must be an unsigned number. */
#define OP_UNSIGNED (1 << 0)
/* Operand must be a signed number. */
#define OP_SIGNED (1 << 1)
/* Operand must be a negative number. */
#define OP_NEG (1 << 2)
/* A special load/stor 4-bit unsigned displacement operand. */
#define OP_DEC (1 << 3)
/* Operand must be an even number. */
#define OP_EVEN (1 << 4)
/* Operand is shifted right. */
#define OP_SHIFT (1 << 5)
/* Operand is shifted right and decremented. */
#define OP_SHIFT_DEC (1 << 6)
/* Operand has reserved escape sequences. */
#define OP_ESC (1 << 7)
/* Operand must be a ABS20 number. */
#define OP_ABS20 (1 << 8)
/* Operand must be a ABS24 number. */
#define OP_ABS24 (1 << 9)
/* Operand has reserved escape sequences type 1. */
#define OP_ESC1 (1 << 10)
/* Single operand description. */
typedef struct
{
/* Operand type. */
operand_type op_type;
/* Operand location within the opcode. */
unsigned int shift;
}
operand_desc;
/* Instruction data structure used in instruction table. */
typedef struct
{
/* Name. */
const char *mnemonic;
/* Size (in words). */
unsigned int size;
/* Constant prefix (matched by the disassembler). */
unsigned long match; /* ie opcode */
/* Match size (in bits). */
/* MASK: if( (i & match_bits) == match ) then match */
int match_bits;
/* Attributes. */
unsigned int flags;
/* Operands (always last, so unreferenced operands are initialized). */
operand_desc operands[MAX_OPERANDS];
}
inst;
/* Data structure for a single instruction's arguments (Operands). */
typedef struct
{
/* Register or base register. */
reg r;
/* Register pair register. */
reg rp;
/* Index register. */
reg i_r;
/* Processor register. */
preg pr;
/* Processor register. 32 bit */
preg prp;
/* Constant/immediate/absolute value. */
long constant;
/* CC code. */
unsigned int cc;
/* Scaled index mode. */
unsigned int scale;
/* Argument type. */
argtype type;
/* Size of the argument (in bits) required to represent. */
int size;
/* The type of the expression. */
unsigned char X_op;
}
argument;
/* Internal structure to hold the various entities
corresponding to the current assembling instruction. */
typedef struct
{
/* Number of arguments. */
int nargs;
/* The argument data structure for storing args (operands). */
argument arg[MAX_OPERANDS];
/* The following fields are required only by CR16-assembler. */
#ifdef TC_CR16
/* Expression used for setting the fixups (if any). */
expressionS exp;
bfd_reloc_code_real_type rtype;
#endif /* TC_CR16 */
/* Instruction size (in bytes). */
int size;
}
ins;
/* Structure to hold information about predefined operands. */
typedef struct
{
/* Size (in bits). */
unsigned int bit_size;
/* Argument type. */
argtype arg_type;
/* One bit syntax flags. */
int flags;
}
operand_entry;
/* Structure to hold trap handler information. */
typedef struct
{
/* Trap name. */
char *name;
/* Index in dispatch table. */
unsigned int entry;
}
trap_entry;
/* Structure to hold information about predefined registers. */
typedef struct
{
/* Name (string representation). */
char *name;
/* Value (enum representation). */
union
{
/* Register. */
reg reg_val;
/* processor register. */
preg preg_val;
} value;
/* Register image. */
int image;
/* Register type. */
reg_type type;
}
reg_entry;
/* CR16 opcode table. */
extern const inst cr16_instruction[];
extern const unsigned int cr16_num_opcodes;
#define NUMOPCODES cr16_num_opcodes
/* CR16 operands table. */
extern const operand_entry cr16_optab[];
extern const unsigned int cr16_num_optab;
/* CR16 registers table. */
extern const reg_entry cr16_regtab[];
extern const unsigned int cr16_num_regs;
#define NUMREGS cr16_num_regs
/* CR16 register pair table. */
extern const reg_entry cr16_regptab[];
extern const unsigned int cr16_num_regps;
#define NUMREGPS cr16_num_regps
/* CR16 processor registers table. */
extern const reg_entry cr16_pregtab[];
extern const unsigned int cr16_num_pregs;
#define NUMPREGS cr16_num_pregs
/* CR16 processor registers - 32 bit table. */
extern const reg_entry cr16_pregptab[];
extern const unsigned int cr16_num_pregps;
#define NUMPREGPS cr16_num_pregps
/* CR16 trap/interrupt table. */
extern const trap_entry cr16_traps[];
extern const unsigned int cr16_num_traps;
#define NUMTRAPS cr16_num_traps
/* CR16 CC - codes bit table. */
extern const char * cr16_b_cond_tab[];
extern const unsigned int cr16_num_cc;
#define NUMCC cr16_num_cc;
/* Table of instructions with no operands. */
extern const char * cr16_no_op_insn[];
/* Current instruction we're assembling. */
extern const inst *instruction;
/* A macro for representing the instruction "constant" opcode, that is,
the FIXED part of the instruction. The "constant" opcode is represented
as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
over that range. */
#define BIN(OPC,SHIFT) (OPC << SHIFT)
/* Is the current instruction type is TYPE ? */
#define IS_INSN_TYPE(TYPE) \
(CR16_INS_TYPE (instruction->flags) == TYPE)
/* Is the current instruction mnemonic is MNEMONIC ? */
#define IS_INSN_MNEMONIC(MNEMONIC) \
(strcmp (instruction->mnemonic, MNEMONIC) == 0)
/* Does the current instruction has register list ? */
#define INST_HAS_REG_LIST \
(instruction->flags & REG_LIST)
/* Utility macros for string comparison. */
#define streq(a, b) (strcmp (a, b) == 0)
#define strneq(a, b, c) (strncmp (a, b, c) == 0)
/* Long long type handling. */
/* Replace all appearances of 'long long int' with LONGLONG. */
typedef long long int LONGLONG;
typedef unsigned long long ULONGLONG;
/* Data types for opcode handling. */
typedef unsigned long dwordU;
typedef unsigned short wordU;
/* Globals to store opcode data and build the instruction. */
extern wordU cr16_words[3];
extern ULONGLONG cr16_allWords;
extern ins cr16_currInsn;
/* Prototypes for function in cr16-dis.c. */
extern void cr16_make_instruction (void);
extern int cr16_match_opcode (void);
#endif /* _CR16_H_ */

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/* cris.h -- Header file for CRIS opcode and register tables.
Copyright (C) 2000, 2001, 2004, 2010 Free Software Foundation, Inc.
Contributed by Axis Communications AB, Lund, Sweden.
Originally written for GAS 1.38.1 by Mikael Asker.
Updated, BFDized and GNUified by Hans-Peter Nilsson.
This file is part of GAS, GDB and the GNU binutils.
GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3, or (at your
option) any later version.
GAS, GDB, and GNU binutils are distributed in the hope that they will be
useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef __CRIS_H_INCLUDED_
#define __CRIS_H_INCLUDED_
#if !defined(__STDC__) && !defined(const)
#define const
#endif
/* Registers. */
#define MAX_REG (15)
#define REG_SP (14)
#define REG_PC (15)
/* CPU version control of disassembly and assembly of instructions.
May affect how the instruction is assembled, at least the size of
immediate operands. */
enum cris_insn_version_usage
{
/* Any version. */
cris_ver_version_all=0,
/* Indeterminate (intended for disassembly only, or obsolete). */
cris_ver_warning,
/* Only for v0..3 (Etrax 1..4). */
cris_ver_v0_3,
/* Only for v3 or higher (ETRAX 4 and beyond). */
cris_ver_v3p,
/* Only for v8 (Etrax 100). */
cris_ver_v8,
/* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
cris_ver_v8p,
/* Only for v0..10. FIXME: Not sure what to do with this. */
cris_ver_sim_v0_10,
/* Only for v0..10. */
cris_ver_v0_10,
/* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
cris_ver_v3_10,
/* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
cris_ver_v8_10,
/* Only for v10 (ETRAX 100 LX) and same series. */
cris_ver_v10,
/* Only for v10 (ETRAX 100 LX) and same series. */
cris_ver_v10p,
/* Only for v32 or higher (codename GUINNESS).
Of course some or all these of may change to cris_ver_v32p if/when
there's a new revision. */
cris_ver_v32p
};
/* Special registers. */
struct cris_spec_reg
{
const char *const name;
unsigned int number;
/* The size of the register. */
unsigned int reg_size;
/* What CPU version the special register of that name is implemented
in. If cris_ver_warning, emit an unimplemented-warning. */
enum cris_insn_version_usage applicable_version;
/* There might be a specific warning for using a special register
here. */
const char *const warning;
};
extern const struct cris_spec_reg cris_spec_regs[];
/* Support registers (kind of special too, but not named as such). */
struct cris_support_reg
{
const char *const name;
unsigned int number;
};
extern const struct cris_support_reg cris_support_regs[];
struct cris_cond15
{
/* The name of the condition. */
const char *const name;
/* What CPU version this condition name applies to. */
enum cris_insn_version_usage applicable_version;
};
extern const struct cris_cond15 cris_conds15[];
/* Opcode-dependent constants. */
#define AUTOINCR_BIT (0x04)
/* Prefixes. */
#define BDAP_QUICK_OPCODE (0x0100)
#define BDAP_QUICK_Z_BITS (0x0e00)
#define BIAP_OPCODE (0x0540)
#define BIAP_Z_BITS (0x0a80)
#define DIP_OPCODE (0x0970)
#define DIP_Z_BITS (0xf280)
#define BDAP_INDIR_LOW (0x40)
#define BDAP_INDIR_LOW_Z (0x80)
#define BDAP_INDIR_HIGH (0x09)
#define BDAP_INDIR_HIGH_Z (0x02)
#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC)
#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT)
/* No prefix must have this code for its "match" bits in the
opcode-table. "BCC .+2" will do nicely. */
#define NO_CRIS_PREFIX 0
/* Definitions for condition codes. */
#define CC_CC 0x0
#define CC_HS 0x0
#define CC_CS 0x1
#define CC_LO 0x1
#define CC_NE 0x2
#define CC_EQ 0x3
#define CC_VC 0x4
#define CC_VS 0x5
#define CC_PL 0x6
#define CC_MI 0x7
#define CC_LS 0x8
#define CC_HI 0x9
#define CC_GE 0xA
#define CC_LT 0xB
#define CC_GT 0xC
#define CC_LE 0xD
#define CC_A 0xE
#define CC_EXT 0xF
/* A table of strings "cc", "cs"... indexed with condition code
values as above. */
extern const char *const cris_cc_strings[];
/* Bcc quick. */
#define BRANCH_QUICK_LOW (0)
#define BRANCH_QUICK_HIGH (0)
#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
#define BRANCH_QUICK_Z_BITS (0x0F00)
/* BA quick. */
#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
/* Bcc [PC+]. */
#define BRANCH_PC_LOW (0xFF)
#define BRANCH_INCR_HIGH (0x0D)
#define BA_PC_INCR_OPCODE \
((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
/* Jump. */
/* Note that old versions generated special register 8 (in high bits)
and not-that-old versions recognized it as a jump-instruction.
That opcode now belongs to JUMPU. */
#define JUMP_INDIR_OPCODE (0x0930)
#define JUMP_INDIR_Z_BITS (0xf2c0)
#define JUMP_PC_INCR_OPCODE \
(JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
#define MOVE_M_TO_PREG_OPCODE 0x0a30
#define MOVE_M_TO_PREG_ZBITS 0x01c0
/* BDAP.D N,PC. */
#define MOVE_PC_INCR_OPCODE_PREFIX \
(((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
#define MOVE_PC_INCR_OPCODE_SUFFIX \
(MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
/* BA DWORD (V32). */
#define BA_DWORD_OPCODE (0x0EBF)
/* Nop. */
#define NOP_OPCODE (0x050F)
#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
#define NOP_OPCODE_V32 (0x05B0)
#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
registers or flags. Unfortunately shuts off interrupts for one cycle
for < v32, but there doesn't seem to be any alternative without that
effect. */
#define NOP_OPCODE_COMMON (0x630)
#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
/* LAPC.D */
#define LAPC_DWORD_OPCODE (0x0D7F)
#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
/* Structure of an opcode table entry. */
enum cris_imm_oprnd_size_type
{
/* No size is applicable. */
SIZE_NONE,
/* Always 32 bits. */
SIZE_FIX_32,
/* Indicated by size of special register. */
SIZE_SPEC_REG,
/* Indicated by size field, signed. */
SIZE_FIELD_SIGNED,
/* Indicated by size field, unsigned. */
SIZE_FIELD_UNSIGNED,
/* Indicated by size field, no sign implied. */
SIZE_FIELD
};
/* For GDB. FIXME: Is this the best way to handle opcode
interpretation? */
enum cris_op_type
{
cris_not_implemented_op = 0,
cris_abs_op,
cris_addi_op,
cris_asr_op,
cris_asrq_op,
cris_ax_ei_setf_op,
cris_bdap_prefix,
cris_biap_prefix,
cris_break_op,
cris_btst_nop_op,
cris_clearf_di_op,
cris_dip_prefix,
cris_dstep_logshift_mstep_neg_not_op,
cris_eight_bit_offset_branch_op,
cris_move_mem_to_reg_movem_op,
cris_move_reg_to_mem_movem_op,
cris_move_to_preg_op,
cris_muls_op,
cris_mulu_op,
cris_none_reg_mode_add_sub_cmp_and_or_move_op,
cris_none_reg_mode_clear_test_op,
cris_none_reg_mode_jump_op,
cris_none_reg_mode_move_from_preg_op,
cris_quick_mode_add_sub_op,
cris_quick_mode_and_cmp_move_or_op,
cris_quick_mode_bdap_prefix,
cris_reg_mode_add_sub_cmp_and_or_move_op,
cris_reg_mode_clear_op,
cris_reg_mode_jump_op,
cris_reg_mode_move_from_preg_op,
cris_reg_mode_test_op,
cris_scc_op,
cris_sixteen_bit_offset_branch_op,
cris_three_operand_add_sub_cmp_and_or_op,
cris_three_operand_bound_op,
cris_two_operand_bound_op,
cris_xor_op
};
struct cris_opcode
{
/* The name of the insn. */
const char *name;
/* Bits that must be 1 for a match. */
unsigned int match;
/* Bits that must be 0 for a match. */
unsigned int lose;
/* See the table in "opcodes/cris-opc.c". */
const char *args;
/* Nonzero if this is a delayed branch instruction. */
char delayed;
/* Size of immediate operands. */
enum cris_imm_oprnd_size_type imm_oprnd_size;
/* Indicates which version this insn was first implemented in. */
enum cris_insn_version_usage applicable_version;
/* What kind of operation this is. */
enum cris_op_type op;
};
extern const struct cris_opcode cris_opcodes[];
/* These macros are for the target-specific flags in disassemble_info
used at disassembly. */
/* This insn accesses memory. This flag is more trustworthy than
checking insn_type for "dis_dref" which does not work for
e.g. "JSR [foo]". */
#define CRIS_DIS_FLAG_MEMREF (1 << 0)
/* The "target" field holds a register number. */
#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
/* The "target2" field holds a register number; add it to "target". */
#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
/* Yet another add-on: the register in "target2" must be multiplied
by 2 before adding to "target". */
#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
/* Yet another add-on: the register in "target2" must be multiplied
by 4 (mutually exclusive with .._MULT2). */
#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
/* The register in "target2" is an indirect memory reference (of the
register there), add to "target". Assumed size is dword (mutually
exclusive with .._MULT[24]). */
#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
sign-extended before adding to "target". */
#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
sign-extended before adding to "target". */
#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
#endif /* __CRIS_H_INCLUDED_ */
/*
* Local variables:
* eval: (c-set-style "gnu")
* indent-tabs-mode: t
* End:
*/

419
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/* crx.h -- Header file for CRX opcode and register tables.
Copyright 2004, 2010, 2012 Free Software Foundation, Inc.
Contributed by Tomer Levi, NSC, Israel.
Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
This file is part of GAS, GDB and the GNU binutils.
GAS, GDB, and GNU binutils is free software; you can redistribute it
and/or modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3, or (at your
option) any later version.
GAS, GDB, and GNU binutils are distributed in the hope that they will be
useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef _CRX_H_
#define _CRX_H_
/* CRX core/debug Registers :
The enums are used as indices to CRX registers table (crx_regtab).
Therefore, order MUST be preserved. */
typedef enum
{
/* 32-bit general purpose registers. */
r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
r10, r11, r12, r13, r14, r15, ra, sp,
/* 32-bit user registers. */
u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
u10, u11, u12, u13, u14, u15, ura, usp,
/* hi and lo registers. */
hi, lo,
/* hi and lo user registers. */
uhi, ulo,
/* Processor Status Register. */
psr,
/* Interrupt Base Register. */
intbase,
/* Interrupt Stack Pointer Register. */
isp,
/* Configuration Register. */
cfg,
/* Coprocessor Configuration Register. */
cpcfg,
/* Coprocessor Enable Register. */
cen,
/* Not a register. */
nullregister,
MAX_REG
}
reg;
/* CRX Coprocessor registers and special registers :
The enums are used as indices to CRX coprocessor registers table
(crx_copregtab). Therefore, order MUST be preserved. */
typedef enum
{
/* Coprocessor registers. */
c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
c9, c10, c11, c12, c13, c14, c15,
/* Coprocessor special registers. */
cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
cs9, cs10, cs11, cs12, cs13, cs14, cs15,
/* Not a Coprocessor register. */
nullcopregister,
MAX_COPREG
}
copreg;
/* CRX Register types. */
typedef enum
{
CRX_R_REGTYPE, /* r<N> */
CRX_U_REGTYPE, /* u<N> */
CRX_C_REGTYPE, /* c<N> */
CRX_CS_REGTYPE, /* cs<N> */
CRX_CFG_REGTYPE /* configuration register */
}
reg_type;
/* CRX argument types :
The argument types correspond to instructions operands
Argument types :
r - register
c - constant
i - immediate
idxr - index register
rbase - register base
s - star ('*')
copr - coprocessor register
copsr - coprocessor special register. */
typedef enum
{
arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc,
arg_idxr, arg_rbase, arg_copr, arg_copsr,
/* Not an argument. */
nullargs
}
argtype;
/* CRX operand types :
The operand types correspond to instructions operands. */
typedef enum
{
dummy,
/* 4-bit encoded constant. */
cst4,
/* N-bit immediate. */
i16, i32,
/* N-bit unsigned immediate. */
ui3, ui4, ui5, ui16,
/* N-bit signed displacement. */
disps9, disps17, disps25, disps32,
/* N-bit unsigned displacement. */
dispu5,
/* N-bit escaped displacement. */
dispe9,
/* N-bit absolute address. */
abs16, abs32,
/* Register relative. */
rbase, rbase_dispu4,
rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
/* Register index. */
rindex_disps6, rindex_disps22,
/* 4-bit genaral-purpose register specifier. */
regr,
/* 8-bit register address space. */
regr8,
/* coprocessor register. */
copregr,
/* coprocessor special register. */
copsregr,
/* Not an operand. */
nulloperand,
/* Maximum supported operand. */
MAX_OPRD
}
operand_type;
/* CRX instruction types. */
#define NO_TYPE_INS 0
#define ARITH_INS 1
#define LD_STOR_INS 2
#define BRANCH_INS 3
#define ARITH_BYTE_INS 4
#define CMPBR_INS 5
#define SHIFT_INS 6
#define BRANCH_NEQ_INS 7
#define LD_STOR_INS_INC 8
#define STOR_IMM_INS 9
#define CSTBIT_INS 10
#define COP_BRANCH_INS 11
#define COP_REG_INS 12
#define COPS_REG_INS 13
#define DCR_BRANCH_INS 14
/* Maximum value supported for instruction types. */
#define CRX_INS_MAX (1 << 4)
/* Mask to record an instruction type. */
#define CRX_INS_MASK (CRX_INS_MAX - 1)
/* Return instruction type, given instruction's attributes. */
#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
/* Indicates whether this instruction has a register list as parameter. */
#define REG_LIST CRX_INS_MAX
/* The operands in binary and assembly are placed in reverse order.
load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
#define REVERSE_MATCH (1 << 5)
/* Kind of displacement map used DISPU[BWD]4. */
#define DISPUB4 (1 << 6)
#define DISPUW4 (1 << 7)
#define DISPUD4 (1 << 8)
#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4)
/* Printing formats, where the instruction prefix isn't consecutive. */
#define FMT_1 (1 << 9) /* 0xF0F00000 */
#define FMT_2 (1 << 10) /* 0xFFF0FF00 */
#define FMT_3 (1 << 11) /* 0xFFF00F00 */
#define FMT_4 (1 << 12) /* 0xFFF0F000 */
#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */
#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
/* Indicates whether this instruction can be relaxed. */
#define RELAXABLE (1 << 14)
/* Indicates that instruction uses user registers (and not
general-purpose registers) as operands. */
#define USER_REG (1 << 15)
/* Indicates that instruction can perfom a cst4 mapping. */
#define CST4MAP (1 << 16)
/* Instruction shouldn't allow 'sp' usage. */
#define NO_SP (1 << 17)
/* Instruction shouldn't allow to push a register which is used as a rptr. */
#define NO_RPTR (1 << 18)
/* Maximum operands per instruction. */
#define MAX_OPERANDS 5
/* Maximum register name length. */
#define MAX_REGNAME_LEN 10
/* Maximum instruction length. */
#define MAX_INST_LEN 256
/* Values defined for the flags field of a struct operand_entry. */
/* Operand must be an unsigned number. */
#define OP_UNSIGNED (1 << 0)
/* Operand must be a signed number. */
#define OP_SIGNED (1 << 1)
/* A special arithmetic 4-bit constant operand. */
#define OP_CST4 (1 << 2)
/* A special load/stor 4-bit unsigned displacement operand. */
#define OP_DISPU4 (1 << 3)
/* Operand must be an even number. */
#define OP_EVEN (1 << 4)
/* Operand is shifted right. */
#define OP_SHIFT (1 << 5)
/* Operand is shifted right and decremented. */
#define OP_SHIFT_DEC (1 << 6)
/* Operand has reserved escape sequences. */
#define OP_ESC (1 << 7)
/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */
#define OP_UPPER_64KB (1 << 8)
/* Single operand description. */
typedef struct
{
/* Operand type. */
operand_type op_type;
/* Operand location within the opcode. */
unsigned int shift;
}
operand_desc;
/* Instruction data structure used in instruction table. */
typedef struct
{
/* Name. */
const char *mnemonic;
/* Size (in words). */
unsigned int size;
/* Constant prefix (matched by the disassembler). */
unsigned long match;
/* Match size (in bits). */
int match_bits;
/* Attributes. */
unsigned int flags;
/* Operands (always last, so unreferenced operands are initialized). */
operand_desc operands[MAX_OPERANDS];
}
inst;
/* Data structure for a single instruction's arguments (Operands). */
typedef struct
{
/* Register or base register. */
reg r;
/* Index register. */
reg i_r;
/* Coprocessor register. */
copreg cr;
/* Constant/immediate/absolute value. */
long constant;
/* Scaled index mode. */
unsigned int scale;
/* Argument type. */
argtype type;
/* Size of the argument (in bits) required to represent. */
int size;
/* The type of the expression. */
unsigned char X_op;
}
argument;
/* Internal structure to hold the various entities
corresponding to the current assembling instruction. */
typedef struct
{
/* Number of arguments. */
int nargs;
/* The argument data structure for storing args (operands). */
argument arg[MAX_OPERANDS];
/* The following fields are required only by CRX-assembler. */
#ifdef TC_CRX
/* Expression used for setting the fixups (if any). */
expressionS exp;
bfd_reloc_code_real_type rtype;
#endif /* TC_CRX */
/* Instruction size (in bytes). */
int size;
}
ins;
/* Structure to hold information about predefined operands. */
typedef struct
{
/* Size (in bits). */
unsigned int bit_size;
/* Argument type. */
argtype arg_type;
/* One bit syntax flags. */
int flags;
}
operand_entry;
/* Structure to hold trap handler information. */
typedef struct
{
/* Trap name. */
char *name;
/* Index in dispatch table. */
unsigned int entry;
}
trap_entry;
/* Structure to hold information about predefined registers. */
typedef struct
{
/* Name (string representation). */
char *name;
/* Value (enum representation). */
union
{
/* Register. */
reg reg_val;
/* Coprocessor register. */
copreg copreg_val;
} value;
/* Register image. */
int image;
/* Register type. */
reg_type type;
}
reg_entry;
/* Structure to hold a cst4 operand mapping. */
/* CRX opcode table. */
extern const inst crx_instruction[];
extern const int crx_num_opcodes;
#define NUMOPCODES crx_num_opcodes
/* CRX operands table. */
extern const operand_entry crx_optab[];
/* CRX registers table. */
extern const reg_entry crx_regtab[];
extern const int crx_num_regs;
#define NUMREGS crx_num_regs
/* CRX coprocessor registers table. */
extern const reg_entry crx_copregtab[];
extern const int crx_num_copregs;
#define NUMCOPREGS crx_num_copregs
/* CRX trap/interrupt table. */
extern const trap_entry crx_traps[];
extern const int crx_num_traps;
#define NUMTRAPS crx_num_traps
/* cst4 operand mapping. */
extern const int cst4_map[];
extern const int cst4_maps;
/* Table of instructions with no operands. */
extern const char* no_op_insn[];
/* Current instruction we're assembling. */
extern const inst *instruction;
/* A macro for representing the instruction "constant" opcode, that is,
the FIXED part of the instruction. The "constant" opcode is represented
as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
over that range. */
#define BIN(OPC,SHIFT) (OPC << SHIFT)
/* Is the current instruction type is TYPE ? */
#define IS_INSN_TYPE(TYPE) \
(CRX_INS_TYPE(instruction->flags) == TYPE)
/* Is the current instruction mnemonic is MNEMONIC ? */
#define IS_INSN_MNEMONIC(MNEMONIC) \
(strcmp(instruction->mnemonic,MNEMONIC) == 0)
/* Does the current instruction has register list ? */
#define INST_HAS_REG_LIST \
(instruction->flags & REG_LIST)
/* Long long type handling. */
/* Replace all appearances of 'long long int' with LONGLONG. */
typedef long long int LONGLONG;
typedef unsigned long long ULONGLONG;
#endif /* _CRX_H_ */

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/* d10v.h -- Header file for D10V opcode table
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2010
Free Software Foundation, Inc.
Written by Martin Hunt (hunt@cygnus.com), Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef D10V_H
#define D10V_H
/* Format Specifier */
#define FM00 0
#define FM01 0x40000000
#define FM10 0x80000000
#define FM11 0xC0000000
#define NOP 0x5e00
#define OPCODE_DIVS 0x14002800
/* The opcode table is an array of struct d10v_opcode. */
struct d10v_opcode
{
/* The opcode name. */
const char *name;
/* the opcode format */
int format;
/* These numbers were picked so we can do if( i & SHORT_OPCODE) */
#define SHORT_OPCODE 1
#define LONG_OPCODE 8
#define SHORT_2 1 /* short with 2 operands */
#define SHORT_B 3 /* short with 8-bit branch */
#define LONG_B 8 /* long with 16-bit branch */
#define LONG_L 10 /* long with 3 operands */
#define LONG_R 12 /* reserved */
/* just a placeholder for variable-length instructions */
/* for example, "bra" will be a fake for "bra.s" and bra.l" */
/* which will immediately follow in the opcode table. */
#define OPCODE_FAKE 32
/* the number of cycles */
int cycles;
/* the execution unit(s) used */
int unit;
#define EITHER 0
#define IU 1
#define MU 2
#define BOTH 3
/* execution type; parallel or sequential */
/* this field is used to decide if two instructions */
/* can be executed in parallel */
int exec_type;
#define PARONLY 1 /* parallel only */
#define SEQ 2 /* must be sequential */
#define PAR 4 /* may be parallel */
#define BRANCH_LINK 8 /* subroutine call. must be aligned */
#define RMEM 16 /* reads memory */
#define WMEM 32 /* writes memory */
#define RF0 64 /* reads f0 */
#define WF0 128 /* modifies f0 */
#define WCAR 256 /* write Carry */
#define BRANCH 512 /* branch, no link */
#define ALONE 1024 /* short but pack with a NOP if on asm line alone */
/* the opcode */
long opcode;
/* mask. if( (i & mask) == opcode ) then match */
long mask;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[6];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct d10v_opcode d10v_opcodes[];
extern const int d10v_num_opcodes;
/* The operands table is an array of struct d10v_operand. */
struct d10v_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* One bit syntax flags. */
int flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the d10v_opcodes table. */
extern const struct d10v_operand d10v_operands[];
/* Values defined for the flags field of a struct d10v_operand. */
/* the operand must be an even number */
#define OPERAND_EVEN (1)
/* the operand must be an odd number */
#define OPERAND_ODD (2)
/* this is the destination register; it will be modified */
/* this is used by the optimizer */
#define OPERAND_DEST (4)
/* number or symbol */
#define OPERAND_NUM (8)
/* address or label */
#define OPERAND_ADDR (0x10)
/* register */
#define OPERAND_REG (0x20)
/* postincrement + */
#define OPERAND_PLUS (0x40)
/* postdecrement - */
#define OPERAND_MINUS (0x80)
/* @ */
#define OPERAND_ATSIGN (0x100)
/* @( */
#define OPERAND_ATPAR (0x200)
/* accumulator 0 */
#define OPERAND_ACC0 (0x400)
/* accumulator 1 */
#define OPERAND_ACC1 (0x800)
/* f0 / f1 flag register */
#define OPERAND_FFLAG (0x1000)
/* c flag register */
#define OPERAND_CFLAG (0x2000)
/* control register */
#define OPERAND_CONTROL (0x4000)
/* predecrement mode '@-sp' */
#define OPERAND_ATMINUS (0x8000)
/* signed number */
#define OPERAND_SIGNED (0x10000)
/* special accumulator shifts need a 4-bit number */
/* 1 <= x <= 16 */
#define OPERAND_SHIFT (0x20000)
/* general purpose register */
#define OPERAND_GPR (0x40000)
/* special imm3 values with range restricted to -2 <= imm3 <= 3 */
/* needed for rac/rachi */
#define RESTRICTED_NUM3 (0x80000)
/* Pre-decrement is only supported for SP. */
#define OPERAND_SP (0x100000)
/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and
unlike OPERAND_SP, this flag doesn't prevent the instruction from
matching, it only fails validation later on. */
#define OPERAND_NOSP (0x200000)
/* Structure to hold information about predefined registers. */
struct pd_reg
{
char *name; /* name to recognize */
char *pname; /* name to print for this register */
int value;
};
extern const struct pd_reg d10v_predefined_registers[];
int d10v_reg_name_cnt (void);
/* an expressionS only has one register type, so we fake it */
/* by setting high bits to indicate type */
#define REGISTER_MASK 0xFF
#endif /* D10V_H */

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/* d30v.h -- Header file for D30V opcode table
Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010
Free Software Foundation, Inc.
Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef D30V_H
#define D30V_H
#define NOP 0x00F00000
/* Structure to hold information about predefined registers. */
struct pd_reg
{
char *name; /* name to recognize */
char *pname; /* name to print for this register */
int value;
};
extern const struct pd_reg pre_defined_registers[];
int reg_name_cnt (void);
/* the number of control registers */
#define MAX_CONTROL_REG 64
/* define the format specifiers */
#define FM00 0
#define FM01 0x80000000
#define FM10 0x8000000000000000LL
#define FM11 0x8000000080000000LL
/* define the opcode classes */
#define BRA 0
#define LOGIC 1
#define IMEM 2
#define IALU1 4
#define IALU2 5
/* define the execution condition codes */
#define ECC_AL 0 /* ALways (default) */
#define ECC_TX 1 /* F0=True, F1=Don't care */
#define ECC_FX 2 /* F0=False, F1=Don't care */
#define ECC_XT 3 /* F0=Don't care, F1=True */
#define ECC_XF 4 /* F0=Don't care, F1=False */
#define ECC_TT 5 /* F0=True, F1=True */
#define ECC_TF 6 /* F0=True, F1=False */
#define ECC_RESERVED 7 /* reserved */
#define ECC_MAX ECC_RESERVED
extern const char *d30v_ecc_names[];
/* condition code table for CMP and CMPU */
extern const char *d30v_cc_names[];
/* The opcode table is an array of struct d30v_opcode. */
struct d30v_opcode
{
/* The opcode name. */
const char *name;
/* the opcode */
int op1; /* first part, "IALU1" for example */
int op2; /* the rest of the opcode */
/* opcode format(s). These numbers correspond to entries */
/* in the d30v_format_table */
unsigned char format[4];
#define SHORT_M 1
#define SHORT_M2 5 /* for ld2w and st2w */
#define SHORT_A 9
#define SHORT_B1 11
#define SHORT_B2 12
#define SHORT_B2r 13
#define SHORT_B3 14
#define SHORT_B3r 16
#define SHORT_B3b 18
#define SHORT_B3br 20
#define SHORT_D1r 22
#define SHORT_D2 24
#define SHORT_D2r 26
#define SHORT_D2Br 28
#define SHORT_U 30 /* unary SHORT_A. ABS for example */
#define SHORT_F 31 /* SHORT_A with flag registers */
#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */
#define SHORT_T 35 /* for trap instruction */
#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */
#define SHORT_CMP 38 /* special form for CMPcc */
#define SHORT_CMPU 40 /* special form for CMPUcc */
#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */
#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */
#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */
#define SHORT_MODINC 48
#define SHORT_MODDEC 49
#define SHORT_C1 50
#define SHORT_C2 51
#define SHORT_UF 52
#define SHORT_A2 53
#define SHORT_NONE 55 /* no operands */
#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */
#define LONG 57
#define LONG_U 58 /* unary LONG */
#define LONG_Ur 59 /* LONG pc-relative */
#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */
#define LONG_M 61 /* Memory long for ldb, stb */
#define LONG_M2 62 /* Memory long for ld2w, st2w */
#define LONG_2 63 /* LONG with 2 operands; jmptnz */
#define LONG_2r 64 /* LONG with 2 operands; bratnz */
#define LONG_2b 65 /* LONG_2 with modifier of 3 */
#define LONG_2br 66 /* LONG_2r with modifier of 3 */
#define LONG_D 67 /* for DJMPI */
#define LONG_Dr 68 /* for DBRAI */
#define LONG_Dbr 69 /* for repeati */
/* the execution unit(s) used */
int unit;
#define EITHER 0
#define IU 1
#define MU 2
#define EITHER_BUT_PREFER_MU 3
/* this field is used to decide if two instructions */
/* can be executed in parallel */
long flags_used;
long flags_set;
#define FLAG_0 (1L<<0)
#define FLAG_1 (1L<<1)
#define FLAG_2 (1L<<2)
#define FLAG_3 (1L<<3)
#define FLAG_4 (1L<<4) /* S (saturation) */
#define FLAG_5 (1L<<5) /* V (overflow) */
#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */
#define FLAG_7 (1L<<7) /* C (carry/borrow) */
#define FLAG_SM (1L<<8) /* SM (stack mode) */
#define FLAG_RP (1L<<9) /* RP (repeat enable) */
#define FLAG_CONTROL (1L<<10) /* control registers */
#define FLAG_A0 (1L<<11) /* A0 */
#define FLAG_A1 (1L<<12) /* A1 */
#define FLAG_JMP (1L<<13) /* instruction is a branch */
#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */
#define FLAG_MEM (1L<<15) /* reads/writes memory */
#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation
New meaning: operation cannot be
combined in parallel with ADD/SUBppp. */
#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */
#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */
#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */
#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */
#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */
#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7)
#define FLAG_C FLAG_7
#define FLAG_ALL (FLAG_0 | \
FLAG_1 | \
FLAG_2 | \
FLAG_3 | \
FLAG_4 | \
FLAG_5 | \
FLAG_6 | \
FLAG_7 | \
FLAG_SM | \
FLAG_RP | \
FLAG_CONTROL)
int reloc_flag;
#define RELOC_PCREL 1
#define RELOC_ABS 2
};
extern const struct d30v_opcode d30v_opcode_table[];
extern const int d30v_num_opcodes;
/* The operands table is an array of struct d30v_operand. */
struct d30v_operand
{
/* the length of the field */
int length;
/* The number of significant bits in the operand. */
int bits;
/* position relative to Ra */
int position;
/* syntax flags. */
long flags;
};
extern const struct d30v_operand d30v_operand_table[];
/* Values defined for the flags field of a struct d30v_operand. */
/* this is the destination register; it will be modified */
/* this is used by the optimizer */
#define OPERAND_DEST (1)
/* number or symbol */
#define OPERAND_NUM (2)
/* address or label */
#define OPERAND_ADDR (4)
/* register */
#define OPERAND_REG (8)
/* postincrement + */
#define OPERAND_PLUS (0x10)
/* postdecrement - */
#define OPERAND_MINUS (0x20)
/* signed number */
#define OPERAND_SIGNED (0x40)
/* this operand must be shifted left by 3 */
#define OPERAND_SHIFT (0x80)
/* flag register */
#define OPERAND_FLAG (0x100)
/* control register */
#define OPERAND_CONTROL (0x200)
/* accumulator */
#define OPERAND_ACC (0x400)
/* @ */
#define OPERAND_ATSIGN (0x800)
/* @( */
#define OPERAND_ATPAR (0x1000)
/* predecrement mode '@-sp' */
#define OPERAND_ATMINUS (0x2000)
/* this operand changes the instruction name */
/* for example, CPMcc, CMPUcc */
#define OPERAND_NAME (0x4000)
/* fake operand for mvtsys and mvfsys */
#define OPERAND_SPECIAL (0x8000)
/* let the optimizer know that two registers are affected */
#define OPERAND_2REG (0x10000)
/* This operand is pc-relative. Note that repeati can have two immediate
operands, one of which is pcrel, the other (the IMM6U one) is not. */
#define OPERAND_PCREL (0x20000)
/* The format table is an array of struct d30v_format. */
struct d30v_format
{
int form; /* SHORT_A, LONG, etc */
int modifier; /* two bit modifier following opcode */
unsigned char operands[5];
};
extern const struct d30v_format d30v_format_table[];
/* an instruction is defined by an opcode and a format */
/* for example, "add" has one opcode, but three different */
/* formats, 2 SHORT_A forms and a LONG form. */
struct d30v_insn
{
struct d30v_opcode *op; /* pointer to an entry in the opcode table */
struct d30v_format *form; /* pointer to an entry in the format table */
int ecc; /* execution condition code */
};
/* an expressionS only has one register type, so we fake it */
/* by setting high bits to indicate type */
#define REGISTER_MASK 0xFF
#endif /* D30V_H */

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/* Table of opcodes for the DLX microprocess.
Copyright 2002, 2010 Free Software Foundation, Inc.
This file is part of GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA.
Initially created by Kuang Hwa Lin, 2002. */
/* Following are the function codes for the Special OP (ALU). */
#define ALUOP 0x00000000
#define SPECIALOP 0x00000000
#define NOPF 0x00000000
#define SLLF 0x00000004
#define SRLF 0x00000006
#define SRAF 0x00000007
#define SEQUF 0x00000010
#define SNEUF 0x00000011
#define SLTUF 0x00000012
#define SGTUF 0x00000013
#define SLEUF 0x00000014
#define SGEUF 0x00000015
#define ADDF 0x00000020
#define ADDUF 0x00000021
#define SUBF 0x00000022
#define SUBUF 0x00000023
#define ANDF 0x00000024
#define ORF 0x00000025
#define XORF 0x00000026
#define SEQF 0x00000028
#define SNEF 0x00000029
#define SLTF 0x0000002A
#define SGTF 0x0000002B
#define SLEF 0x0000002C
#define SGEF 0x0000002D
/* Following special functions was not mentioned in the
Hennessy's book but was implemented in the RTL. */
#define MVTSF 0x00000030
#define MVFSF 0x00000031
#define BSWAPF 0x00000032
#define LUTF 0x00000033
/* Following special functions was mentioned in the
Hennessy's book but was not implemented in the RTL. */
#define MULTF 0x00000005
#define MULTUF 0x00000006
#define DIVF 0x00000007
#define DIVUF 0x00000008
/* Following are the rest of the OPcodes:
JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26)
ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26)
ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26)
RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26)
BREAKOP= (0x014 << 26)
SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26)
SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26)
LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26)
LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26)
LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26),
SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26)
SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26)
SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */
#define JOP 0x08000000
#define JALOP 0x0c000000
#define BEQOP 0x10000000
#define BNEOP 0x14000000
#define ADDIOP 0x20000000
#define ADDUIOP 0x24000000
#define SUBIOP 0x28000000
#define SUBUIOP 0x2c000000
#define ANDIOP 0x30000000
#define ORIOP 0x34000000
#define XORIOP 0x38000000
#define LHIOP 0x3c000000
#define RFEOP 0x40000000
#define TRAPOP 0x44000000
#define JROP 0x48000000
#define JALROP 0x4c000000
#define BREAKOP 0x50000000
#define SEQIOP 0x60000000
#define SNEIOP 0x64000000
#define SLTIOP 0x68000000
#define SGTIOP 0x6c000000
#define SLEIOP 0x70000000
#define SGEIOP 0x74000000
#define LBOP 0x80000000
#define LHOP 0x84000000
#define LWOP 0x8c000000
#define LBUOP 0x90000000
#define LHUOP 0x94000000
#define LDSTBU
#define LDSTHU
#define SBOP 0xa0000000
#define SHOP 0xa4000000
#define SWOP 0xac000000
#define LDST
#define SEQUIOP 0xc0000000
#define SNEUIOP 0xc4000000
#define SLTUIOP 0xc8000000
#define SGTUIOP 0xcc000000
#define SLEUIOP 0xd0000000
#define SGEUIOP 0xd4000000
#define SLLIOP 0xd8000000
#define SRLIOP 0xdc000000
#define SRAIOP 0xe0000000
/* Following 3 ops was added to provide the MP atonmic operation. */
#define LSBUOP 0x98000000
#define LSHUOP 0x9c000000
#define LSWOP 0xb0000000
/* Following opcode was defined in the Hennessy's book as
"normal" opcode but was implemented in the RTL as special
functions. */
#if 0
#define MVTSOP 0x50000000
#define MVFSOP 0x54000000
#endif
struct dlx_opcode
{
/* Name of the instruction. */
char *name;
/* Opcode word. */
unsigned long opcode;
/* A string of characters which describe the operands.
Valid characters are:
, Itself. The character appears in the assembly code.
a rs1 The register number is in bits 21-25 of the instruction.
b rs2/rd The register number is in bits 16-20 of the instruction.
c rd. The register number is in bits 11-15 of the instruction.
f FUNC bits 0-10 of the instruction.
i An immediate operand is in bits 0-16 of the instruction. 0 extended
I An immediate operand is in bits 0-16 of the instruction. sign extended
d An 16 bit PC relative displacement.
D An immediate operand is in bits 0-25 of the instruction.
N No opperands needed, for nops.
P it can be a register or a 16 bit operand. */
char *args;
};
static const struct dlx_opcode dlx_opcodes[] =
{
/* Arithmetic and Logic R-TYPE instructions. */
{ "nop", (ALUOP|NOPF), "N" }, /* NOP */
{ "add", (ALUOP|ADDF), "c,a,b" }, /* Add */
{ "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */
{ "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */
{ "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */
{ "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */
{ "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */
{ "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */
{ "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */
{ "and", (ALUOP|ANDF), "c,a,b" }, /* AND */
{ "or", (ALUOP|ORF), "c,a,b" }, /* OR */
{ "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */
{ "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */
{ "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */
{ "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */
{ "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */
{ "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */
{ "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */
{ "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */
{ "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */
{ "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */
{ "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */
{ "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */
{ "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */
{ "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */
{ "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/
{ "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */
{ "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */
{ "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */
{ "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */
{ "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */
/* Arithmetic and Logical Immediate I-TYPE instructions. */
{ "addi", ADDIOP, "b,a,I" }, /* Add Immediate */
{ "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */
{ "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */
{ "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */
{ "andi", ANDIOP, "b,a,i" }, /* AND Immediate */
{ "ori", ORIOP, "b,a,i" }, /* OR Immediate */
{ "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */
{ "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */
{ "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */
{ "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/
{ "seqi", SEQIOP, "b,a,i" }, /* Set if equal */
{ "snei", SNEIOP, "b,a,i" }, /* Set if not equal */
{ "slti", SLTIOP, "b,a,i" }, /* Set if less */
{ "sgti", SGTIOP, "b,a,i" }, /* Set if greater */
{ "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */
{ "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */
{ "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */
{ "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */
{ "sltui", SLTUIOP, "b,a,i" }, /* Set if less */
{ "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */
{ "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */
{ "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */
/* Macros for I type instructions. */
{ "mov", ADDIOP, "b,P" }, /* a move macro */
{ "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */
#if 0
/* Move special. */
{ "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */
{ "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */
#endif
/* Load high Immediate I-TYPE instruction. */
{ "lhi", LHIOP, "b,i" }, /* Load High Immediate */
{ "lui", LHIOP, "b,i" }, /* Load High Immediate */
{ "sethi", LHIOP, "b,i" }, /* Load High Immediate */
/* LOAD/STORE BYTE 8 bits I-TYPE. */
{ "lb", LBOP, "b,a,I" }, /* Load Byte */
{ "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */
{ "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */
{ "sb", SBOP, "b,a,I" }, /* Store Byte */
/* LOAD/STORE HALFWORD 16 bits. */
{ "lh", LHOP, "b,a,I" }, /* Load Halfword */
{ "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */
{ "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */
{ "sh", SHOP, "b,a,I" }, /* Store Halfword */
/* LOAD/STORE WORD 32 bits. */
{ "lw", LWOP, "b,a,I" }, /* Load Word */
{ "sw", SWOP, "b,a,I" }, /* Store Word */
{ "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */
/* Branch PC-relative, 16 bits offset. */
{ "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */
{ "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */
{ "beq", BEQOP, "a,d" }, /* Branch if a == 0 */
{ "bne", BNEOP, "a,d" }, /* Branch if a != 0 */
/* Jumps Trap and RFE J-TYPE. */
{ "j", JOP, "D" }, /* Jump, PC-relative 26 bits */
{ "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */
{ "break", BREAKOP, "D" }, /* break to OS */
{ "trap" , TRAPOP, "D" }, /* TRAP to OS */
{ "rfe", RFEOP, "N" }, /* Return From Exception */
/* Macros. */
{ "call", JOP, "D" }, /* Jump, PC-relative 26 bits */
/* Jumps Trap and RFE I-TYPE. */
{ "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */
{ "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */
/* Macros. */
{ "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */
{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES.
This lets code examine entry i + 1 without
checking if we've run off the end of the table. */
};
const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1);

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/* i370.h -- Header file for S/390 opcode table
Copyright 1994, 1995, 1998, 1999, 2000, 2003, 2010
Free Software Foundation, Inc.
PowerPC version written by Ian Lance Taylor, Cygnus Support
Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef I370_H
#define I370_H
/* The opcode table is an array of struct i370_opcode. */
typedef union
{
unsigned int i[2];
unsigned short s[4];
unsigned char b[8];
} i370_insn_t;
struct i370_opcode
{
/* The opcode name. */
const char *name;
/* the length of the instruction */
char len;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
i370_insn_t opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
i370_insn_t mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
are listed below. */
unsigned long flags;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct i370_opcode i370_opcodes[];
extern const int i370_num_opcodes;
/* Values defined for the flags field of a struct i370_opcode. */
/* Opcode is defined for the original 360 architecture. */
#define I370_OPCODE_360 (0x01)
/* Opcode is defined for the 370 architecture. */
#define I370_OPCODE_370 (0x02)
/* Opcode is defined for the 370-XA architecture. */
#define I370_OPCODE_370_XA (0x04)
/* Opcode is defined for the ESA/370 architecture. */
#define I370_OPCODE_ESA370 (0x08)
/* Opcode is defined for the ESA/390 architecture. */
#define I370_OPCODE_ESA390 (0x10)
/* Opcode is defined for the ESA/390 w/ BFP facility. */
#define I370_OPCODE_ESA390_BF (0x20)
/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */
#define I370_OPCODE_ESA390_BS (0x40)
/* Opcode is defined for the ESA/390 w/ checksum facility. */
#define I370_OPCODE_ESA390_CK (0x80)
/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */
#define I370_OPCODE_ESA390_CM (0x100)
/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
#define I370_OPCODE_ESA390_FX (0x200)
/* Opcode is defined for the ESA/390 w/ HFP facility. */
#define I370_OPCODE_ESA390_HX (0x400)
/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */
#define I370_OPCODE_ESA390_IR (0x800)
/* Opcode is defined for the ESA/390 w/ move-inverse facility. */
#define I370_OPCODE_ESA390_MI (0x1000)
/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */
#define I370_OPCODE_ESA390_PC (0x2000)
/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */
#define I370_OPCODE_ESA390_PL (0x4000)
/* Opcode is defined for the ESA/390 w/ square-root facility. */
#define I370_OPCODE_ESA390_QR (0x8000)
/* Opcode is defined for the ESA/390 w/ resume-program facility. */
#define I370_OPCODE_ESA390_RP (0x10000)
/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */
#define I370_OPCODE_ESA390_SA (0x20000)
/* Opcode is defined for the ESA/390 w/ subspace group facility. */
#define I370_OPCODE_ESA390_SG (0x40000)
/* Opcode is defined for the ESA/390 w/ string facility. */
#define I370_OPCODE_ESA390_SR (0x80000)
/* Opcode is defined for the ESA/390 w/ trap facility. */
#define I370_OPCODE_ESA390_TR (0x100000)
#define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
/* The operands table is an array of struct i370_operand. */
struct i370_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
i370_insn_t (*insert)
(i370_insn_t instruction, long op, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & I370_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (i370_insn_t instruction, int *invalid);
/* One bit syntax flags. */
unsigned long flags;
/* name -- handy for debugging, otherwise pointless */
char * name;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the i370_opcodes table. */
extern const struct i370_operand i370_operands[];
/* Values defined for the flags field of a struct i370_operand. */
/* This operand should be wrapped in parentheses rather than
separated from the previous by a comma. This is used for S, RS and
SS form instructions which want their operands to look like
reg,displacement(basereg) */
#define I370_OPERAND_SBASE (0x01)
/* This operand is a base register. It may or may not appear next
to an index register, i.e. either of the two forms
reg,displacement(basereg)
reg,displacement(index,basereg) */
#define I370_OPERAND_BASE (0x02)
/* This pair of operands should be wrapped in parentheses rather than
separated from the last by a comma. This is used for the RX form
instructions which want their operands to look like
reg,displacement(index,basereg) */
#define I370_OPERAND_INDEX (0x04)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define I370_OPERAND_GPR (0x08)
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define I370_OPERAND_FPR (0x10)
/* This operand is a displacement. */
#define I370_OPERAND_RELATIVE (0x20)
/* This operand is a length, such as that in SS form instructions. */
#define I370_OPERAND_LENGTH (0x40)
/* This operand is optional, and is zero if omitted. This is used for
the optional B2 field in the shift-left, shift-right instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
#define I370_OPERAND_OPTIONAL (0x80)
/* Define some misc macros. We keep them with the operands table
for simplicity. The macro table is an array of struct i370_macro. */
struct i370_macro
{
/* The macro name. */
const char *name;
/* The number of operands the macro takes. */
unsigned int operands;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The values are the
same as those for the struct i370_opcode flags field. */
unsigned long flags;
/* A format string to turn the macro into a normal instruction.
Each %N in the string is replaced with operand number N (zero
based). */
const char *format;
};
extern const struct i370_macro i370_macros[];
extern const int i370_num_macros;
#endif /* I370_H */

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/* opcode/i386.h -- Intel 80386 opcode macros
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
ix86 Unix assemblers, generate floating point instructions with
reversed source and destination registers in certain cases.
Unfortunately, gcc and possibly many other programs use this
reversed syntax, so we're stuck with it.
eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
`fsub %st,%st(3)' results in st(3) = st - st(3), rather than
the expected st(3) = st(3) - st
This happens with all the non-commutative arithmetic floating point
operations with two register operands, where the source register is
%st, and destination register is %st(i).
The affected opcode map is dceX, dcfX, deeX, defX. */
#ifndef OPCODE_I386_H
#define OPCODE_I386_H
#ifndef SYSV386_COMPAT
/* Set non-zero for broken, compatible instructions. Set to zero for
non-broken opcodes at your peril. gcc generates SystemV/386
compatible instructions. */
#define SYSV386_COMPAT 1
#endif
#ifndef OLDGCC_COMPAT
/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
reversed. */
#define OLDGCC_COMPAT SYSV386_COMPAT
#endif
#define MOV_AX_DISP32 0xa0
#define POP_SEG_SHORT 0x07
#define JUMP_PC_RELATIVE 0xeb
#define INT_OPCODE 0xcd
#define INT3_OPCODE 0xcc
/* The opcode for the fwait instruction, which disassembler treats as a
prefix when it can. */
#define FWAIT_OPCODE 0x9b
/* Instruction prefixes.
NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as
part of the opcode. Other prefixes may still appear between them
and the 0x0f part of the opcode. */
#define ADDR_PREFIX_OPCODE 0x67
#define DATA_PREFIX_OPCODE 0x66
#define LOCK_PREFIX_OPCODE 0xf0
#define CS_PREFIX_OPCODE 0x2e
#define DS_PREFIX_OPCODE 0x3e
#define ES_PREFIX_OPCODE 0x26
#define FS_PREFIX_OPCODE 0x64
#define GS_PREFIX_OPCODE 0x65
#define SS_PREFIX_OPCODE 0x36
#define REPNE_PREFIX_OPCODE 0xf2
#define REPE_PREFIX_OPCODE 0xf3
#define XACQUIRE_PREFIX_OPCODE 0xf2
#define XRELEASE_PREFIX_OPCODE 0xf3
#define BND_PREFIX_OPCODE 0xf2
#define TWO_BYTE_OPCODE_ESCAPE 0x0f
#define NOP_OPCODE (char) 0x90
/* register numbers */
#define EAX_REG_NUM 0
#define ECX_REG_NUM 1
#define EDX_REG_NUM 2
#define EBX_REG_NUM 3
#define ESP_REG_NUM 4
#define EBP_REG_NUM 5
#define ESI_REG_NUM 6
#define EDI_REG_NUM 7
/* modrm_byte.regmem for twobyte escape */
#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
/* index_base_byte.index for no index register addressing */
#define NO_INDEX_REGISTER ESP_REG_NUM
/* index_base_byte.base for no base register addressing */
#define NO_BASE_REGISTER EBP_REG_NUM
#define NO_BASE_REGISTER_16 6
/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
/* Extract fields from the mod/rm byte. */
#define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3)
#define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7)
#define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7)
/* Extract fields from the sib byte. */
#define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3)
#define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7)
#define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7)
/* x86-64 extension prefix. */
#define REX_OPCODE 0x40
/* Non-zero if OPCODE is the rex prefix. */
#define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE)
/* Indicates 64 bit operand size. */
#define REX_W 8
/* High extension to reg field of modrm byte. */
#define REX_R 4
/* High extension to SIB index field. */
#define REX_X 2
/* High extension to base field of modrm or SIB, or reg field of opcode. */
#define REX_B 1
/* max operands per insn */
#define MAX_OPERANDS 5
/* max immediates per insn (lcall, ljmp, insertq, extrq) */
#define MAX_IMMEDIATE_OPERANDS 2
/* max memory refs per insn (string ops) */
#define MAX_MEMORY_OPERANDS 2
/* max size of insn mnemonics. */
#define MAX_MNEM_SIZE 20
/* max size of register name in insn mnemonics. */
#define MAX_REG_NAME_SIZE 8
#endif /* OPCODE_I386_H */

507
contrib/toolchain/binutils/include/opcode/i860.h Normal file
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@@ -0,0 +1,507 @@
/* Table of opcodes for the i860.
Copyright 1989, 1991, 2000, 2002, 2003, 2010
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/* Structure of an opcode table entry. */
struct i860_opcode
{
/* The opcode name. */
const char *name;
/* Bits that must be set. */
unsigned long match;
/* Bits that must not be set. */
unsigned long lose;
const char *args;
/* Nonzero if this is a possible expand-instruction. */
char expand;
};
enum expand_type
{
E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY
};
/* All i860 opcodes are 32 bits, except for the pseudo-instructions
and the operations utilizing a 32-bit address expression, an
unsigned 32-bit constant, or a signed 32-bit constant.
These opcodes are expanded into a two-instruction sequence for
any situation where the immediate operand does not fit in 32 bits.
In the case of the add and subtract operations the expansion is
to a three-instruction sequence (ex: orh, or, adds). In cases
where the address is to be relocated, the instruction is
expanded to handle the worse case, this could be optimized at
the final link if the actual address were known.
The pseudoinstructions are: mov, fmov, pmov, nop, and fnop.
These instructions are implemented as a one or two instruction
sequence of other operations.
The match component is a mask saying which bits must match a
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing one character
for each operand of the instruction.
Kinds of operands:
# Number used by optimizer. It is ignored.
1 src1 integer register.
2 src2 integer register.
d dest register.
c ctrlreg control register.
i 16 bit immediate.
I 16 bit immediate, aligned 2^0. (ld.b)
J 16 bit immediate, aligned 2^1. (ld.s)
K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l)
L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d)
M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q)
5 5 bit immediate.
l lbroff 26 bit PC relative immediate.
r sbroff 16 bit PC relative immediate.
s split 16 bit immediate.
S split 16 bit immediate, aligned 2^0. (st.b)
T split 16 bit immediate, aligned 2^1. (st.s)
U split 16 bit immediate, aligned 2^2. (st.l)
e src1 floating point register.
f src2 floating point register.
g dest floating point register. */
/* The order of the opcodes in this table is significant. The assembler
requires that all instances of the same mnemonic must be consecutive.
If they aren't, the assembler will not function properly.
The order of opcodes does not affect the disassembler. */
static const struct i860_opcode i860_opcodes[] =
{
/* REG-Format Instructions. */
{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */
{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */
{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */
{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */
{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */
{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */
{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */
{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */
{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */
{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */
{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */
{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */
{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */
{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */
{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */
{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */
{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */
{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */
{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */
{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */
{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */
{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */
{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */
{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */
{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */
{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */
{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */
{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */
{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */
{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */
{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */
{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */
{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */
{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */
{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */
{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */
{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */
{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */
{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */
{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */
{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */
{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */
{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */
{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */
{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */
{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */
{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */
{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */
{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */
{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */
{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */
{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */
{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */
{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */
{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */
{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */
{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */
{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */
{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */
{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */
{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */
{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */
{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */
{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */
{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */
{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */
{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */
{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */
{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */
{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */
{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */
{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */
{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */
{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */
{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */
{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */
{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */
{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */
{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */
{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */
{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */
{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */
{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */
{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */
{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */
{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */
{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */
{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */
/* Core Escape Instruction Format */
{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */
{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */
{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */
{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */
{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */
{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */
{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */
{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */
{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */
{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */
{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */
{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */
{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */
{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */
/* CTRL-Format Instructions */
{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */
{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */
{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */
{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */
{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */
{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */
/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */
{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 },
{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 },
{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 },
{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 },
{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 },
{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 },
{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 },
{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 },
{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 },
{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 },
{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 },
{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 },
{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 },
{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 },
{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 },
{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 },
{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 },
{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 },
{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 },
{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 },
{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 },
{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 },
{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 },
{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 },
{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 },
{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 },
{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 },
{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 },
{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 },
{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 },
{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 },
{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 },
{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 },
{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 },
{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 },
{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 },
{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 },
{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 },
{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 },
{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 },
{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 },
{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 },
{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 },
{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 },
{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 },
{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 },
{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 },
{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */
{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 },
{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 },
{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 },
{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 },
{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 },
{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 },
{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 },
{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 },
{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 },
{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 },
{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 },
{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 },
{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 },
{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 },
{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 },
{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 },
{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 },
{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 },
{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 },
{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 },
{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 },
{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 },
{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 },
{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 },
{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 },
{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 },
{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 },
{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 },
{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 },
{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 },
{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 },
{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 },
{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 },
{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 },
{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 },
{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 },
{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 },
{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 },
{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 },
{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 },
{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 },
{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 },
{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 },
{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 },
{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 },
{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 },
{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 },
{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */
{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 },
{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 },
{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 },
{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 },
{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 },
{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 },
{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 },
{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 },
{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 },
{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 },
{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 },
{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 },
{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 },
{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 },
{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 },
{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 },
{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 },
{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 },
{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 },
{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 },
{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 },
{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 },
{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 },
{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 },
{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 },
{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 },
{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 },
{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 },
{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 },
{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 },
{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 },
{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 },
{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 },
{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 },
{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 },
{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 },
{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 },
{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 },
{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 },
{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 },
{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 },
{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 },
{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 },
{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 },
{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */
{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 },
{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 },
{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 },
{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 },
{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 },
{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 },
{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 },
{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 },
{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 },
{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 },
{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 },
{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 },
{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 },
{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 },
{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 },
{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 },
{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 },
{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 },
{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 },
{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 },
{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 },
{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 },
{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 },
{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 },
{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 },
{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 },
{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 },
{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 },
{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 },
{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 },
{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 },
{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 },
{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 },
{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 },
{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 },
{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 },
{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 },
{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 },
{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 },
{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 },
{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 },
{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 },
{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 },
{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 },
{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 },
{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */
{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */
{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */
{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */
{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */
{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */
{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */
{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */
{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */
{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */
{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */
{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */
{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
/* Opcode pfgt has R bit cleared; pfle has R bit set. */
{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
/* Opcode pfgt has R bit cleared; pfle has R bit set. */
{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */
{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */
{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */
{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */
{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */
{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */
{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */
{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */
{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */
{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */
{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */
{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */
{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */
{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */
{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */
{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */
{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */
{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */
/* Floating point pseudo-instructions. */
{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */
{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */
{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */
{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */
{ 0, 0, 0, 0, 0 },
};
#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0]))

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contrib/toolchain/binutils/include/opcode/i960.h Normal file
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/* Basic 80960 instruction formats.
Copyright 2001-2013 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/* The 'COJ' instructions are actually COBR instructions with the 'b' in
the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if
necessary: if the displacement will not fit in 13 bits, the assembler will
replace them with the corresponding compare and branch instructions.
All of the 'MEMn' instructions are the same format; the 'n' in the name
indicates the default index scale factor (the size of the datum operated on).
The FBRA formats are not actually an instruction format. They are the
"convenience directives" for branching on floating-point comparisons,
each of which generates 2 instructions (a 'bno' and one other branch).
The CALLJ format is not actually an instruction format. It indicates that
the instruction generated (a CTRL-format 'call') should have its relocation
specially flagged for link-time replacement with a 'bal' or 'calls' if
appropriate. */
#define CTRL 0
#define COBR 1
#define COJ 2
#define REG 3
#define MEM1 4
#define MEM2 5
#define MEM4 6
#define MEM8 7
#define MEM12 8
#define MEM16 9
#define FBRA 10
#define CALLJ 11
/* Masks for the mode bits in REG format instructions */
#define M1 0x0800
#define M2 0x1000
#define M3 0x2000
/* Generate the 12-bit opcode for a REG format instruction by placing the
* high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
* 7-10.
*/
#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
/* Generate a template for a REG format instruction: place the opcode bits
* in the appropriate fields and OR in mode bits for the operands that will not
* be used. I.e.,
* set m1=1, if src1 will not be used
* set m2=1, if src2 will not be used
* set m3=1, if dst will not be used
*
* Setting the "unused" mode bits to 1 speeds up instruction execution(!).
* The information is also useful to us because some 1-operand REG instructions
* use the src1 field, others the dst field; and some 2-operand REG instructions
* use src1/src2, others src1/dst. The set mode bits enable us to distinguish.
*/
#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */
#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */
#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */
#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */
#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */
#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */
/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
*
* Interpret names as follows:
* R: global or local register only
* RS: global, local, or (if target allows) special-function register only
* RL: global or local register, or integer literal
* RSL: global, local, or (if target allows) special-function register;
* or integer literal
* F: global, local, or floating-point register
* FL: global, local, or floating-point register; or literal (including
* floating point)
*
* A number appended to a name indicates that registers must be aligned,
* as follows:
* 2: register number must be multiple of 2
* 4: register number must be multiple of 4
*/
#define SFR 0x10 /* Mask for the "sfr-OK" bit */
#define LIT 0x08 /* Mask for the "literal-OK" bit */
#define FP 0x04 /* Mask for "floating-point-OK" bit */
/* This macro ors the bits together. Note that 'align' is a mask
* for the low 0, 1, or 2 bits of the register number, as appropriate.
*/
#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr )
#define R OP( 0, 0, 0, 0 )
#define RS OP( 0, 0, 0, SFR )
#define RL OP( 0, LIT, 0, 0 )
#define RSL OP( 0, LIT, 0, SFR )
#define F OP( 0, 0, FP, 0 )
#define FL OP( 0, LIT, FP, 0 )
#define R2 OP( 1, 0, 0, 0 )
#define RL2 OP( 1, LIT, 0, 0 )
#define F2 OP( 1, 0, FP, 0 )
#define FL2 OP( 1, LIT, FP, 0 )
#define R4 OP( 3, 0, 0, 0 )
#define RL4 OP( 3, LIT, 0, 0 )
#define F4 OP( 3, 0, FP, 0 )
#define FL4 OP( 3, LIT, FP, 0 )
#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */
/* Macros to extract info from the register operand descriptor byte 'od'.
*/
#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */
#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */
#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */
#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0)
/* TRUE if reg #n is properly aligned */
#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/
/* Description of a single i80960 instruction */
struct i960_opcode {
long opcode; /* 32 bits, constant fields filled in, rest zeroed */
char *name; /* Assembler mnemonic */
short iclass; /* Class: see #defines below */
char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */
char num_ops; /* Number of operands */
char operand[3];/* Operand descriptors; same order as assembler instr */
};
/* Classes of 960 instructions:
* - each instruction falls into one class.
* - each target architecture supports one or more classes.
*
* EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass().
*/
#define I_BASE 0x01 /* 80960 base instruction set */
#define I_CX 0x02 /* 80960Cx instruction */
#define I_DEC 0x04 /* Decimal instruction */
#define I_FP 0x08 /* Floating point instruction */
#define I_KX 0x10 /* 80960Kx instruction */
#define I_MIL 0x20 /* Military instruction */
#define I_CASIM 0x40 /* CA simulator instruction */
#define I_CX2 0x80 /* Cx/Jx/Hx instructions */
#define I_JX 0x100 /* Jx/Hx instruction */
#define I_HX 0x200 /* Hx instructions */
/******************************************************************************
*
* TABLE OF i960 INSTRUCTION DESCRIPTIONS
*
******************************************************************************/
const struct i960_opcode i960_opcodes[] = {
/* if a CTRL instruction has an operand, it's always a displacement */
/* callj default=='call' */
{ 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } },
{ 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* bf same as bno */
{ 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* bru same as bno */
{ 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* brg same as bg */
{ 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* bre same as be */
{ 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* brge same as bge */
{ 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* brl same as bl */
{ 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* brlg same as bne */
{ 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* brle same as ble */
{ 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* bt same as bo */
{ 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } },
/* bro same as bo */
{ 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } },
{ 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } },
/* faultf same as faultno */
{ 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } },
/* faultt syn for faulto */
{ 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } },
{ 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } },
/* If a COBR (or COJ) has 3 operands, the last one is always a
* displacement and does not appear explicitly in the table.
*/
{ 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } },
{ 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } },
{ 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } },
{ 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } },
{ 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } },
{ 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } },
{ 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } },
{ 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } },
{ 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } },
{ 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } },
{ 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } },
{ 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } },
{ 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } },
{ 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } },
{ 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } },
{ 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } },
{ 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } },
{ 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } },
{ 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } },
{ 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } },
{ 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } },
{ 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } },
{ 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } },
{ R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } },
{ R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } },
{ R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } },
{ R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } },
{ R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } },
{ R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } },
{ R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } },
{ R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } },
{ R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } },
{ R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } },
{ R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } },
{ R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } },
{ R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } },
{ R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } },
{ R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } },
{ R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } },
{ R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } },
{ R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } },
{ R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } },
{ R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } },
{ R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } },
{ R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } },
{ R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } },
{ R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } },
/* Floating-point instructions */
{ R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } },
{ R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } },
{ R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } },
{ R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } },
{ R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } },
{ R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } },
{ R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } },
{ R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } },
{ R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } },
{ R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } },
{ R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } },
{ R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } },
{ R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } },
{ R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } },
{ R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } },
{ R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } },
{ R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } },
{ R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } },
{ R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } },
{ R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } },
{ R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } },
{ R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } },
{ R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } },
{ R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } },
/* These are the floating point branch instructions. Each actually
* generates 2 branch instructions: the first a CTRL instruction with
* the indicated opcode, and the second a 'bno'.
*/
{ 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } },
{ 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } },
{ 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } },
{ 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } },
{ 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } },
{ 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } },
/* Decimal instructions */
{ R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } },
{ R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } },
{ R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } },
/* KX extensions */
{ R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } },
{ R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } },
{ R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } },
{ R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } },
/* MC extensions */
{ R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } },
{ R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } },
{ R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } },
{ R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } },
{ R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } },
{ R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } },
{ R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } },
{ R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } },
{ R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } },
{ R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } },
{ R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } },
{ R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } },
{ R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } },
{ R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } },
{ R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } },
{ R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } },
{ R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } },
/* CX extensions */
{ R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } },
{ R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } },
{ R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } },
{ R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } },
/* Jx extensions. */
{ R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } },
{ R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } },
{ R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } },
{ R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } },
{ R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } },
{ R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } },
{ R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } },
{ R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } },
{ R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } },
/* Hx extensions. */
{ 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } },
/* END OF TABLE */
{ 0, NULL, 0, 0, 0, { 0, 0, 0 } }
};
/* end of i960-opcode.h */

422
contrib/toolchain/binutils/include/opcode/ia64.h Normal file
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/* ia64.h -- Header file for ia64 opcode table
Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006, 2010
Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
#ifndef opcode_ia64_h
#define opcode_ia64_h
#include <sys/types.h>
#include "bfd.h"
typedef BFD_HOST_U_64_BIT ia64_insn;
enum ia64_insn_type
{
IA64_TYPE_NIL = 0, /* illegal type */
IA64_TYPE_A, /* integer alu (I- or M-unit) */
IA64_TYPE_I, /* non-alu integer (I-unit) */
IA64_TYPE_M, /* memory (M-unit) */
IA64_TYPE_B, /* branch (B-unit) */
IA64_TYPE_F, /* floating-point (F-unit) */
IA64_TYPE_X, /* long encoding (X-unit) */
IA64_TYPE_DYN, /* Dynamic opcode */
IA64_NUM_TYPES
};
enum ia64_unit
{
IA64_UNIT_NIL = 0, /* illegal unit */
IA64_UNIT_I, /* integer unit */
IA64_UNIT_M, /* memory unit */
IA64_UNIT_B, /* branching unit */
IA64_UNIT_F, /* floating-point unit */
IA64_UNIT_L, /* long "unit" */
IA64_UNIT_X, /* may be integer or branch unit */
IA64_NUM_UNITS
};
/* Changes to this enumeration must be propagated to the operand table in
bfd/cpu-ia64-opc.c
*/
enum ia64_opnd
{
IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
/* constants */
IA64_OPND_AR_CSD, /* application register csd (ar.csd) */
IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
IA64_OPND_C1, /* the constant 1 */
IA64_OPND_C8, /* the constant 8 */
IA64_OPND_C16, /* the constant 16 */
IA64_OPND_GR0, /* gr0 */
IA64_OPND_IP, /* instruction pointer (ip) */
IA64_OPND_PR, /* predicate register (pr) */
IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
IA64_OPND_PSR, /* processor status register (psr) */
IA64_OPND_PSR_L, /* processor status register L (psr.l) */
IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
/* register operands: */
IA64_OPND_AR3, /* third application register # (bits 20-26) */
IA64_OPND_B1, /* branch register # (bits 6-8) */
IA64_OPND_B2, /* branch register # (bits 13-15) */
IA64_OPND_CR3, /* third control register # (bits 20-26) */
IA64_OPND_F1, /* first floating-point register # */
IA64_OPND_F2, /* second floating-point register # */
IA64_OPND_F3, /* third floating-point register # */
IA64_OPND_F4, /* fourth floating-point register # */
IA64_OPND_P1, /* first predicate # */
IA64_OPND_P2, /* second predicate # */
IA64_OPND_R1, /* first register # */
IA64_OPND_R2, /* second register # */
IA64_OPND_R3, /* third register # */
IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */
/* memory operands: */
IA64_OPND_MR3, /* memory at addr of third register # */
/* indirect operands: */
IA64_OPND_CPUID_R3, /* cpuid[reg] */
IA64_OPND_DBR_R3, /* dbr[reg] */
IA64_OPND_DTR_R3, /* dtr[reg] */
IA64_OPND_ITR_R3, /* itr[reg] */
IA64_OPND_IBR_R3, /* ibr[reg] */
IA64_OPND_MSR_R3, /* msr[reg] */
IA64_OPND_PKR_R3, /* pkr[reg] */
IA64_OPND_PMC_R3, /* pmc[reg] */
IA64_OPND_PMD_R3, /* pmd[reg] */
IA64_OPND_DAHR_R3, /* dahr[reg] */
IA64_OPND_RR_R3, /* rr[reg] */
/* immediate operands: */
IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */
IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
IA64_OPND_SOF, /* 8-bit stack frame size */
IA64_OPND_SOL, /* 8-bit size of locals */
IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */
IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */
IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */
IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */
IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */
IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
};
enum ia64_dependency_mode
{
IA64_DV_RAW,
IA64_DV_WAW,
IA64_DV_WAR,
};
enum ia64_dependency_semantics
{
IA64_DVS_NONE,
IA64_DVS_IMPLIED,
IA64_DVS_IMPLIEDF,
IA64_DVS_DATA,
IA64_DVS_INSTR,
IA64_DVS_SPECIFIC,
IA64_DVS_STOP,
IA64_DVS_OTHER,
};
enum ia64_resource_specifier
{
IA64_RS_ANY,
IA64_RS_AR_K,
IA64_RS_AR_UNAT,
IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
IA64_RS_ARb, /* 48-63, 112-127 */
IA64_RS_BR,
IA64_RS_CFM,
IA64_RS_CPUID,
IA64_RS_CR_IIB,
IA64_RS_CR_IRR,
IA64_RS_CR_LRR,
IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
IA64_RS_DAHR,
IA64_RS_DBR,
IA64_RS_FR,
IA64_RS_FRb,
IA64_RS_GR0,
IA64_RS_GR,
IA64_RS_IBR,
IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
IA64_RS_MSR,
IA64_RS_PKR,
IA64_RS_PMC,
IA64_RS_PMD,
IA64_RS_PR, /* non-rotating, 1-15 */
IA64_RS_PRr, /* rotating, 16-62 */
IA64_RS_PR63,
IA64_RS_RR,
IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
IA64_RS_CRX, /* CRs not in RS_CR */
IA64_RS_PSR, /* PSR bits */
IA64_RS_RSE, /* implementation-specific RSE resources */
IA64_RS_AR_FPSR,
};
enum ia64_rse_resource
{
IA64_RSE_N_STACKED_PHYS,
IA64_RSE_BOF,
IA64_RSE_STORE_REG,
IA64_RSE_LOAD_REG,
IA64_RSE_BSPLOAD,
IA64_RSE_RNATBITINDEX,
IA64_RSE_CFLE,
IA64_RSE_NDIRTY,
};
/* Information about a given resource dependency */
struct ia64_dependency
{
/* Name of the resource */
const char *name;
/* Does this dependency need further specification? */
enum ia64_resource_specifier specifier;
/* Mode of dependency */
enum ia64_dependency_mode mode;
/* Dependency semantics */
enum ia64_dependency_semantics semantics;
/* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
#define REG_NONE (-1)
int regindex;
/* Special info on semantics */
const char *info;
};
/* Two arrays of indexes into the ia64_dependency table.
chks are dependencies to check for conflicts when an opcode is
encountered; regs are dependencies to register (mark as used) when an
opcode is used. chks correspond to readers (RAW) or writers (WAW or
WAR) of a resource, while regs correspond to writers (RAW or WAW) and
readers (WAR) of a resource. */
struct ia64_opcode_dependency
{
int nchks;
const unsigned short *chks;
int nregs;
const unsigned short *regs;
};
/* encode/extract the note/index for a dependency */
#define RDEP(N,X) (((N)<<11)|(X))
#define NOTE(X) (((X)>>11)&0x1F)
#define DEP(X) ((X)&0x7FF)
/* A template descriptor describes the execution units that are active
for each of the three slots. It also specifies the location of
instruction group boundaries that may be present between two slots. */
struct ia64_templ_desc
{
int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
enum ia64_unit exec_unit[3];
const char *name;
};
/* The opcode table is an array of struct ia64_opcode. */
struct ia64_opcode
{
/* The opcode name. */
const char *name;
/* The type of the instruction: */
enum ia64_insn_type type;
/* Number of output operands: */
int num_outputs;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
ia64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
ia64_insn mask;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum ia64_opnd operands[5];
/* One bit flags for the opcode. These are primarily used to
indicate specific processors and environments support the
instructions. The defined values are listed below. */
unsigned int flags;
/* Used by ia64_find_next_opcode (). */
short ent_index;
/* Opcode dependencies. */
const struct ia64_opcode_dependency *dependencies;
};
/* Values defined for the flags field of a struct ia64_opcode. */
#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
/* A macro to extract the major opcode from an instruction. */
#define IA64_OP(i) (((i) >> 37) & 0xf)
enum ia64_operand_class
{
IA64_OPND_CLASS_CST, /* constant */
IA64_OPND_CLASS_REG, /* register */
IA64_OPND_CLASS_IND, /* indirect register */
IA64_OPND_CLASS_ABS, /* absolute value */
IA64_OPND_CLASS_REL, /* IP-relative value */
};
/* The operands table is an array of struct ia64_operand. */
struct ia64_operand
{
enum ia64_operand_class op_class;
/* Set VALUE as the operand bits for the operand of type SELF in the
instruction pointed to by CODE. If an error occurs, *CODE is not
modified and the returned string describes the cause of the
error. If no error occurs, NULL is returned. */
const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code);
/* Extract the operand bits for an operand of type SELF from
instruction CODE store them in *VALUE. If an error occurs, the
cause of the error is described by the string returned. If no
error occurs, NULL is returned. */
const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
ia64_insn *value);
/* A string whose meaning depends on the operand class. */
const char *str;
struct bit_field
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
}
field[4]; /* no operand has more than this many bit-fields */
unsigned int flags;
const char *desc; /* brief description */
};
/* Values defined for the flags field of a struct ia64_operand. */
/* Disassemble as signed decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
/* Disassemble as unsigned decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
extern const struct ia64_templ_desc ia64_templ_desc[16];
/* The tables are sorted by major opcode number and are otherwise in
the order in which the disassembler should consider instructions. */
extern struct ia64_opcode ia64_opcodes_a[];
extern struct ia64_opcode ia64_opcodes_i[];
extern struct ia64_opcode ia64_opcodes_m[];
extern struct ia64_opcode ia64_opcodes_b[];
extern struct ia64_opcode ia64_opcodes_f[];
extern struct ia64_opcode ia64_opcodes_d[];
extern struct ia64_opcode *ia64_find_opcode (const char *);
extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *);
extern struct ia64_opcode *ia64_dis_opcode (ia64_insn,
enum ia64_insn_type);
extern void ia64_free_opcode (struct ia64_opcode *);
extern const struct ia64_dependency *ia64_find_dependency (int);
/* To avoid circular library dependencies, this array is implemented
in bfd/cpu-ia64-opc.c: */
extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
#endif /* opcode_ia64_h */

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contrib/toolchain/binutils/include/opcode/m68hc11.h Normal file
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/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table
Copyright 1999, 2000, 2002, 2003, 2010, 2012
Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef _OPCODE_M68HC11_H
#define _OPCODE_M68HC11_H
/* Flags for the definition of the 68HC11 & 68HC12 CCR. */
#define M6811_S_BIT 0x80 /* Stop disable */
#define M6811_X_BIT 0x40 /* X-interrupt mask */
#define M6811_H_BIT 0x20 /* Half carry flag */
#define M6811_I_BIT 0x10 /* I-interrupt mask */
#define M6811_N_BIT 0x08 /* Negative */
#define M6811_Z_BIT 0x04 /* Zero */
#define M6811_V_BIT 0x02 /* Overflow */
#define M6811_C_BIT 0x01 /* Carry */
/* 68HC11 register address offsets (range 0..0x3F or 0..64).
The absolute address of the I/O register depends on the setting
of the M6811_INIT register. At init time, the I/O registers are
mapped at 0x1000. Address of registers is then:
0x1000 + M6811_xxx. */
#define M6811_PORTA 0x00 /* Port A register */
#define M6811__RES1 0x01 /* Unused/Reserved */
#define M6811_PIOC 0x02 /* Parallel I/O Control register */
#define M6811_PORTC 0x03 /* Port C register */
#define M6811_PORTB 0x04 /* Port B register */
#define M6811_PORTCL 0x05 /* Alternate latched port C */
#define M6811__RES6 0x06 /* Unused/Reserved */
#define M6811_DDRC 0x07 /* Data direction register for port C */
#define M6811_PORTD 0x08 /* Port D register */
#define M6811_DDRD 0x09 /* Data direction register for port D */
#define M6811_PORTE 0x0A /* Port E input register */
#define M6811_CFORC 0x0B /* Compare Force Register */
#define M6811_OC1M 0x0C /* OC1 Action Mask register */
#define M6811_OC1D 0x0D /* OC1 Action Data register */
#define M6811_TCTN 0x0E /* Timer Counter Register */
#define M6811_TCTN_H 0x0E /* " " " High part */
#define M6811_TCTN_L 0x0F /* " " " Low part */
#define M6811_TIC1 0x10 /* Input capture 1 register */
#define M6811_TIC1_H 0x10 /* " " " High part */
#define M6811_TIC1_L 0x11 /* " " " Low part */
#define M6811_TIC2 0x12 /* Input capture 2 register */
#define M6811_TIC2_H 0x12 /* " " " High part */
#define M6811_TIC2_L 0x13 /* " " " Low part */
#define M6811_TIC3 0x14 /* Input capture 3 register */
#define M6811_TIC3_H 0x14 /* " " " High part */
#define M6811_TIC3_L 0x15 /* " " " Low part */
#define M6811_TOC1 0x16 /* Output Compare 1 register */
#define M6811_TOC1_H 0x16 /* " " " High part */
#define M6811_TOC1_L 0x17 /* " " " Low part */
#define M6811_TOC2 0x18 /* Output Compare 2 register */
#define M6811_TOC2_H 0x18 /* " " " High part */
#define M6811_TOC2_L 0x19 /* " " " Low part */
#define M6811_TOC3 0x1A /* Output Compare 3 register */
#define M6811_TOC3_H 0x1A /* " " " High part */
#define M6811_TOC3_L 0x1B /* " " " Low part */
#define M6811_TOC4 0x1C /* Output Compare 4 register */
#define M6811_TOC4_H 0x1C /* " " " High part */
#define M6811_TOC4_L 0x1D /* " " " Low part */
#define M6811_TOC5 0x1E /* Output Compare 5 register */
#define M6811_TOC5_H 0x1E /* " " " High part */
#define M6811_TOC5_L 0x1F /* " " " Low part */
#define M6811_TCTL1 0x20 /* Timer Control register 1 */
#define M6811_TCTL2 0x21 /* Timer Control register 2 */
#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */
#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */
#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */
#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */
#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */
#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */
#define M6811_SPCR 0x28 /* SPI Control register */
#define M6811_SPSR 0x29 /* SPI Status register */
#define M6811_SPDR 0x2A /* SPI Data register */
#define M6811_BAUD 0x2B /* SCI Baud register */
#define M6811_SCCR1 0x2C /* SCI Control register 1 */
#define M6811_SCCR2 0x2D /* SCI Control register 2 */
#define M6811_SCSR 0x2E /* SCI Status register */
#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */
#define M6811_ADCTL 0x30 /* A/D Control register */
#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */
#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */
#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */
#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */
#define M6811__RES35 0x35
#define M6811__RES36 0x36
#define M6811__RES37 0x37
#define M6811__RES38 0x38
#define M6811_OPTION 0x39 /* System Configuration Options */
#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */
#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */
#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */
#define M6811_INIT 0x3D /* Ram and I/O mapping register */
#define M6811_TEST1 0x3E /* Factory test control register */
#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */
/* Flags of the CONFIG register (in EEPROM). */
#define M6811_NOSEC 0x08 /* Security mode disable */
#define M6811_NOCOP 0x04 /* COP system disable */
#define M6811_ROMON 0x02 /* Enable on-chip rom */
#define M6811_EEON 0x01 /* Enable on-chip eeprom */
/* Flags of the PPROG register. */
#define M6811_BYTE 0x10 /* Byte mode */
#define M6811_ROW 0x08 /* Row mode */
#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */
#define M6811_EELAT 0x02 /* EEPROM Latch Control */
#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */
/* Flags of the PIOC register. */
#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */
#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */
#define M6811_CWOM 0x20 /* Port C Wire OR mode */
#define M6811_HNDS 0x10 /* Handshake mode */
#define M6811_OIN 0x08 /* Output or Input handshaking */
#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */
#define M6811_EGA 0x02 /* Active Edge for Strobe A */
#define M6811_INVB 0x01 /* Invert Strobe B */
/* Flags of the SCCR1 register. */
#define M6811_R8 0x80 /* Receive Data bit 8 */
#define M6811_T8 0x40 /* Transmit data bit 8 */
#define M6811__SCCR1_5 0x20 /* Unused */
#define M6811_M 0x10 /* SCI Character length */
#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */
/* Flags of the SCCR2 register. */
#define M6811_TIE 0x80 /* Transmit Interrupt enable */
#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */
#define M6811_RIE 0x20 /* Receive Interrupt Enable */
#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */
#define M6811_TE 0x08 /* Transmit Enable */
#define M6811_RE 0x04 /* Receive Enable */
#define M6811_RWU 0x02 /* Receiver Wake Up */
#define M6811_SBK 0x01 /* Send Break */
/* Flags of the SCSR register. */
#define M6811_TDRE 0x80 /* Transmit Data Register Empty */
#define M6811_TC 0x40 /* Transmit Complete */
#define M6811_RDRF 0x20 /* Receive Data Register Full */
#define M6811_IDLE 0x10 /* Idle Line Detect */
#define M6811_OR 0x08 /* Overrun Error */
#define M6811_NF 0x04 /* Noise Flag */
#define M6811_FE 0x02 /* Framing Error */
#define M6811__SCSR_0 0x01 /* Unused */
/* Flags of the BAUD register. */
#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */
#define M6811__BAUD_6 0x40 /* Not used */
#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */
#define M6811_SCP0 0x10
#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */
#define M6811_SCR2 0x04 /* SCI Baud rate select */
#define M6811_SCR1 0x02
#define M6811_SCR0 0x01
#define M6811_BAUD_DIV_1 (0)
#define M6811_BAUD_DIV_3 (M6811_SCP0)
#define M6811_BAUD_DIV_4 (M6811_SCP1)
#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0)
/* Flags of the SPCR register. */
#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */
#define M6811_SPE 0x40 /* Serial Peripheral System Enable */
#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */
#define M6811_MSTR 0x10 /* Master Mode Select */
#define M6811_CPOL 0x08 /* Clock Polarity */
#define M6811_CPHA 0x04 /* Clock Phase */
#define M6811_SPR1 0x02 /* SPI Clock Rate Select */
#define M6811_SPR0 0x01
/* Flags of the SPSR register. */
#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */
#define M6811_WCOL 0x40 /* Write Collision */
#define M6811_MODF 0x10 /* Mode Fault */
/* Flags of the ADCTL register. */
#define M6811_CCF 0x80 /* Conversions Complete Flag */
#define M6811_SCAN 0x20 /* Continuous Scan Control */
#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */
#define M6811_CD 0x08 /* Channel Select D */
#define M6811_CC 0x04 /* C */
#define M6811_CB 0x02 /* B */
#define M6811_CA 0x01 /* A */
/* Flags of the CFORC register. */
#define M6811_FOC1 0x80 /* Force Output Compare 1 */
#define M6811_FOC2 0x40 /* 2 */
#define M6811_FOC3 0x20 /* 3 */
#define M6811_FOC4 0x10 /* 4 */
#define M6811_FOC5 0x08 /* 5 */
/* Flags of the OC1M register. */
#define M6811_OC1M7 0x80 /* Output Compare 7 */
#define M6811_OC1M6 0x40 /* 6 */
#define M6811_OC1M5 0x20 /* 5 */
#define M6811_OC1M4 0x10 /* 4 */
#define M6811_OC1M3 0x08 /* 3 */
/* Flags of the OC1D register. */
#define M6811_OC1D7 0x80
#define M6811_OC1D6 0x40
#define M6811_OC1D5 0x20
#define M6811_OC1D4 0x10
#define M6811_OC1D3 0x08
/* Flags of the TCTL1 register. */
#define M6811_OM2 0x80 /* Output Mode 2 */
#define M6811_OL2 0x40 /* Output Level 2 */
#define M6811_OM3 0x20
#define M6811_OL3 0x10
#define M6811_OM4 0x08
#define M6811_OL4 0x04
#define M6811_OM5 0x02
#define M6811_OL5 0x01
/* Flags of the TCTL2 register. */
#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */
#define M6811_EDG1A 0x10
#define M6811_EDG2B 0x08 /* Input 2 */
#define M6811_EDG2A 0x04
#define M6811_EDG3B 0x02 /* Input 3 */
#define M6811_EDG3A 0x01
/* Flags of the TMSK1 register. */
#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */
#define M6811_OC2I 0x40 /* 2 */
#define M6811_OC3I 0x20 /* 3 */
#define M6811_OC4I 0x10 /* 4 */
#define M6811_OC5I 0x08 /* 5 */
#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */
#define M6811_IC2I 0x02 /* 2 */
#define M6811_IC3I 0x01 /* 3 */
/* Flags of the TFLG1 register. */
#define M6811_OC1F 0x80 /* Output Compare 1 Flag */
#define M6811_OC2F 0x40 /* 2 */
#define M6811_OC3F 0x20 /* 3 */
#define M6811_OC4F 0x10 /* 4 */
#define M6811_OC5F 0x08 /* 5 */
#define M6811_IC1F 0x04 /* Input Capture 1 Flag */
#define M6811_IC2F 0x02 /* 2 */
#define M6811_IC3F 0x01 /* 3 */
/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */
#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */
#define M6811_RTII 0x40 /* RTI Interrupt Enable */
#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */
#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */
#define M6811_PR1 0x02 /* Timer prescaler */
#define M6811_PR0 0x01 /* Timer prescaler */
#define M6811_TPR_1 0x00 /* " " prescale div 1 */
#define M6811_TPR_4 0x01 /* " " prescale div 4 */
#define M6811_TPR_8 0x02 /* " " prescale div 8 */
#define M6811_TPR_16 0x03 /* " " prescale div 16 */
/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */
#define M6811_TOF 0x80 /* Timer overflow bit */
#define M6811_RTIF 0x40 /* Read time interrupt flag */
#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */
#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */
/* Flags of Pulse Accumulator Control Register (PACTL). */
#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */
#define M6811_PAEN 0x40 /* Pulse accumulator system enable */
#define M6811_PAMOD 0x20 /* Pulse accumulator mode */
#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */
#define M6811_RTR1 0x02 /* RTI Interrupt rates select */
#define M6811_RTR0 0x01 /* " " " " */
/* Flags of the Options register. */
#define M6811_ADPU 0x80 /* A/D Powerup */
#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */
#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */
#define M6811_DLY 0x10 /* Stop exit turn on delay */
#define M6811_CME 0x08 /* Clock Monitor enable */
#define M6811_CR1 0x02 /* COP timer rate select */
#define M6811_CR0 0x01 /* COP timer rate select */
/* Flags of the HPRIO register. */
#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */
#define M6811_SMOD 0x40 /* Special Mode */
#define M6811_MDA 0x20 /* Mode Select A */
#define M6811_IRV 0x10 /* Internal Read Visibility */
#define M6811_PSEL3 0x08 /* Priority Select */
#define M6811_PSEL2 0x04
#define M6811_PSEL1 0x02
#define M6811_PSEL0 0x01
/* Some insns used by gas to turn relative branches into absolute ones. */
#define M6811_BRA 0x20
#define M6811_JMP 0x7e
#define M6811_BSR 0x8d
#define M6811_JSR 0xbd
#define M6812_JMP 0x06
#define M6812_BSR 0x07
#define M6812_JSR 0x16
/* Instruction code pages. Code page 1 is the default. */
/*#define M6811_OPCODE_PAGE1 0x00*/
#define M6811_OPCODE_PAGE2 0x18
#define M6811_OPCODE_PAGE3 0x1A
#define M6811_OPCODE_PAGE4 0xCD
/* 68HC11 operands formats as stored in the m6811_opcode table. These
flags do not correspond to anything in the 68HC11 or 68HC12.
They are only used by GAS to recognize operands. */
#define M6811_OP_NONE 0 /* No operand */
#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */
#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */
#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */
#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */
#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */
#define M6812_OP_REG 0x0020 /* Register operand 1 */
#define M6812_OP_REG_2 0x0040 /* Register operand 2 */
#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */
#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */
#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */
#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */
#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */
#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */
#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */
#define M6812_OP_PAGE 0x4000 /* Page number */
#define M6811_OP_MASK 0x07FFF
#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */
#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */
#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */
#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */
#define M6811_OP_PAGE1 0x0000
#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */
#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */
#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */
#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */
#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */
#define M6812_ACC_IND 0x00800000 /* [D,r] */
#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */
#define M6812_PRE_DEC 0x02000000 /* n,-r */
#define M6812_POST_INC 0x04000000 /* n,r+ */
#define M6812_POST_DEC 0x08000000 /* n,r- */
#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */
#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */
#define M6812_OP_IDX_P2 0x40000000
/* XGATE defines.
These overlap with HC11/12 as above but not used at the same time. */
#define M68XG_OP_NONE 0x0001
#define M68XG_OP_IMM3 0x0002
#define M68XG_OP_R 0x0004
#define M68XG_OP_R_R 0x0008
#define M68XG_OP_R_IMM4 0x0010
#define M68XG_OP_R_R_R 0x0020
#define M68XG_OP_REL9 0x0040
#define M68XG_OP_REL10 0x0080
#define M68XG_OP_R_R_OFFS5 0x0100
#define M68XG_OP_RD_RB_RI 0x0200
#define M68XG_OP_RD_RB_RIp 0x0400
#define M68XG_OP_RD_RB_mRI 0x0800
#define M68XG_OP_R_IMM8 0x1000
#define M68XG_OP_R_IMM16 0x2000
#define M68XG_OP_REG 0x4000 /* Register operand 1. */
#define M68XG_OP_REG_2 0x8000 /* Register operand 2. */
#define M68XG_MAX_OPERANDS 3 /* Max operands of triadic r1, r2, r3. */
/* Markers to identify some instructions. */
#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */
#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */
#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */
#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */
#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */
#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */
#define M6812_OP_TBCC_MARKER 0x01000000
/* XGATE markers. */
#define M68XG_OP_B_MARKER 0x04000000 /* bXX rel9 */
#define M68XG_OP_BRA_MARKER 0x02000000 /* bra rel10 */
#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */
#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */
#define M6811_OP_LOW_ADDR 0x02000000
#define M68HC12_BANK_VIRT 0x010000
#define M68HC12_BANK_MASK 0x00003fff
#define M68HC12_BANK_BASE 0x00008000
#define M68HC12_BANK_SHIFT 14
#define M68HC12_BANK_PAGE_MASK 0x0ff
/* CPU identification. */
#define cpu6811 0x01
#define cpu6812 0x02
#define cpu6812s 0x04
#define cpu9s12x 0x08 /* 9S12X main cpu. */
#define cpuxgate 0x10 /* The XGATE module itself. */
/* The opcode table is an array of struct m68hc11_opcode. */
struct m68hc11_opcode
{
const char * name; /* Op-code name. */
long format;
unsigned char size;
unsigned int opcode;
unsigned char cycles_low;
unsigned char cycles_high;
unsigned char set_flags_mask;
unsigned char clr_flags_mask;
unsigned char chg_flags_mask;
unsigned char arch;
unsigned int xg_mask; /* Mask with zero in register place for xgate. */
};
/* Alias definition for 68HC12. */
struct m68hc12_opcode_alias
{
const char* name;
const char* translation;
unsigned char size;
unsigned char code1;
unsigned char code2;
};
/* The opcode table. The table contains all the opcodes (all pages).
You can't rely on the order. */
extern const struct m68hc11_opcode m68hc11_opcodes[];
extern const int m68hc11_num_opcodes;
/* Alias table for 68HC12. It translates some 68HC11 insn which are not
implemented in 68HC12 but have equivalent translations. */
extern const struct m68hc12_opcode_alias m68hc12_alias[];
extern const int m68hc12_num_alias;
#endif /* _OPCODE_M68HC11_H */

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/* Opcode table header for m680[01234]0/m6888[12]/m68851.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
2003, 2004, 2006, 2010 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* These are used as bit flags for the arch field in the m68k_opcode
structure. */
#define _m68k_undef 0
#define m68000 0x001
#define m68010 0x002
#define m68020 0x004
#define m68030 0x008
#define m68040 0x010
#define m68060 0x020
#define m68881 0x040
#define m68851 0x080
#define cpu32 0x100 /* e.g., 68332 */
#define fido_a 0x200
#define m68k_mask 0x3ff
#define mcfmac 0x400 /* ColdFire MAC. */
#define mcfemac 0x800 /* ColdFire EMAC. */
#define cfloat 0x1000 /* ColdFire FPU. */
#define mcfhwdiv 0x2000 /* ColdFire hardware divide. */
#define mcfisa_a 0x4000 /* ColdFire ISA_A. */
#define mcfisa_aa 0x8000 /* ColdFire ISA_A+. */
#define mcfisa_b 0x10000 /* ColdFire ISA_B. */
#define mcfisa_c 0x20000 /* ColdFire ISA_C. */
#define mcfusp 0x40000 /* ColdFire USP instructions. */
#define mcf_mask 0x7e400
/* Handy aliases. */
#define m68040up (m68040 | m68060)
#define m68030up (m68030 | m68040up)
#define m68020up (m68020 | m68030up)
#define m68010up (m68010 | cpu32 | fido_a | m68020up)
#define m68000up (m68000 | m68010up)
#define mfloat (m68881 | m68040 | m68060)
#define mmmu (m68851 | m68030 | m68040 | m68060)
/* The structure used to hold information for an opcode. */
struct m68k_opcode
{
/* The opcode name. */
const char *name;
/* The pseudo-size of the instruction(in bytes). Used to determine
number of bytes necessary to disassemble the instruction. */
unsigned int size;
/* The opcode itself. */
unsigned long opcode;
/* The mask used by the disassembler. */
unsigned long match;
/* The arguments. */
const char *args;
/* The architectures which support this opcode. */
unsigned int arch;
};
/* The structure used to hold information for an opcode alias. */
struct m68k_opcode_alias
{
/* The alias name. */
const char *alias;
/* The instruction for which this is an alias. */
const char *primary;
};
/* We store four bytes of opcode for all opcodes because that is the
most any of them need. The actual length of an instruction is
always at least 2 bytes, and is as much longer as necessary to hold
the operands it has.
The match field is a mask saying which bits must match particular
opcode in order for an instruction to be an instance of that
opcode.
The args field is a string containing two characters for each
operand of the instruction. The first specifies the kind of
operand; the second, the place it is stored.
If the first char of args is '.', it indicates that the opcode is
two words. This is only necessary when the match field does not
have any bits set in the second opcode word. Such a '.' is skipped
for operand processing. */
/* Kinds of operands:
Characters used: AaBbCcDdEeFfGgHIiJjKkLlMmnOopQqRrSsTtUuVvWwXxYyZz01234|*~%;@!&$?/<>#^+-
D data register only. Stored as 3 bits.
A address register only. Stored as 3 bits.
a address register indirect only. Stored as 3 bits.
R either kind of register. Stored as 4 bits.
r either kind of register indirect only. Stored as 4 bits.
At the moment, used only for cas2 instruction.
F floating point coprocessor register only. Stored as 3 bits.
O an offset (or width): immediate data 0-31 or data register.
Stored as 6 bits in special format for BF... insns.
+ autoincrement only. Stored as 3 bits (number of the address register).
- autodecrement only. Stored as 3 bits (number of the address register).
Q quick immediate data. Stored as 3 bits.
This matches an immediate operand only when value is in range 1 .. 8.
M moveq immediate data. Stored as 8 bits.
This matches an immediate operand only when value is in range -128..127
T trap vector immediate data. Stored as 4 bits.
k K-factor for fmove.p instruction. Stored as a 7-bit constant or
a three bit register offset, depending on the field type.
# immediate data. Stored in special places (b, w or l)
which say how many bits to store.
^ immediate data for floating point instructions. Special places
are offset by 2 bytes from '#'...
B pc-relative address, converted to an offset
that is treated as immediate data.
d displacement and register. Stores the register as 3 bits
and stores the displacement in the entire second word.
C the CCR. No need to store it; this is just for filtering validity.
S the SR. No need to store, just as with CCR.
U the USP. No need to store, just as with CCR.
E the MAC ACC. No need to store, just as with CCR.
e the EMAC ACC[0123].
G the MAC/EMAC MACSR. No need to store, just as with CCR.
g the EMAC ACCEXT{01,23}.
H the MASK. No need to store, just as with CCR.
i the MAC/EMAC scale factor.
I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
extracted from the 'd' field of word one, which means that an extended
coprocessor opcode can be skipped using the 'i' place, if needed.
s System Control register for the floating point coprocessor.
J Misc register for movec instruction, stored in 'j' format.
Possible values:
0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
0x003 TC MMU Translation Control [60, 40]
0x004 ITT0 Instruction Transparent
Translation reg 0 [60, 40]
0x005 ITT1 Instruction Transparent
Translation reg 1 [60, 40]
0x006 DTT0 Data Transparent
Translation reg 0 [60, 40]
0x007 DTT1 Data Transparent
Translation reg 1 [60, 40]
0x008 BUSCR Bus Control Register [60]
0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
0x802 CAAR Cache Address Register [ 30, 20]
0x803 MSP Master Stack Pointer [ 40, 30, 20]
0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
0x805 MMUSR MMU Status reg [ 40]
0x806 URP User Root Pointer [60, 40]
0x807 SRP Supervisor Root Pointer [60, 40]
0x808 PCR Processor Configuration reg [60]
0xC00 ROMBAR ROM Base Address Register [520X]
0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
0xC0F MBAR0 RAM Base Address Register 0 [520X]
0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
L Register list of the type d0-d7/a0-a7 etc.
(New! Improved! Can also hold fp0-fp7, as well!)
The assembler tries to see if the registers match the insn by
looking at where the insn wants them stored.
l Register list like L, but with all the bits reversed.
Used for going the other way. . .
c cache identifier which may be "nc" for no cache, "ic"
for instruction cache, "dc" for data cache, or "bc"
for both caches. Used in cinv and cpush. Always
stored in position "d".
u Any register, with ``upper'' or ``lower'' specification. Used
in the mac instructions with size word.
The remainder are all stored as 6 bits using an address mode and a
register number; they differ in which addressing modes they match.
* all (modes 0-6,7.0-4)
~ alterable memory (modes 2-6,7.0,7.1)
(not 0,1,7.2-4)
% alterable (modes 0-6,7.0,7.1)
(not 7.2-4)
; data (modes 0,2-6,7.0-4)
(not 1)
@ data, but not immediate (modes 0,2-6,7.0-3)
(not 1,7.4)
! control (modes 2,5,6,7.0-3)
(not 0,1,3,4,7.4)
& alterable control (modes 2,5,6,7.0,7.1)
(not 0,1,3,4,7.2-4)
$ alterable data (modes 0,2-6,7.0,7.1)
(not 1,7.2-4)
? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
(not 1,3,4,7.2-4)
/ control, or data register (modes 0,2,5,6,7.0-3)
(not 1,3,4,7.4)
> *save operands (modes 2,4,5,6,7.0,7.1)
(not 0,1,3,7.2-4)
< *restore operands (modes 2,3,5,6,7.0-3)
(not 0,1,4,7.4)
coldfire move operands:
m (modes 0-4)
n (modes 5,7.2)
o (modes 6,7.0,7.1,7.3,7.4)
p (modes 0-5)
coldfire bset/bclr/btst/mulsl/mulul operands:
q (modes 0,2-5)
v (modes 0,2-5,7.0,7.1)
b (modes 0,2-5,7.2)
w (modes 2-5,7.2)
y (modes 2,5)
z (modes 2,5,7.2)
x mov3q immediate operand.
j coprocessor ET operand.
K coprocessor command number.
4 (modes 2,3,4,5)
*/
/* For the 68851: */
/* I didn't use much imagination in choosing the
following codes, so many of them aren't very
mnemonic. -rab
0 32 bit pmmu register
Possible values:
000 TC Translation Control Register (68030, 68851)
1 16 bit pmmu register
111 AC Access Control (68851)
2 8 bit pmmu register
100 CAL Current Access Level (68851)
101 VAL Validate Access Level (68851)
110 SCC Stack Change Control (68851)
3 68030-only pmmu registers (32 bit)
010 TT0 Transparent Translation reg 0
(aka Access Control reg 0 -- AC0 -- on 68ec030)
011 TT1 Transparent Translation reg 1
(aka Access Control reg 1 -- AC1 -- on 68ec030)
W wide pmmu registers
Possible values:
001 DRP Dma Root Pointer (68851)
010 SRP Supervisor Root Pointer (68030, 68851)
011 CRP Cpu Root Pointer (68030, 68851)
f function code register (68030, 68851)
0 SFC
1 DFC
V VAL register only (68851)
X BADx, BACx (16 bit)
100 BAD Breakpoint Acknowledge Data (68851)
101 BAC Breakpoint Acknowledge Control (68851)
Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
Z PCSR (68851)
| memory (modes 2-6, 7.*)
t address test level (68030 only)
Stored as 3 bits, range 0-7.
Also used for breakpoint instruction now.
*/
/* Places to put an operand, for non-general operands:
Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
s source, low bits of first word.
d dest, shifted 9 in first word
1 second word, shifted 12
2 second word, shifted 6
3 second word, shifted 0
4 third word, shifted 12
5 third word, shifted 6
6 third word, shifted 0
7 second word, shifted 7
8 second word, shifted 10
9 second word, shifted 5
E second word, shifted 9
D store in both place 1 and place 3; for divul and divsl.
B first word, low byte, for branch displacements
W second word (entire), for branch displacements
L second and third words (entire), for branch displacements
(also overloaded for move16)
b second word, low byte
w second word (entire) [variable word/long branch offset for dbra]
W second word (entire) (must be signed 16 bit value)
l second and third word (entire)
g variable branch offset for bra and similar instructions.
The place to store depends on the magnitude of offset.
t store in both place 7 and place 8; for floating point operations
c branch offset for cpBcc operations.
The place to store is word two if bit six of word one is zero,
and words two and three if bit six of word one is one.
i Increment by two, to skip over coprocessor extended operands. Only
works with the 'I' format.
k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
Also used for dynamic fmovem instruction.
C floating point coprocessor constant - 7 bits. Also used for static
K-factors...
j Movec register #, stored in 12 low bits of second word.
m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
and remaining 3 bits of register shifted 9 bits in first word.
Indicate upper/lower in 1 bit shifted 7 bits in second word.
Use with `R' or `u' format.
n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
with MSB shifted 6 bits in first word and remaining 3 bits of
register shifted 9 bits in first word. No upper/lower
indication is done.) Use with `R' or `u' format.
o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
Indicate upper/lower in 1 bit shifted 7 bits in second word.
Use with `R' or `u' format.
M For M[S]ACw; 4 bits in low bits of first word. Indicate
upper/lower in 1 bit shifted 6 bits in second word. Use with
`R' or `u' format.
N For M[S]ACw; 4 bits in low bits of second word. Indicate
upper/lower in 1 bit shifted 6 bits in second word. Use with
`R' or `u' format.
h shift indicator (scale factor), 1 bit shifted 10 in second word
Places to put operand, for general operands:
d destination, shifted 6 bits in first word
b source, at low bit of first word, and immediate uses one byte
w source, at low bit of first word, and immediate uses two bytes
l source, at low bit of first word, and immediate uses four bytes
s source, at low bit of first word.
Used sometimes in contexts where immediate is not allowed anyway.
f single precision float, low bit of 1st word, immediate uses 4 bytes
F double precision float, low bit of 1st word, immediate uses 8 bytes
x extended precision float, low bit of 1st word, immediate uses 12 bytes
p packed float, low bit of 1st word, immediate uses 12 bytes
G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
F EMAC ACCx
f EMAC ACCy
I MAC/EMAC scale factor
/ Like 's', but set 2nd word, bit 5 if trailing_ampersand set
] first word, bit 10
*/
extern const struct m68k_opcode m68k_opcodes[];
extern const struct m68k_opcode_alias m68k_opcode_aliases[];
extern const int m68k_numopcodes, m68k_numaliases;
/* end of m68k-opcode.h */

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/* Table of opcodes for the Motorola M88k family.
Copyright 1989, 1990, 1991, 1993, 2001, 2002, 2010
Free Software Foundation, Inc.
This file is part of GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/*
* Disassembler Instruction Table
*
* The first field of the table is the opcode field. If an opcode
* is specified which has any non-opcode bits on, a system error
* will occur when the system attempts the install it into the
* instruction table. The second parameter is a pointer to the
* instruction mnemonic. Each operand is specified by offset, width,
* and type. The offset is the bit number of the least significant
* bit of the operand with bit 0 being the least significant bit of
* the instruction. The width is the number of bits used to specify
* the operand. The type specifies the output format to be used for
* the operand. The valid formats are: register, register indirect,
* hex constant, and bit field specification. The last field is a
* pointer to the next instruction in the linked list. These pointers
* are initialized by init_disasm().
*
* Revision History
*
* Revision 1.0 11/08/85 Creation date
* 1.1 02/05/86 Updated instruction mnemonic table MD
* 1.2 06/16/86 Updated SIM_FLAGS for floating point
* 1.3 09/20/86 Updated for new encoding
* 05/11/89 R. Trawick adapted from Motorola disassembler
*/
#include <stdio.h>
/* Define the number of bits in the primary opcode field of the instruction,
the destination field, the source 1 and source 2 fields. */
/* Size of opcode field. */
#define OP 8
/* Size of destination. */
#define DEST 6
/* Size of source1. */
#define SOURCE1 6
/* Size of source2. */
#define SOURCE2 6
/* Number of registers. */
#define REGs 32
/* Type definitions. */
typedef unsigned int UINT;
#define WORD long
#define FLAG unsigned
#define STATE short
/* The next four equates define the priorities that the various classes
* of instructions have regarding writing results back into registers and
* signalling exceptions. */
/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */
#undef PMEM
/* Integer priority. */
#define PINT 0
/* Floating point priority. */
#define PFLT 1
/* Memory priority. */
#define PMEM 2
/* Not applicable, instruction doesn't write to regs. */
#define NA 3
/* Highest of these priorities. */
#define HIPRI 3
/* The instruction registers are an artificial mechanism to speed up
* simulator execution. In the real processor, an instruction register
* is 32 bits wide. In the simulator, the 32 bit instruction is kept in
* a structure field called rawop, and the instruction is partially decoded,
* and split into various fields and flags which make up the other fields
* of the structure.
* The partial decode is done when the instructions are initially loaded
* into simulator memory. The simulator code memory is not an array of
* 32 bit words, but is an array of instruction register structures.
* Yes this wastes memory, but it executes much quicker.
*/
struct IR_FIELDS
{
unsigned op:OP,
dest: DEST,
src1: SOURCE1,
src2: SOURCE2;
int ltncy,
extime,
/* Writeback priority. */
wb_pri;
/* Immediate size. */
unsigned imm_flags:2,
/* Register source 1 used. */
rs1_used:1,
/* Register source 2 used. */
rs2_used:1,
/* Register source/dest. used. */
rsd_used:1,
/* Complement. */
c_flag:1,
/* Upper half word. */
u_flag:1,
/* Execute next. */
n_flag:1,
/* Uses writeback slot. */
wb_flag:1,
/* Dest size. */
dest_64:1,
/* Source 1 size. */
s1_64:1,
/* Source 2 size. */
s2_64:1,
scale_flag:1,
/* Scaled register. */
brk_flg:1;
};
struct mem_segs
{
/* Pointer (returned by calloc) to segment. */
struct mem_wrd *seg;
/* Base load address from file headers. */
unsigned long baseaddr;
/* Ending address of segment. */
unsigned long endaddr;
/* Segment control flags (none defined). */
int flags;
};
#define MAXSEGS (10) /* max number of segment allowed */
#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */
#if 0
#define BRK_RD (0x01) /* break on memory read */
#define BRK_WR (0x02) /* break on memory write */
#define BRK_EXEC (0x04) /* break on execution */
#define BRK_CNT (0x08) /* break on terminal count */
#endif
struct mem_wrd
{
/* Simulator instruction break down. */
struct IR_FIELDS opcode;
union {
/* Memory element break down. */
unsigned long l;
unsigned short s[2];
unsigned char c[4];
} mem;
};
/* Size of each 32 bit memory model. */
#define MEMWRDSIZE (sizeof (struct mem_wrd))
extern struct mem_segs memory[];
extern struct PROCESSOR m78000;
struct PROCESSOR
{
unsigned WORD
/* Execute instruction pointer. */
ip,
/* Vector base register. */
vbr,
/* Processor status register. */
psr;
/* Source 1. */
WORD S1bus,
/* Source 2. */
S2bus,
/* Destination. */
Dbus,
/* Data address bus. */
DAbus,
ALU,
/* Data registers. */
Regs[REGs],
/* Max clocks before reg is available. */
time_left[REGs],
/* Writeback priority of reg. */
wb_pri[REGs],
/* Integer unit control regs. */
SFU0_regs[REGs],
/* Floating point control regs. */
SFU1_regs[REGs],
Scoreboard[REGs],
Vbr;
unsigned WORD scoreboard,
Psw,
Tpsw;
/* Waiting for a jump instruction. */
FLAG jump_pending:1;
};
/* Size of immediate field. */
#define i26bit 1
#define i16bit 2
#define i10bit 3
/* Definitions for fields in psr. */
#define psr_mode 31
#define psr_rbo 30
#define psr_ser 29
#define psr_carry 28
#define psr_sf7m 11
#define psr_sf6m 10
#define psr_sf5m 9
#define psr_sf4m 8
#define psr_sf3m 7
#define psr_sf2m 6
#define psr_sf1m 5
#define psr_mam 4
#define psr_inm 3
#define psr_exm 2
#define psr_trm 1
#define psr_ovfm 0
/* The 1 clock operations. */
#define ADDU 1
#define ADDC 2
#define ADDUC 3
#define ADD 4
#define SUBU ADD+1
#define SUBB ADD+2
#define SUBUB ADD+3
#define SUB ADD+4
#define AND_ ADD+5
#define OR ADD+6
#define XOR ADD+7
#define CMP ADD+8
/* Loads. */
#define LDAB CMP+1
#define LDAH CMP+2
#define LDA CMP+3
#define LDAD CMP+4
#define LDB LDAD+1
#define LDH LDAD+2
#define LD LDAD+3
#define LDD LDAD+4
#define LDBU LDAD+5
#define LDHU LDAD+6
/* Stores. */
#define STB LDHU+1
#define STH LDHU+2
#define ST LDHU+3
#define STD LDHU+4
/* Exchange. */
#define XMEMBU LDHU+5
#define XMEM LDHU+6
/* Branches. */
#define JSR STD+1
#define BSR STD+2
#define BR STD+3
#define JMP STD+4
#define BB1 STD+5
#define BB0 STD+6
#define RTN STD+7
#define BCND STD+8
/* Traps. */
#define TB1 BCND+1
#define TB0 BCND+2
#define TCND BCND+3
#define RTE BCND+4
#define TBND BCND+5
/* Misc. */
#define MUL TBND + 1
#define DIV MUL +2
#define DIVU MUL +3
#define MASK MUL +4
#define FF0 MUL +5
#define FF1 MUL +6
#define CLR MUL +7
#define SET MUL +8
#define EXT MUL +9
#define EXTU MUL +10
#define MAK MUL +11
#define ROT MUL +12
/* Control register manipulations. */
#define LDCR ROT +1
#define STCR ROT +2
#define XCR ROT +3
#define FLDCR ROT +4
#define FSTCR ROT +5
#define FXCR ROT +6
#define NOP XCR +1
/* Floating point instructions. */
#define FADD NOP +1
#define FSUB NOP +2
#define FMUL NOP +3
#define FDIV NOP +4
#define FSQRT NOP +5
#define FCMP NOP +6
#define FIP NOP +7
#define FLT NOP +8
#define INT NOP +9
#define NINT NOP +10
#define TRNC NOP +11
#define FLDC NOP +12
#define FSTC NOP +13
#define FXC NOP +14
#define UEXT(src,off,wid) \
((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
#define SEXT(src,off,wid) \
(((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
#define MAKE(src,off,wid) \
((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
#define opword(n) (unsigned long) (memaddr->mem.l)
/* Constants and masks. */
#define SFU0 0x80000000
#define SFU1 0x84000000
#define SFU7 0x9c000000
#define RRI10 0xf0000000
#define RRR 0xf4000000
#define SFUMASK 0xfc00ffe0
#define RRRMASK 0xfc00ffe0
#define RRI10MASK 0xfc00fc00
#define DEFMASK 0xfc000000
#define CTRL 0x0000f000
#define CTRLMASK 0xfc00f800
/* Operands types. */
enum operand_type
{
HEX = 1,
REG = 2,
CONT = 3,
IND = 3,
BF = 4,
/* Scaled register. */
REGSC = 5,
/* Control register. */
CRREG = 6,
/* Floating point control register. */
FCRREG = 7,
PCREL = 8,
CONDMASK = 9,
/* Extended register. */
XREG = 10,
/* Decimal. */
DEC = 11
};
/* Hashing specification. */
#define HASHVAL 79
/* Structure templates. */
typedef struct
{
unsigned int offset;
unsigned int width;
enum operand_type type;
} OPSPEC;
struct SIM_FLAGS
{
int ltncy, /* latency (max number of clocks needed to execute). */
extime, /* execution time (min number of clocks needed to execute). */
wb_pri; /* writeback slot priority. */
unsigned op:OP, /* simulator version of opcode. */
imm_flags:2, /* 10,16 or 26 bit immediate flags. */
rs1_used:1, /* register source 1 used. */
rs2_used:1, /* register source 2 used. */
rsd_used:1, /* register source/dest used. */
c_flag:1, /* complement. */
u_flag:1, /* upper half word. */
n_flag:1, /* execute next. */
wb_flag:1, /* uses writeback slot. */
dest_64:1, /* double precision dest. */
s1_64:1, /* double precision source 1. */
s2_64:1, /* double precision source 2. */
scale_flag:1; /* register is scaled. */
};
typedef struct INSTRUCTAB {
unsigned int opcode;
char *mnemonic;
OPSPEC op1,op2,op3;
struct SIM_FLAGS flgs;
} INSTAB;
#define NO_OPERAND {0,0,0}
extern const INSTAB instructions[];
/*
* Local Variables:
* fill-column: 131
* End:
*/

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/* mmix.h -- Header file for MMIX opcode table
Copyright (C) 2001, 2003, 2010 Free Software Foundation, Inc.
Written by Hans-Peter Nilsson (hp@bitrange.com)
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* We could have just a char*[] table indexed by the register number, but
that would not allow for synonyms. The table is terminated with an
entry with a NULL name. */
struct mmix_spec_reg
{
const char *name;
unsigned int number;
};
/* General indication of the type of instruction. */
enum mmix_insn_type
{
mmix_type_pseudo,
mmix_type_normal,
mmix_type_branch,
mmix_type_condbranch,
mmix_type_memaccess_octa,
mmix_type_memaccess_tetra,
mmix_type_memaccess_wyde,
mmix_type_memaccess_byte,
mmix_type_memaccess_block,
mmix_type_jsr
};
/* Type of operands an instruction takes. Use when parsing assembly code
and disassembling. */
enum mmix_operands_type
{
mmix_operands_none = 0,
/* All operands are registers: "$X,$Y,$Z". */
mmix_operands_regs,
/* "$X,YZ", like SETH. */
mmix_operands_reg_yz,
/* The regular "$X,$Y,$Z|Z".
The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is
assumed. */
mmix_operands_regs_z_opt,
/* The regular "$X,$Y,$Z|Z". */
mmix_operands_regs_z,
/* "Address"; only JMP. Zero operands allowed unless GNU syntax. */
mmix_operands_jmp,
/* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an
integer. */
mmix_operands_pushgo,
/* Two registers or a register and a byte, like FLOT, possibly with
rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */
mmix_operands_roundregs_z,
/* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */
mmix_operands_pop,
/* Two registers, possibly with rounding: "$X,$Z" or
"$X,ROUND_MODE,$Z". */
mmix_operands_roundregs,
/* "XYZ", like SYNC. */
mmix_operands_sync,
/* "X,$Y,$Z|Z", like SYNCD. */
mmix_operands_x_regs_z,
/* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */
mmix_operands_neg,
/* "$X,Address, like GETA or branches. */
mmix_operands_regaddr,
/* "$X|X,Address, like PUSHJ. */
mmix_operands_pushj,
/* "$X,spec_reg"; GET. */
mmix_operands_get,
/* "spec_reg,$Z|Z"; PUT. */
mmix_operands_put,
/* Two registers, "$X,$Y". */
mmix_operands_set,
/* "$X,0"; SAVE. */
mmix_operands_save,
/* "0,$Z"; UNSAVE. */
mmix_operands_unsave,
/* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three
operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */
mmix_operands_xyz_opt,
/* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted
and will then be assumed zero. */
mmix_operands_resume,
/* These are specials to handle that pseudo-directives are specified
like ordinary insns when being mmixal-compatible. They signify the
specific pseudo-directive rather than the operands type. */
/* LOC. */
mmix_operands_loc,
/* PREFIX. */
mmix_operands_prefix,
/* BYTE. */
mmix_operands_byte,
/* WYDE. */
mmix_operands_wyde,
/* TETRA. */
mmix_operands_tetra,
/* OCTA. */
mmix_operands_octa,
/* LOCAL. */
mmix_operands_local,
/* BSPEC. */
mmix_operands_bspec,
/* ESPEC. */
mmix_operands_espec,
};
struct mmix_opcode
{
const char *name;
unsigned long match;
unsigned long lose;
enum mmix_operands_type operands;
/* This is used by the disassembly function. */
enum mmix_insn_type type;
};
/* Declare the actual tables. */
extern const struct mmix_opcode mmix_opcodes[];
/* This one is terminated with an entry with a NULL name. */
extern const struct mmix_spec_reg mmix_spec_regs[];
/* Some insn values we use when padding and synthesizing address loads. */
#define IMM_OFFSET_BIT 1
#define COND_INV_BIT 0x8
#define PRED_INV_BIT 0x10
#define PUSHGO_INSN_BYTE 0xbe
#define GO_INSN_BYTE 0x9e
#define SETL_INSN_BYTE 0xe3
#define INCML_INSN_BYTE 0xe6
#define INCMH_INSN_BYTE 0xe5
#define INCH_INSN_BYTE 0xe4
#define SWYM_INSN_BYTE 0xfd
#define JMP_INSN_BYTE 0xf0
/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable)
global registers. */
#define MAX_GREGS 223

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/* mn10200.h -- Header file for Matsushita 10200 opcode table
Copyright 1996, 1997, 2010 Free Software Foundation, Inc.
Written by Jeff Law, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef MN10200_H
#define MN10200_H
/* The opcode table is an array of struct mn10200_opcode. */
struct mn10200_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned long opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned long mask;
/* The format of this opcode. */
unsigned char format;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct mn10200_opcode mn10200_opcodes[];
extern const int mn10200_num_opcodes;
/* The operands table is an array of struct mn10200_operand. */
struct mn10200_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* One bit syntax flags. */
int flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the mn10200_opcodes table. */
extern const struct mn10200_operand mn10200_operands[];
/* Values defined for the flags field of a struct mn10200_operand. */
#define MN10200_OPERAND_DREG 0x1
#define MN10200_OPERAND_AREG 0x2
#define MN10200_OPERAND_PSW 0x4
#define MN10200_OPERAND_MDR 0x8
#define MN10200_OPERAND_SIGNED 0x10
#define MN10200_OPERAND_PROMOTE 0x20
#define MN10200_OPERAND_PAREN 0x40
#define MN10200_OPERAND_REPEATED 0x80
#define MN10200_OPERAND_EXTENDED 0x100
#define MN10200_OPERAND_NOCHECK 0x200
#define MN10200_OPERAND_PCREL 0x400
#define MN10200_OPERAND_MEMADDR 0x800
#define MN10200_OPERAND_RELAX 0x1000
#define FMT_1 1
#define FMT_2 2
#define FMT_3 3
#define FMT_4 4
#define FMT_5 5
#define FMT_6 6
#define FMT_7 7
#endif /* MN10200_H */

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/* mn10300.h -- Header file for Matsushita 10300 opcode table
Copyright 1996, 1997, 1998, 1999, 2003, 2010 Free Software Foundation, Inc.
Written by Jeff Law, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef MN10300_H
#define MN10300_H
/* The opcode table is an array of struct mn10300_opcode. */
#define MN10300_MAX_OPERANDS 8
struct mn10300_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned long opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned long mask;
/* A bitmask. For each operand, nonzero if it must not have the same
register specification as all other operands with a nonzero bit in
this flag. ie 0x81 would indicate that operands 7 and 0 must not
match. Note that we count operands from left to right as they appear
in the operands specification below. */
unsigned int no_match_operands;
/* The format of this opcode. */
unsigned char format;
/* Bitmask indicating what cpu variants this opcode is available on.
We assume mn10300 base opcodes are available everywhere, so we only
have to note opcodes which are available on other variants. */
unsigned int machine;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[MN10300_MAX_OPERANDS];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct mn10300_opcode mn10300_opcodes[];
extern const int mn10300_num_opcodes;
/* The operands table is an array of struct mn10300_operand. */
struct mn10300_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* One bit syntax flags. */
int flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the mn10300_opcodes table. */
extern const struct mn10300_operand mn10300_operands[];
/* Values defined for the flags field of a struct mn10300_operand. */
#define MN10300_OPERAND_DREG 0x1
#define MN10300_OPERAND_AREG 0x2
#define MN10300_OPERAND_SP 0x4
#define MN10300_OPERAND_PSW 0x8
#define MN10300_OPERAND_MDR 0x10
#define MN10300_OPERAND_SIGNED 0x20
#define MN10300_OPERAND_PROMOTE 0x40
#define MN10300_OPERAND_PAREN 0x80
#define MN10300_OPERAND_REPEATED 0x100
#define MN10300_OPERAND_EXTENDED 0x200
#define MN10300_OPERAND_SPLIT 0x400
#define MN10300_OPERAND_REG_LIST 0x800
#define MN10300_OPERAND_PCREL 0x1000
#define MN10300_OPERAND_MEMADDR 0x2000
#define MN10300_OPERAND_RELAX 0x4000
#define MN10300_OPERAND_USP 0x8000
#define MN10300_OPERAND_SSP 0x10000
#define MN10300_OPERAND_MSP 0x20000
#define MN10300_OPERAND_PC 0x40000
#define MN10300_OPERAND_EPSW 0x80000
#define MN10300_OPERAND_RREG 0x100000
#define MN10300_OPERAND_XRREG 0x200000
#define MN10300_OPERAND_PLUS 0x400000
#define MN10300_OPERAND_24BIT 0x800000
#define MN10300_OPERAND_FSREG 0x1000000
#define MN10300_OPERAND_FDREG 0x2000000
#define MN10300_OPERAND_FPCR 0x4000000
/* Opcode Formats. */
#define FMT_S0 1
#define FMT_S1 2
#define FMT_S2 3
#define FMT_S4 4
#define FMT_S6 5
#define FMT_D0 6
#define FMT_D1 7
#define FMT_D2 8
#define FMT_D4 9
#define FMT_D5 10
#define FMT_D6 11
#define FMT_D7 12
#define FMT_D8 13
#define FMT_D9 14
#define FMT_D10 15
#define FMT_D3 16
/* Variants of the mn10300 which have additional opcodes. */
#define MN103 300
#define AM30 300
#define AM33 330
#define AM33_2 332
#endif /* MN10300_H */

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/* Definitions for decoding the moxie opcode table.
Copyright 2009 Free Software Foundation, Inc.
Contributed by Anthony Green (green@moxielogic.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* Form 1 instructions come in different flavors:
Some have no arguments (MOXIE_F1_NARG)
Some only use the A operand (MOXIE_F1_A)
Some use A and B registers (MOXIE_F1_AB)
Some use A and consume a 4 byte immediate value (MOXIE_F1_A4)
Some use just a 4 byte immediate value (MOXIE_F1_4)
Some use just a 4 byte memory address (MOXIE_F1_M)
Some use B and an indirect A (MOXIE_F1_AiB)
Some use A and an indirect B (MOXIE_F1_ABi)
Some consume a 4 byte immediate value and use X (MOXIE_F1_4A)
Some use B and an indirect A plus 4 bytes (MOXIE_F1_AiB4)
Some use A and an indirect B plus 4 bytes (MOXIE_F1_ABi4)
Form 2 instructions also come in different flavors:
Some have no arguments (MOXIE_F2_NARG)
Some use the A register and an 8-bit value (MOXIE_F2_A8V)
Form 3 instructions also come in different flavors:
Some have no arguments (MOXIE_F3_NARG)
Some have a 10-bit PC relative operand (MOXIE_F3_PCREL). */
#define MOXIE_F1_NARG 0x100
#define MOXIE_F1_A 0x101
#define MOXIE_F1_AB 0x102
/* #define MOXIE_F1_ABC 0x103 */
#define MOXIE_F1_A4 0x104
#define MOXIE_F1_4 0x105
#define MOXIE_F1_AiB 0x106
#define MOXIE_F1_ABi 0x107
#define MOXIE_F1_4A 0x108
#define MOXIE_F1_AiB4 0x109
#define MOXIE_F1_ABi4 0x10a
#define MOXIE_F1_M 0x10b
#define MOXIE_F2_NARG 0x200
#define MOXIE_F2_A8V 0x201
#define MOXIE_F3_NARG 0x300
#define MOXIE_F3_PCREL 0x301
#define MOXIE_BAD 0x400
typedef struct moxie_opc_info_t
{
short opcode;
unsigned itype;
const char * name;
} moxie_opc_info_t;
extern const moxie_opc_info_t moxie_form1_opc_info[128];
extern const moxie_opc_info_t moxie_form2_opc_info[4];
extern const moxie_opc_info_t moxie_form3_opc_info[16];

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/* Opcode decoder for the TI MSP430
Copyright 2012-2013 Free Software Foundation, Inc.
Written by DJ Delorie <dj@redhat.com>
This file is part of GDB, the GNU Debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
typedef enum
{
MSO_unknown,
/* Double-operand instructions - all repeat .REPEATS times. */
MSO_mov, /* dest = src */
MSO_add, /* dest += src */
MSO_addc, /* dest += src + carry */
MSO_subc, /* dest -= (src-1) + carry */
MSO_sub, /* dest -= src */
MSO_cmp, /* dest - src -> status */
MSO_dadd, /* dest += src (as BCD) */
MSO_bit, /* dest & src -> status */
MSO_bic, /* dest &= ~src (bit clear) */
MSO_bis, /* dest |= src (bit set, OR) */
MSO_xor, /* dest ^= src */
MSO_and, /* dest &= src */
/* Single-operand instructions. */
MSO_rrc, /* Rotate through carry, dest >>= .REPEATS. */
MSO_swpb, /* Swap lower bytes of operand. */
MSO_rra, /* Signed shift dest >>= .REPEATS. */
MSO_sxt, /* Sign extend lower byte. */
MSO_push, /* Push .REPEATS registers (or other op) starting at SRC going towards R0. */
MSO_pop, /* Pop .REPEATS registers starting at DEST going towards R15. */
MSO_call,
MSO_reti,
/* Jumps. */
MSO_jmp, /* PC = SRC if .COND true. */
/* Extended single-operand instructions. */
MSO_rru, /* Unsigned shift right, dest >>= .REPEATS. */
} MSP430_Opcode_ID;
typedef enum
{
MSP430_Operand_None,
MSP430_Operand_Immediate,
MSP430_Operand_Register,
MSP430_Operand_Indirect,
MSP430_Operand_Indirect_Postinc
} MSP430_Operand_Type;
typedef enum
{
MSR_0 = 0,
MSR_PC = 0,
MSR_SP = 1,
MSR_SR = 2,
MSR_CG = 3,
MSR_None = 16,
} MSP430_Register;
typedef struct
{
MSP430_Operand_Type type;
int addend;
MSP430_Register reg : 8;
MSP430_Register reg2 : 8;
unsigned char bit_number : 4;
unsigned char condition : 3;
} MSP430_Opcode_Operand;
typedef enum
{
MSP430_Byte = 0,
MSP430_Word,
MSP430_Addr
} MSP430_Size;
/* These numerically match the bit encoding. */
typedef enum
{
MSC_nz = 0,
MSC_z,
MSC_nc,
MSC_c,
MSC_n,
MSC_ge,
MSC_l,
MSC_true,
} MSP430_Condition;
#define MSP430_FLAG_C 0x01
#define MSP430_FLAG_Z 0x02
#define MSP430_FLAG_N 0x04
#define MSP430_FLAG_V 0x80
typedef struct
{
int lineno;
MSP430_Opcode_ID id;
unsigned flags_1:8; /* These flags are set to '1' by the insn. */
unsigned flags_0:8; /* These flags are set to '0' by the insn. */
unsigned flags_set:8; /* These flags are set appropriately by the insn. */
unsigned zc:1; /* If set, pretend the carry bit is zero. */
unsigned repeat_reg:1; /* If set, count is in REG[repeats]. */
unsigned ofs_430x:1; /* If set, the offset in any operand is 430x (else use 430 compatibility mode). */
unsigned repeats:5; /* Contains COUNT-1, or register number. */
int n_bytes; /* Opcode size in BYTES. */
char * syntax;
MSP430_Size size; /* Operand size in BITS. */
MSP430_Condition cond;
/* By convention, these are [0]destination, [1]source. */
MSP430_Opcode_Operand op[2];
} MSP430_Opcode_Decoded;
int msp430_decode_opcode (unsigned long, MSP430_Opcode_Decoded *, int (*)(void *), void *);

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/* Opcode table for the TI MSP430 microcontrollers
Copyright 2002-2013 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef __MSP430_H_
#define __MSP430_H_
struct msp430_operand_s
{
int ol; /* Operand length words. */
int am; /* Addr mode. */
int reg; /* Register. */
int mode; /* Pperand mode. */
#define OP_REG 0
#define OP_EXP 1
#ifndef DASM_SECTION
expressionS exp;
#endif
};
#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
struct msp430_opcode_s
{
char *name;
int fmt;
int insn_opnumb;
int bin_opcode;
int bin_mask;
};
#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
static struct msp430_opcode_s msp430_opcodes[] =
{
MSP_INSN (and, 1, 2, 0xf000, 0xf000),
MSP_INSN (inv, 0, 1, 0xe330, 0xfff0),
MSP_INSN (xor, 1, 2, 0xe000, 0xf000),
MSP_INSN (setz, 0, 0, 0xd322, 0xffff),
MSP_INSN (setc, 0, 0, 0xd312, 0xffff),
MSP_INSN (eint, 0, 0, 0xd232, 0xffff),
MSP_INSN (setn, 0, 0, 0xd222, 0xffff),
MSP_INSN (bis, 1, 2, 0xd000, 0xf000),
MSP_INSN (clrz, 0, 0, 0xc322, 0xffff),
MSP_INSN (clrc, 0, 0, 0xc312, 0xffff),
MSP_INSN (dint, 0, 0, 0xc232, 0xffff),
MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
MSP_INSN (bic, 1, 2, 0xc000, 0xf000),
MSP_INSN (bit, 1, 2, 0xb000, 0xf000),
MSP_INSN (dadc, 0, 1, 0xa300, 0xff30),
MSP_INSN (dadd, 1, 2, 0xa000, 0xf000),
MSP_INSN (tst, 0, 1, 0x9300, 0xff30),
MSP_INSN (cmp, 1, 2, 0x9000, 0xf000),
MSP_INSN (decd, 0, 1, 0x8320, 0xff30),
MSP_INSN (dec, 0, 1, 0x8310, 0xff30),
MSP_INSN (sub, 1, 2, 0x8000, 0xf000),
MSP_INSN (sbc, 0, 1, 0x7300, 0xff30),
MSP_INSN (subc, 1, 2, 0x7000, 0xf000),
MSP_INSN (adc, 0, 1, 0x6300, 0xff30),
MSP_INSN (rlc, 0, 2, 0x6000, 0xf000),
MSP_INSN (addc, 1, 2, 0x6000, 0xf000),
MSP_INSN (incd, 0, 1, 0x5320, 0xff30),
MSP_INSN (inc, 0, 1, 0x5310, 0xff30),
MSP_INSN (rla, 0, 2, 0x5000, 0xf000),
MSP_INSN (add, 1, 2, 0x5000, 0xf000),
MSP_INSN (nop, 0, 0, 0x4303, 0xffff),
MSP_INSN (clr, 0, 1, 0x4300, 0xff30),
MSP_INSN (ret, 0, 0, 0x4130, 0xff30),
MSP_INSN (pop, 0, 1, 0x4130, 0xff30),
MSP_INSN (br, 0, 3, 0x4000, 0xf000),
MSP_INSN (mov, 1, 2, 0x4000, 0xf000),
MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00),
MSP_INSN (jl, 3, 1, 0x3800, 0xfc00),
MSP_INSN (jge, 3, 1, 0x3400, 0xfc00),
MSP_INSN (jn, 3, 1, 0x3000, 0xfc00),
MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00),
MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00),
MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00),
MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00),
MSP_INSN (jz, 3, 1, 0x2400, 0xfc00),
MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00),
MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00),
MSP_INSN (jne, 3, 1, 0x2000, 0xfc00),
MSP_INSN (reti, 2, 0, 0x1300, 0xffc0),
MSP_INSN (call, 2, 1, 0x1280, 0xffc0),
MSP_INSN (push, 2, 1, 0x1200, 0xff80),
MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0),
MSP_INSN (rra, 2, 1, 0x1100, 0xff80),
MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0),
MSP_INSN (rrc, 2, 1, 0x1000, 0xff80),
/* Simple polymorphs. */
MSP_INSN (beq, 4, 0, 0, 0xffff),
MSP_INSN (bne, 4, 1, 0, 0xffff),
MSP_INSN (blt, 4, 2, 0, 0xffff),
MSP_INSN (bltu, 4, 3, 0, 0xffff),
MSP_INSN (bge, 4, 4, 0, 0xffff),
MSP_INSN (bgeu, 4, 5, 0, 0xffff),
MSP_INSN (bltn, 4, 6, 0, 0xffff),
MSP_INSN (jump, 4, 7, 0, 0xffff),
/* Long polymorphs. */
MSP_INSN (bgt, 5, 0, 0, 0xffff),
MSP_INSN (bgtu, 5, 1, 0, 0xffff),
MSP_INSN (bleu, 5, 2, 0, 0xffff),
MSP_INSN (ble, 5, 3, 0, 0xffff),
/* MSP430X instructions - these ones use an extension word.
A negative format indicates an MSP430X instruction. */
MSP_INSN (addcx, -2, 2, 0x6000, 0xf000),
MSP_INSN (addx, -2, 2, 0x5000, 0xf000),
MSP_INSN (andx, -2, 2, 0xf000, 0xf000),
MSP_INSN (bicx, -2, 2, 0xc000, 0xf000),
MSP_INSN (bisx, -2, 2, 0xd000, 0xf000),
MSP_INSN (bitx, -2, 2, 0xb000, 0xf000),
MSP_INSN (cmpx, -2, 2, 0x9000, 0xf000),
MSP_INSN (daddx, -2, 2, 0xa000, 0xf000),
MSP_INSN (movx, -2, 2, 0x4000, 0xf000),
MSP_INSN (subcx, -2, 2, 0x7000, 0xf000),
MSP_INSN (subx, -2, 2, 0x8000, 0xf000),
MSP_INSN (xorx, -2, 2, 0xe000, 0xf000),
/* MSP430X Synthetic instructions. */
MSP_INSN (adcx, -1, 1, 0x6300, 0xff30),
MSP_INSN (clra, -1, 1, 0x4300, 0xff30),
MSP_INSN (clrx, -1, 1, 0x4300, 0xff30),
MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30),
MSP_INSN (decx, -1, 1, 0x8310, 0xff30),
MSP_INSN (decda, -1, 1, 0x8320, 0xff30),
MSP_INSN (decdx, -1, 1, 0x8320, 0xff30),
MSP_INSN (incx, -1, 1, 0x5310, 0xff30),
MSP_INSN (incda, -1, 1, 0x5320, 0xff30),
MSP_INSN (incdx, -1, 1, 0x5320, 0xff30),
MSP_INSN (invx, -1, 1, 0xe330, 0xfff0),
MSP_INSN (popx, -1, 1, 0x4130, 0xff30),
MSP_INSN (rlax, -1, 2, 0x5000, 0xf000),
MSP_INSN (rlcx, -1, 2, 0x6000, 0xf000),
MSP_INSN (sbcx, -1, 1, 0x7300, 0xff30),
MSP_INSN (tsta, -1, 1, 0x9300, 0xff30),
MSP_INSN (tstx, -1, 1, 0x9300, 0xff30),
MSP_INSN (pushx, -3, 1, 0x1200, 0xff80),
MSP_INSN (rrax, -3, 1, 0x1100, 0xff80),
MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80),
MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0),
MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0),
/* MSP430X Address instructions - no extension word needed.
The insn_opnumb field is used to encode the nature of the
instruction for assembly and disassembly purposes. */
MSP_INSN (calla, -1, 4, 0x1300, 0xff00),
MSP_INSN (popm, -1, 5, 0x1600, 0xfe00),
MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00),
MSP_INSN (rrcm, -1, 6, 0x0040, 0xf3e0),
MSP_INSN (rram, -1, 6, 0x0140, 0xf3e0),
MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0),
MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0),
MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */
MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0),
MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0),
MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0),
MSP_INSN (reta, -1, 9, 0x0110, 0xffff),
MSP_INSN (bra, -1, 9, 0x0000, 0xf0cf),
MSP_INSN (mova, -1, 9, 0x0000, 0xf080),
MSP_INSN (mova, -1, 9, 0x0080, 0xf0b0),
MSP_INSN (mova, -1, 9, 0x00c0, 0xf0f0),
/* Pseudo instruction to set the repeat field in the extension word. */
MSP_INSN (rpt, -1, 10, 0x0000, 0x0000),
/* End of instruction set. */
{ NULL, 0, 0, 0, 0 }
};
#endif

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/* Nios II opcode list for GAS, the GNU assembler.
Copyright (C) 2012, 2013 Free Software Foundation, Inc.
Contributed by Nigel Gray (ngray@altera.com).
Contributed by Mentor Graphics, Inc.
This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifndef _NIOS2_H_
#define _NIOS2_H_
#include "bfd.h"
/****************************************************************************
* This file contains structures, bit masks and shift counts used
* by the GNU toolchain to define the Nios II instruction set and
* access various opcode fields.
****************************************************************************/
/* Identify different overflow situations for error messages. */
enum overflow_type
{
call_target_overflow = 0,
branch_target_overflow,
address_offset_overflow,
signed_immed16_overflow,
unsigned_immed16_overflow,
unsigned_immed5_overflow,
custom_opcode_overflow,
no_overflow
};
/* This structure holds information for a particular instruction.
The args field is a string describing the operands. The following
letters can appear in the args:
c - a 5-bit control register index
d - a 5-bit destination register index
s - a 5-bit left source register index
t - a 5-bit right source register index
i - a 16-bit signed immediate
u - a 16-bit unsigned immediate
o - a 16-bit signed program counter relative offset
j - a 5-bit unsigned immediate
b - a 5-bit break instruction constant
l - a 8-bit custom instruction constant
m - a 26-bit unsigned immediate
Literal ',', '(', and ')' characters may also appear in the args as
delimiters.
The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection
of bits describing the instruction, notably any relevant hazard
information.
When assembling, the match field contains the opcode template, which
is modified by the arguments to produce the actual opcode
that is emitted. If pinfo is INSN_MACRO, then this is 0.
If pinfo is INSN_MACRO, the mask field stores the macro identifier.
Otherwise this is a bit mask for the relevant portions of the opcode
when disassembling. If the actual opcode anded with the match field
equals the opcode field, then we have found the correct instruction. */
struct nios2_opcode
{
const char *name; /* The name of the instruction. */
const char *args; /* A string describing the arguments for this
instruction. */
const char *args_test; /* Like args, but with an extra argument for
the expected opcode. */
unsigned long num_args; /* The number of arguments the instruction
takes. */
unsigned long match; /* The basic opcode for the instruction. */
unsigned long mask; /* Mask for the opcode field of the
instruction. */
unsigned long pinfo; /* Is this a real instruction or instruction
macro? */
enum overflow_type overflow_msg; /* Used to generate informative
message when fixup overflows. */
};
/* This value is used in the nios2_opcode.pinfo field to indicate that the
instruction is a macro or pseudo-op. This requires special treatment by
the assembler, and is used by the disassembler to determine whether to
check for a nop. */
#define NIOS2_INSN_MACRO 0x80000000
#define NIOS2_INSN_MACRO_MOV 0x80000001
#define NIOS2_INSN_MACRO_MOVI 0x80000002
#define NIOS2_INSN_MACRO_MOVIA 0x80000004
#define NIOS2_INSN_RELAXABLE 0x40000000
#define NIOS2_INSN_UBRANCH 0x00000010
#define NIOS2_INSN_CBRANCH 0x00000020
#define NIOS2_INSN_CALL 0x00000040
#define NIOS2_INSN_ADDI 0x00000080
#define NIOS2_INSN_ANDI 0x00000100
#define NIOS2_INSN_ORI 0x00000200
#define NIOS2_INSN_XORI 0x00000400
/* Associates a register name ($6) with a 5-bit index (eg 6). */
struct nios2_reg
{
const char *name;
const int index;
};
/* These are bit masks and shift counts for accessing the various
fields of a Nios II instruction. */
/* Macros for getting and setting an instruction field. */
#define GET_INSN_FIELD(X, i) \
(((i) & OP_MASK_##X) >> OP_SH_##X)
#define SET_INSN_FIELD(X, i, j) \
((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X)))
/* Instruction field definitions. */
#define IW_A_LSB 27
#define IW_A_MSB 31
#define IW_A_SZ 5
#define IW_A_MASK 0x1f
#define IW_B_LSB 22
#define IW_B_MSB 26
#define IW_B_SZ 5
#define IW_B_MASK 0x1f
#define IW_C_LSB 17
#define IW_C_MSB 21
#define IW_C_SZ 5
#define IW_C_MASK 0x1f
#define IW_IMM16_LSB 6
#define IW_IMM16_MSB 21
#define IW_IMM16_SZ 16
#define IW_IMM16_MASK 0xffff
#define IW_IMM26_LSB 6
#define IW_IMM26_MSB 31
#define IW_IMM26_SZ 26
#define IW_IMM26_MASK 0x3ffffff
#define IW_OP_LSB 0
#define IW_OP_MSB 5
#define IW_OP_SZ 6
#define IW_OP_MASK 0x3f
#define IW_OPX_LSB 11
#define IW_OPX_MSB 16
#define IW_OPX_SZ 6
#define IW_OPX_MASK 0x3f
#define IW_SHIFT_IMM5_LSB 6
#define IW_SHIFT_IMM5_MSB 10
#define IW_SHIFT_IMM5_SZ 5
#define IW_SHIFT_IMM5_MASK 0x1f
#define IW_CONTROL_REGNUM_LSB 6
#define IW_CONTROL_REGNUM_MSB 9
#define IW_CONTROL_REGNUM_SZ 4
#define IW_CONTROL_REGNUM_MASK 0xf
/* Operator mask and shift. */
#define OP_MASK_OP (IW_OP_MASK << IW_OP_LSB)
#define OP_SH_OP IW_OP_LSB
/* Masks and shifts for I-type instructions. */
#define OP_MASK_IOP (IW_OP_MASK << IW_OP_LSB)
#define OP_SH_IOP IW_OP_LSB
#define OP_MASK_IMM16 (IW_IMM16_MASK << IW_IMM16_LSB)
#define OP_SH_IMM16 IW_IMM16_LSB
#define OP_MASK_IRD (IW_B_MASK << IW_B_LSB)
#define OP_SH_IRD IW_B_LSB /* The same as T for I-type. */
#define OP_MASK_IRT (IW_B_MASK << IW_B_LSB)
#define OP_SH_IRT IW_B_LSB
#define OP_MASK_IRS (IW_A_MASK << IW_A_LSB)
#define OP_SH_IRS IW_A_LSB
/* Masks and shifts for R-type instructions. */
#define OP_MASK_ROP (IW_OP_MASK << IW_OP_LSB)
#define OP_SH_ROP IW_OP_LSB
#define OP_MASK_ROPX (IW_OPX_MASK << IW_OPX_LSB)
#define OP_SH_ROPX IW_OPX_LSB
#define OP_MASK_RRD (IW_C_MASK << IW_C_LSB)
#define OP_SH_RRD IW_C_LSB
#define OP_MASK_RRT (IW_B_MASK << IW_B_LSB)
#define OP_SH_RRT IW_B_LSB
#define OP_MASK_RRS (IW_A_MASK << IW_A_LSB)
#define OP_SH_RRS IW_A_LSB
/* Masks and shifts for J-type instructions. */
#define OP_MASK_JOP (IW_OP_MASK << IW_OP_LSB)
#define OP_SH_JOP IW_OP_LSB
#define OP_MASK_IMM26 (IW_IMM26_MASK << IW_IMM26_LSB)
#define OP_SH_IMM26 IW_IMM26_LSB
/* Masks and shifts for CTL instructions. */
#define OP_MASK_RCTL 0x000007c0
#define OP_SH_RCTL 6
/* Break instruction imm5 field. */
#define OP_MASK_TRAP_IMM5 0x000007c0
#define OP_SH_TRAP_IMM5 6
/* Instruction imm5 field. */
#define OP_MASK_IMM5 (IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB)
#define OP_SH_IMM5 IW_SHIFT_IMM5_LSB
/* Cache operation fields (type j,i(s)). */
#define OP_MASK_CACHE_OPX (IW_B_MASK << IW_B_LSB)
#define OP_SH_CACHE_OPX IW_B_LSB
#define OP_MASK_CACHE_RRS (IW_A_MASK << IW_A_LSB)
#define OP_SH_CACHE_RRS IW_A_LSB
/* Custom instruction masks. */
#define OP_MASK_CUSTOM_A 0x00010000
#define OP_SH_CUSTOM_A 16
#define OP_MASK_CUSTOM_B 0x00008000
#define OP_SH_CUSTOM_B 15
#define OP_MASK_CUSTOM_C 0x00004000
#define OP_SH_CUSTOM_C 14
#define OP_MASK_CUSTOM_N 0x00003fc0
#define OP_SH_CUSTOM_N 6
#define OP_MAX_CUSTOM_N 255
/* OP instruction values. */
#define OP_ADDI 4
#define OP_ANDHI 44
#define OP_ANDI 12
#define OP_BEQ 38
#define OP_BGE 14
#define OP_BGEU 46
#define OP_BLT 22
#define OP_BLTU 54
#define OP_BNE 30
#define OP_BR 6
#define OP_CALL 0
#define OP_CMPEQI 32
#define OP_CMPGEI 8
#define OP_CMPGEUI 40
#define OP_CMPLTI 16
#define OP_CMPLTUI 48
#define OP_CMPNEI 24
#define OP_CUSTOM 50
#define OP_FLUSHD 59
#define OP_FLUSHDA 27
#define OP_INITD 51
#define OP_INITDA 19
#define OP_JMPI 1
#define OP_LDB 7
#define OP_LDBIO 39
#define OP_LDBU 3
#define OP_LDBUIO 35
#define OP_LDH 15
#define OP_LDHIO 47
#define OP_LDHU 11
#define OP_LDHUIO 43
#define OP_LDL 31
#define OP_LDW 23
#define OP_LDWIO 55
#define OP_MULI 36
#define OP_OPX 58
#define OP_ORHI 52
#define OP_ORI 20
#define OP_RDPRS 56
#define OP_STB 5
#define OP_STBIO 37
#define OP_STC 29
#define OP_STH 13
#define OP_STHIO 45
#define OP_STW 21
#define OP_STWIO 53
#define OP_XORHI 60
#define OP_XORI 28
/* OPX instruction values. */
#define OPX_ADD 49
#define OPX_AND 14
#define OPX_BREAK 52
#define OPX_BRET 9
#define OPX_CALLR 29
#define OPX_CMPEQ 32
#define OPX_CMPGE 8
#define OPX_CMPGEU 40
#define OPX_CMPLT 16
#define OPX_CMPLTU 48
#define OPX_CMPNE 24
#define OPX_CRST 62
#define OPX_DIV 37
#define OPX_DIVU 36
#define OPX_ERET 1
#define OPX_FLUSHI 12
#define OPX_FLUSHP 4
#define OPX_HBREAK 53
#define OPX_INITI 41
#define OPX_INTR 61
#define OPX_JMP 13
#define OPX_MUL 39
#define OPX_MULXSS 31
#define OPX_MULXSU 23
#define OPX_MULXUU 7
#define OPX_NEXTPC 28
#define OPX_NOR 6
#define OPX_OR 22
#define OPX_RDCTL 38
#define OPX_RET 5
#define OPX_ROL 3
#define OPX_ROLI 2
#define OPX_ROR 11
#define OPX_SLL 19
#define OPX_SLLI 18
#define OPX_SRA 59
#define OPX_SRAI 58
#define OPX_SRL 27
#define OPX_SRLI 26
#define OPX_SUB 57
#define OPX_SYNC 54
#define OPX_TRAP 45
#define OPX_WRCTL 46
#define OPX_WRPRS 20
#define OPX_XOR 30
/* The following macros define the opcode matches for each
instruction code & OP_MASK_INST == OP_MATCH_INST. */
/* OP instruction matches. */
#define OP_MATCH_ADDI OP_ADDI
#define OP_MATCH_ANDHI OP_ANDHI
#define OP_MATCH_ANDI OP_ANDI
#define OP_MATCH_BEQ OP_BEQ
#define OP_MATCH_BGE OP_BGE
#define OP_MATCH_BGEU OP_BGEU
#define OP_MATCH_BLT OP_BLT
#define OP_MATCH_BLTU OP_BLTU
#define OP_MATCH_BNE OP_BNE
#define OP_MATCH_BR OP_BR
#define OP_MATCH_FLUSHD OP_FLUSHD
#define OP_MATCH_FLUSHDA OP_FLUSHDA
#define OP_MATCH_INITD OP_INITD
#define OP_MATCH_INITDA OP_INITDA
#define OP_MATCH_CALL OP_CALL
#define OP_MATCH_CMPEQI OP_CMPEQI
#define OP_MATCH_CMPGEI OP_CMPGEI
#define OP_MATCH_CMPGEUI OP_CMPGEUI
#define OP_MATCH_CMPLTI OP_CMPLTI
#define OP_MATCH_CMPLTUI OP_CMPLTUI
#define OP_MATCH_CMPNEI OP_CMPNEI
#define OP_MATCH_JMPI OP_JMPI
#define OP_MATCH_LDB OP_LDB
#define OP_MATCH_LDBIO OP_LDBIO
#define OP_MATCH_LDBU OP_LDBU
#define OP_MATCH_LDBUIO OP_LDBUIO
#define OP_MATCH_LDH OP_LDH
#define OP_MATCH_LDHIO OP_LDHIO
#define OP_MATCH_LDHU OP_LDHU
#define OP_MATCH_LDHUIO OP_LDHUIO
#define OP_MATCH_LDL OP_LDL
#define OP_MATCH_LDW OP_LDW
#define OP_MATCH_LDWIO OP_LDWIO
#define OP_MATCH_MULI OP_MULI
#define OP_MATCH_OPX OP_OPX
#define OP_MATCH_ORHI OP_ORHI
#define OP_MATCH_ORI OP_ORI
#define OP_MATCH_RDPRS OP_RDPRS
#define OP_MATCH_STB OP_STB
#define OP_MATCH_STBIO OP_STBIO
#define OP_MATCH_STC OP_STC
#define OP_MATCH_STH OP_STH
#define OP_MATCH_STHIO OP_STHIO
#define OP_MATCH_STW OP_STW
#define OP_MATCH_STWIO OP_STWIO
#define OP_MATCH_CUSTOM OP_CUSTOM
#define OP_MATCH_XORHI OP_XORHI
#define OP_MATCH_XORI OP_XORI
#define OP_MATCH_OPX OP_OPX
/* OPX instruction values. */
#define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX)
#define OP_MATCH_ADD OPX_MATCH (OPX_ADD)
#define OP_MATCH_AND OPX_MATCH (OPX_AND)
#define OP_MATCH_BREAK ((0x1e << 17) | OPX_MATCH (OPX_BREAK))
#define OP_MATCH_BRET (0xf0000000 | OPX_MATCH (OPX_BRET))
#define OP_MATCH_CALLR ((0x1f << 17) | OPX_MATCH (OPX_CALLR))
#define OP_MATCH_CMPEQ OPX_MATCH (OPX_CMPEQ)
#define OP_MATCH_CMPGE OPX_MATCH (OPX_CMPGE)
#define OP_MATCH_CMPGEU OPX_MATCH (OPX_CMPGEU)
#define OP_MATCH_CMPLT OPX_MATCH (OPX_CMPLT)
#define OP_MATCH_CMPLTU OPX_MATCH (OPX_CMPLTU)
#define OP_MATCH_CMPNE OPX_MATCH (OPX_CMPNE)
#define OP_MATCH_DIV OPX_MATCH (OPX_DIV)
#define OP_MATCH_DIVU OPX_MATCH (OPX_DIVU)
#define OP_MATCH_JMP OPX_MATCH (OPX_JMP)
#define OP_MATCH_MUL OPX_MATCH (OPX_MUL)
#define OP_MATCH_MULXSS OPX_MATCH (OPX_MULXSS)
#define OP_MATCH_MULXSU OPX_MATCH (OPX_MULXSU)
#define OP_MATCH_MULXUU OPX_MATCH (OPX_MULXUU)
#define OP_MATCH_NEXTPC OPX_MATCH (OPX_NEXTPC)
#define OP_MATCH_NOR OPX_MATCH (OPX_NOR)
#define OP_MATCH_OR OPX_MATCH (OPX_OR)
#define OP_MATCH_RDCTL OPX_MATCH (OPX_RDCTL)
#define OP_MATCH_RET (0xf8000000 | OPX_MATCH (OPX_RET))
#define OP_MATCH_ROL OPX_MATCH (OPX_ROL)
#define OP_MATCH_ROLI OPX_MATCH (OPX_ROLI)
#define OP_MATCH_ROR OPX_MATCH (OPX_ROR)
#define OP_MATCH_SLL OPX_MATCH (OPX_SLL)
#define OP_MATCH_SLLI OPX_MATCH (OPX_SLLI)
#define OP_MATCH_SRA OPX_MATCH (OPX_SRA)
#define OP_MATCH_SRAI OPX_MATCH (OPX_SRAI)
#define OP_MATCH_SRL OPX_MATCH (OPX_SRL)
#define OP_MATCH_SRLI OPX_MATCH (OPX_SRLI)
#define OP_MATCH_SUB OPX_MATCH (OPX_SUB)
#define OP_MATCH_SYNC OPX_MATCH (OPX_SYNC)
#define OP_MATCH_TRAP ((0x1d << 17) | OPX_MATCH (OPX_TRAP))
#define OP_MATCH_ERET (0xef800000 | OPX_MATCH (OPX_ERET))
#define OP_MATCH_WRCTL OPX_MATCH (OPX_WRCTL)
#define OP_MATCH_WRPRS OPX_MATCH (OPX_WRPRS)
#define OP_MATCH_XOR OPX_MATCH (OPX_XOR)
#define OP_MATCH_FLUSHI OPX_MATCH (OPX_FLUSHI)
#define OP_MATCH_FLUSHP OPX_MATCH (OPX_FLUSHP)
#define OP_MATCH_INITI OPX_MATCH (OPX_INITI)
/* Some unusual op masks. */
#define OP_MASK_BREAK ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
| OP_MASK_ROPX | OP_MASK_OP) \
& 0xfffff03f)
#define OP_MASK_CALLR ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
| OP_MASK_OP))
#define OP_MASK_JMP ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
| OP_MASK_OP))
#define OP_MASK_SYNC ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
| OP_MASK_OP))
#define OP_MASK_TRAP ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
| OP_MASK_ROPX | OP_MASK_OP) \
& 0xfffff83f)
#define OP_MASK_WRCTL ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
| OP_MASK_OP)) /*& 0xfffff83f */
#define OP_MASK_NEXTPC ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
| OP_MASK_OP))
#define OP_MASK_FLUSHI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
| OP_MASK_OP))
#define OP_MASK_INITI ((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
| OP_MASK_OP))
#define OP_MASK_ROLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
#define OP_MASK_SLLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
#define OP_MASK_SRAI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
#define OP_MASK_SRLI ((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
#define OP_MASK_RDCTL ((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
| OP_MASK_OP)) /*& 0xfffff83f */
#ifndef OP_MASK
#define OP_MASK 0xffffffff
#endif
/* These convenience macros to extract instruction fields are used by GDB. */
#define GET_IW_A(Iw) \
(((Iw) >> IW_A_LSB) & IW_A_MASK)
#define GET_IW_B(Iw) \
(((Iw) >> IW_B_LSB) & IW_B_MASK)
#define GET_IW_C(Iw) \
(((Iw) >> IW_C_LSB) & IW_C_MASK)
#define GET_IW_CONTROL_REGNUM(Iw) \
(((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK)
#define GET_IW_IMM16(Iw) \
(((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK)
#define GET_IW_IMM26(Iw) \
(((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK)
#define GET_IW_OP(Iw) \
(((Iw) >> IW_OP_LSB) & IW_OP_MASK)
#define GET_IW_OPX(Iw) \
(((Iw) >> IW_OPX_LSB) & IW_OPX_MASK)
/* These are the data structures we use to hold the instruction information. */
extern const struct nios2_opcode nios2_builtin_opcodes[];
extern const int bfd_nios2_num_builtin_opcodes;
extern struct nios2_opcode *nios2_opcodes;
extern int bfd_nios2_num_opcodes;
/* These are the data structures used to hold the register information. */
extern const struct nios2_reg nios2_builtin_regs[];
extern struct nios2_reg *nios2_regs;
extern const int nios2_num_builtin_regs;
extern int nios2_num_regs;
/* Machine-independent macro for number of opcodes. */
#define NUMOPCODES bfd_nios2_num_opcodes
#define NUMREGISTERS nios2_num_regs;
/* This is made extern so that the assembler can use it to find out
what instruction caused an error. */
extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long);
#endif /* _NIOS2_H */

421
contrib/toolchain/binutils/include/opcode/np1.h Normal file
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@@ -0,0 +1,421 @@
/* Print GOULD NPL instructions for GDB, the GNU debugger.
Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc.
This file is part of GDB.
GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
struct gld_opcode
{
char *name;
unsigned long opcode;
unsigned long mask;
char *args;
int length;
};
/* We store four bytes of opcode for all opcodes because that
is the most any of them need. The actual length of an instruction
is always at least 2 bytes, and at most four. The length of the
instruction is based on the opcode.
The mask component is a mask saying which bits must match
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing characters
that are used to format the arguments to the instruction. */
/* Kinds of operands:
r Register in first field
R Register in second field
b Base register in first field
B Base register in second field
v Vector register in first field
V Vector register in first field
A Optional address register (base register)
X Optional index register
I Immediate data (16bits signed)
O Offset field (16bits signed)
h Offset field (15bits signed)
d Offset field (14bits signed)
S Shift count field
any other characters are printed as is... */
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
must be consecutive. */
struct gld_opcode gld_opcodes[] =
{
{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 },
{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 },
{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 },
{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 },
{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 },
{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 },
{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 },
{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 },
{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 },
{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 },
{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 },
{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 },
{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 },
{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 },
{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 },
{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 },
{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 },
{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 },
{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 },
{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 },
{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 },
{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 },
{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 },
{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 },
{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 },
{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 },
{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 },
{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 },
{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 },
{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 },
{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 },
{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 },
{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 },
{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 },
{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 },
{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 },
{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 },
{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 },
{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 },
{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 },
{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 },
{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 },
{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 },
{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 },
{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 },
{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 },
{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 },
{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 },
{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 },
{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 },
{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 },
{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 },
{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 },
{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 },
{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 },
{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 },
{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 },
{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 },
{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 },
{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 },
{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 },
{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 },
{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 },
{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 },
{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 },
{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 },
{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 },
{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 },
{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 },
{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 },
{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 },
{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 },
{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 },
{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 },
{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 },
{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 },
{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 },
{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 },
{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 },
{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 },
{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 },
{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 },
{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 },
{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 },
{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 },
{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 },
{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 },
{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 },
{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 },
{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 },
{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 },
{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 },
{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 },
{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 },
{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 },
{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 },
{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 },
{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 },
{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 },
{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 },
{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 },
{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 },
{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 },
{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 },
{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 },
{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 },
{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 },
{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 },
{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 },
{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 },
{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 },
{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 },
{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 },
{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 },
{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 },
{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 },
{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 },
{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 },
{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 },
{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 },
{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 },
{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 },
{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 },
{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 },
{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 },
{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 },
{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 },
{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 },
{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 },
{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 },
{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 },
{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 },
{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 },
{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 },
{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 },
{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 },
{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 },
{ "slc", 0x24400000, 0xfc600000, "r,S", 2 },
{ "slad", 0x20400000, 0xfc600000, "r,S", 2 },
{ "slld", 0x20600000, 0xfc600000, "r,S", 2 },
{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 },
{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 },
{ "src", 0x24000000, 0xfc600000, "r,S", 2 },
{ "srad", 0x20000000, 0xfc600000, "r,S", 2 },
{ "srld", 0x20200000, 0xfc600000, "r,S", 2 },
{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 },
{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 },
{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 },
{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 },
{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 },
{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 },
{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 },
{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 },
{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 },
{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 },
{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 },
{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 },
{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 },
{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 },
{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 },
{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 },
{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 },
{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 },
{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 },
{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 },
{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 },
{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 },
{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 },
{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 },
{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 },
{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 },
{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 },
{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 },
{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 },
{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 },
{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 },
{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 },
{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 },
{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 },
{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 },
{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 },
{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 },
{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 },
{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 },
{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 },
{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 },
{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 },
{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 },
{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 },
{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 },
{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 },
{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 },
{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 },
{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 },
{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 },
{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 },
{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 },
{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 },
{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 },
{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 },
{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 },
{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 },
{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 },
{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 },
{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 },
{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 },
{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 },
{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 },
{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 },
{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 },
{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 },
{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 },
{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 },
{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 },
{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 },
{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 },
{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 },
{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 },
{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 },
{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 },
{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 },
{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 },
{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 },
{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 },
{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 },
{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 },
{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 },
{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 },
{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 },
{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 },
{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 },
{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 },
{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 },
{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 },
{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 },
{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 },
{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 },
{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 },
{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 },
{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 },
{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 },
{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 },
{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 },
{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 },
{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 },
{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 },
{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 },
{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 },
{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 },
{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 },
{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 },
{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 },
{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 },
{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 },
{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 },
{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 },
{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 },
{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 },
{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 },
{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 },
{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 },
{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 },
{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 },
{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 },
{ "exr", 0xf8070000, 0xfc0f0000, "", 4 },
{ "halt", 0x00000000, 0xfc0f0000, "", 2 },
{ "wait", 0x00010000, 0xfc0f0000, "", 2 },
{ "nop", 0x00020000, 0xfc0f0000, "", 2 },
{ "eiae", 0x00030000, 0xfc0f0000, "", 2 },
{ "efae", 0x000d0000, 0xfc0f0000, "", 2 },
{ "diae", 0x000e0000, 0xfc0f0000, "", 2 },
{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 },
{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 },
{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 },
{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 },
{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 },
{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 },
{ "attnio", 0x00050000, 0xfc0f0000, "", 2 },
{ "fudit", 0x28080000, 0xfc0f0000, "", 2 },
{ "break", 0x28090000, 0xfc0f0000, "", 2 },
{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 },
{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 },
{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 },
{ "block", 0x04060000, 0xfc0f0000, "", 2 },
{ "unblock", 0x04070000, 0xfc0f0000, "", 2 },
{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 },
{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 },
{ "fq", 0x04080000, 0xfc0f0000, "r", 2 },
{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 },
{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 },
{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 },
{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 },
{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 },
{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 },
{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 },
{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 },
{ "grun", 0x0c040000, 0xfc0f0000, "", 2 },
{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 },
{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 },
{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 },
{ "trver", 0x28070000, 0xfc0f0000, "r", 2 },
{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 },
{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 },
{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 },
{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 },
{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 },
{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 },
{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 },
{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 },
{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 },
{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 },
};
int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
sizeof(gld_opcodes[0]);

487
contrib/toolchain/binutils/include/opcode/ns32k.h Normal file
View File

@@ -0,0 +1,487 @@
/* ns32k-opcode.h -- Opcode table for National Semi 32k processor
Copyright 1987, 1991, 1994, 2002, 2010 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifdef SEQUENT_COMPATABILITY
#define DEF_MODEC 20
#define DEF_MODEL 21
#endif
#ifndef DEF_MODEC
#define DEF_MODEC 20
#endif
#ifndef DEF_MODEL
#define DEF_MODEL 20
#endif
/*
After deciding the instruction entry (via hash.c) the instruction parser
will try to match the operands after the instruction to the required set
given in the entry operandfield. Every operand will result in a change in
the opcode or the addition of data to the opcode.
The operands in the source instruction are checked for inconsistent
semantics.
F : 32 bit float general form
L : 64 bit float "
B : byte "
W : word "
D : double-word "
A : double-word gen-address-form ie no regs, no immediate
I : integer writeable gen int except immediate (A + reg)
Z : floating writeable gen float except immediate (Z + freg)
d : displacement
b : displacement - pc relative addressing acb
p : displacement - pc relative addressing br bcond bsr cxp
q : quick
i : immediate (8 bits)
This is not a standard ns32k operandtype, it is used to build
instructions like svc arg1,arg2
Svc is the instruction SuperVisorCall and is sometimes used to
call OS-routines from usermode. Some args might be handy!
r : register number (3 bits)
O : setcfg instruction optionslist
C : cinv instruction optionslist
S : stringinstruction optionslist
U : registerlist save,enter
u : registerlist restore,exit
M : mmu register
P : cpu register
g : 3:rd operand of inss or exts instruction
G : 4:th operand of inss or exts instruction
Those operands are encoded in the same byte.
This byte is placed last in the instruction.
f : operand of sfsr
H : sequent-hack for bsr (Warning)
column 1 instructions
2 number of bits in opcode.
3 number of bits in opcode explicitly
determined by the instruction type.
4 opcodeseed, the number we build our opcode
from.
5 operandtypes, used by operandparser.
6 size in bytes of immediate
*/
struct ns32k_opcode {
const char *name;
unsigned char opcode_id_size; /* not used by the assembler */
unsigned char opcode_size;
unsigned long opcode_seed;
const char *operands;
unsigned char im_size; /* not used by dissassembler */
const char *default_args; /* default to those args when none given */
char default_modec; /* default to this addr-mode when ambigous
ie when the argument of a general addr-mode
is a plain constant */
char default_model; /* is a plain label */
};
#ifdef comment
/* This section was from the gdb version of this file. */
#ifndef ns32k_opcodeT
#define ns32k_opcodeT int
#endif /* no ns32k_opcodeT */
struct not_wot /* ns32k opcode table: wot to do with this */
/* particular opcode */
{
int obits; /* number of opcode bits */
int ibits; /* number of instruction bits */
ns32k_opcodeT code; /* op-code (may be > 8 bits!) */
const char *args; /* how to compile said opcode */
};
struct not /* ns32k opcode text */
{
const char *name; /* opcode name: lowercase string [key] */
struct not_wot detail; /* rest of opcode table [datum] */
};
/* Instructions look like this:
basic instruction--1, 2, or 3 bytes
index byte for operand A, if operand A is indexed--1 byte
index byte for operand B, if operand B is indexed--1 byte
addressing extension for operand A
addressing extension for operand B
implied operands
Operand A is the operand listed first in the following opcode table.
Operand B is the operand listed second in the following opcode table.
All instructions have at most 2 general operands, so this is enough.
The implied operands are associated with operands other than A and B.
Each operand has a digit and a letter.
The digit gives the position in the assembly language. The letter,
one of the following, tells us what kind of operand it is. */
/* F : 32 bit float
* L : 64 bit float
* B : byte
* W : word
* D : double-word
* I : integer not immediate
* Z : floating not immediate
* d : displacement
* q : quick
* i : immediate (8 bits)
* r : register number (3 bits)
* p : displacement - pc relative addressing
*/
#endif /* comment */
static const struct ns32k_opcode ns32k_opcodes[]=
{
{ "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL },
{ "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL },
{ "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL },
{ "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL },
{ "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL },
{ "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL },
{ "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 },
{ "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL },
{ "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "beq", 8,8, 0x0a, "1p", 0, "", 21,21 },
{ "bne", 8,8, 0x1a, "1p", 0, "", 21,21 },
{ "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 },
{ "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 },
{ "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 },
{ "bls", 8,8, 0x5a, "1p", 0, "", 21,21 },
{ "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 },
{ "ble", 8,8, 0x7a, "1p", 0, "", 21,21 },
{ "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 },
{ "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 },
{ "blo", 8,8, 0xaa, "1p", 0, "", 21,21 },
{ "bhs", 8,8, 0xba, "1p", 0, "", 21,21 },
{ "blt", 8,8, 0xca, "1p", 0, "", 21,21 },
{ "bge", 8,8, 0xda, "1p", 0, "", 21,21 },
{ "but", 8,8, 0xea, "1p", 0, "", 21,21 },
{ "buf", 8,8, 0xfa, "1p", 0, "", 21,21 },
{ "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "br", 8,8, 0xea, "1p", 0, "", 21,21 },
#ifdef SEQUENT_COMPATABILITY
{ "bsr", 8,8, 0x02, "1H", 0, "", 21,21 },
#else
{ "bsr", 8,8, 0x02, "1p", 0, "", 21,21 },
#endif
{ "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL },
{ "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL },
{ "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL },
{ "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL },
{ "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL },
{ "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL },
{ "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL },
{ "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL },
{ "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL },
{ "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL },
{ "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL },
{ "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL },
{ "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL },
{ "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL },
{ "cxp", 8,8, 0x22, "1p", 0, "", 21,21 },
{ "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL },
{ "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL },
{ "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL },
{ "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL },
{ "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL },
{ "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL },
{ "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL },
{ "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL },
{ "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL },
{ "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL },
{ "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL },
{ "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL },
{ "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL },
{ "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL },
{ "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL },
{ "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL },
{ "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL },
{ "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL },
{ "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL },
{ "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 },
{ "jump", 11,16, 0x27f, "1A", 4, "", 21,21 },
{ "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL },
{ "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL },
{ "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL },
{ "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL },
{ "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL },
{ "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL },
{ "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL },
{ "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL },
{ "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL },
{ "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL },
{ "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL },
{ "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL },
{ "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL },
{ "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL },
{ "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL },
{ "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL },
{ "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL },
{ "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL },
{ "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL },
{ "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL },
{ "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL },
{ "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL },
{ "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL },
{ "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL },
{ "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL },
{ "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL },
{ "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL },
{ "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL },
{ "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL },
{ "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL },
{ "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL },
{ "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
#ifdef NS32K_SVC_IMMED_OPERANDS
{ "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */
#else
{ "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL },
#endif
{ "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL },
{ "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL },
{ "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL },
{ "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL },
{ "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL },
{ "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL },
{ "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL },
{ "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL },
{ "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL },
{ "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
{ "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL },
{ "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL },
{ "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL },
{ "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL },
};
#define MAX_ARGS 4
#define ARG_LEN 50

181
contrib/toolchain/binutils/include/opcode/or32.h Normal file
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/* Table of opcodes for the OpenRISC 1000 ISA.
Copyright 2002, 2003, 2010 Free Software Foundation, Inc.
Contributed by Damjan Lampret (lampret@opencores.org).
This file is part of or1k_gen_isa, or1ksim, GDB and GAS.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* We treat all letters the same in encode/decode routines so
we need to assign some characteristics to them like signess etc. */
#ifndef OR32_H_ISA
#define OR32_H_ISA
#define NUM_UNSIGNED (0)
#define NUM_SIGNED (1)
#define MAX_GPRS 32
#define PAGE_SIZE 4096
#undef __HALF_WORD_INSN__
#define OPERAND_DELIM (',')
#define OR32_IF_DELAY (1)
#define OR32_W_FLAG (2)
#define OR32_R_FLAG (4)
struct or32_letter
{
char letter;
int sign;
/* int reloc; relocation per letter ?? */
};
/* Main instruction specification array. */
struct or32_opcode
{
/* Name of the instruction. */
char *name;
/* A string of characters which describe the operands.
Valid characters are:
,() Itself. Characters appears in the assembly code.
rA Register operand.
rB Register operand.
rD Register operand.
I An immediate operand, range -32768 to 32767.
J An immediate operand, range . (unused)
K An immediate operand, range 0 to 65535.
L An immediate operand, range 0 to 63.
M An immediate operand, range . (unused)
N An immediate operand, range -33554432 to 33554431.
O An immediate operand, range . (unused). */
char *args;
/* Opcode and operand encoding. */
char *encoding;
void (*exec) (void);
unsigned int flags;
};
#define OPTYPE_LAST (0x80000000)
#define OPTYPE_OP (0x40000000)
#define OPTYPE_REG (0x20000000)
#define OPTYPE_SIG (0x10000000)
#define OPTYPE_DIS (0x08000000)
#define OPTYPE_DST (0x04000000)
#define OPTYPE_SBIT (0x00001F00)
#define OPTYPE_SHR (0x0000001F)
#define OPTYPE_SBIT_SHR (8)
/* MM: Data how to decode operands. */
extern struct insn_op_struct
{
unsigned long type;
unsigned long data;
} **op_start;
#ifdef HAS_EXECUTION
extern void l_invalid (void);
extern void l_sfne (void);
extern void l_bf (void);
extern void l_add (void);
extern void l_sw (void);
extern void l_sb (void);
extern void l_sh (void);
extern void l_lwz (void);
extern void l_lbs (void);
extern void l_lbz (void);
extern void l_lhs (void);
extern void l_lhz (void);
extern void l_movhi (void);
extern void l_and (void);
extern void l_or (void);
extern void l_xor (void);
extern void l_sub (void);
extern void l_mul (void);
extern void l_div (void);
extern void l_divu (void);
extern void l_sll (void);
extern void l_sra (void);
extern void l_srl (void);
extern void l_j (void);
extern void l_jal (void);
extern void l_jalr (void);
extern void l_jr (void);
extern void l_rfe (void);
extern void l_nop (void);
extern void l_bnf (void);
extern void l_sfeq (void);
extern void l_sfgts (void);
extern void l_sfges (void);
extern void l_sflts (void);
extern void l_sfles (void);
extern void l_sfgtu (void);
extern void l_sfgeu (void);
extern void l_sfltu (void);
extern void l_sfleu (void);
extern void l_mtspr (void);
extern void l_mfspr (void);
extern void l_sys (void);
extern void l_trap (void); /* CZ 21/06/01. */
extern void l_macrc (void);
extern void l_mac (void);
extern void l_msb (void);
extern void l_invalid (void);
extern void l_cust1 (void);
extern void l_cust2 (void);
extern void l_cust3 (void);
extern void l_cust4 (void);
#endif
extern void l_none (void);
extern const struct or32_letter or32_letters[];
extern const struct or32_opcode or32_opcodes[];
extern const unsigned int or32_num_opcodes;
/* Calculates instruction length in bytes. Always 4 for OR32. */
extern int insn_len (int);
/* Is individual insn's operand signed or unsigned? */
extern int letter_signed (char);
/* Number of letters in the individual lettered operand. */
extern int letter_range (char);
/* MM: Returns index of given instruction name. */
extern int insn_index (char *);
/* MM: Returns instruction name from index. */
extern const char *insn_name (int);
/* MM: Constructs new FSM, based on or32_opcodes. */
extern void build_automata (void);
/* MM: Destructs FSM. */
extern void destruct_automata (void);
/* MM: Decodes instruction using FSM. Call build_automata first. */
extern int insn_decode (unsigned int);
/* Disassemble one instruction from insn to disassemble.
Return the size of the instruction. */
int disassemble_insn (unsigned long);
#endif

84
contrib/toolchain/binutils/include/opcode/pdp11.h Normal file
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/* PDP-11 opcde list.
Copyright 2001, 2002, 2010 Free Software Foundation, Inc.
This file is part of GDB and GAS.
GDB and GAS are free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GDB and GAS are distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB or GAS; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/* PDP-11 opcode types. */
#define PDP11_OPCODE_NO_OPS 0
#define PDP11_OPCODE_REG 1 /* register */
#define PDP11_OPCODE_OP 2 /* generic operand */
#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */
#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand,
reversed syntax */
#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float
operand */
#define PDP11_OPCODE_OP_OP 6 /* two generic operands */
#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */
#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative
displacement */
#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */
#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */
#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */
#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */
#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu
accumulator */
#define PDP11_OPCODE_FOP 14 /* generic float operand */
#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int
operand */
#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu
accumulator */
/*
* PDP-11 instruction set extensions.
*
* Please keep the numbers low, as they are used as indices into
* an array.
*/
#define PDP11_NONE 0 /* not in instruction set */
#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */
#define PDP11_CSM 2 /* commercial instruction set */
#define PDP11_CIS 3 /* commercial instruction set */
#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */
#define PDP11_FIS 5 /* KEV11 floating-point instructions */
#define PDP11_FPP 6 /* FP-11 floating-point instructions */
#define PDP11_LEIS 7 /* limited extended instruction set
(11/40 etc) */
#define PDP11_MFPT 8 /* move from processor type */
#define PDP11_MPROC 9 /* multiprocessor instructions: tstset,
wrtlck */
#define PDP11_MXPS 10 /* move from/to processor status */
#define PDP11_SPL 11 /* set priority level */
#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */
#define PDP11_EXT_NUM 13 /* total number of extension types */
struct pdp11_opcode
{
const char *name;
int opcode;
int mask;
int type;
int extension;
};
extern const struct pdp11_opcode pdp11_opcodes[];
extern const struct pdp11_opcode pdp11_aliases[];
extern const int pdp11_num_opcodes, pdp11_num_aliases;
/* end of pdp11.h */

49
contrib/toolchain/binutils/include/opcode/pj.h Normal file
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/* Definitions for decoding the picoJava opcode table.
Copyright 1999, 2002, 2003, 2010 Free Software Foundation, Inc.
Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* Names used to describe the type of instruction arguments, used by
the assembler and disassembler. Attributes are encoded in various fields. */
/* reloc size pcrel uns */
#define O_N 0
#define O_16 (1<<4 | 2 | (0<<6) | (0<<3))
#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3))
#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3))
#define O_8 (3<<4 | 1 | (0<<6) | (0<<3))
#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3))
#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3))
#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3))
#define O_32 (6<<4 | 4 | (0<<6) | (0<<3))
#define ASIZE(x) ((x) & 0x7)
#define PCREL(x) (!!((x) & (1<<6)))
#define UNS(x) (!!((x) & (1<<3)))
typedef struct pj_opc_info_t
{
short opcode;
short opcode_next;
char len;
unsigned char arg[2];
union {
const char *name;
void (*func) (struct pj_opc_info_t *, char *);
} u;
} pj_opc_info_t;

283
contrib/toolchain/binutils/include/opcode/pn.h Normal file
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/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger.
Copyright 1986, 1987, 1989, 1991, 2010 Free Software Foundation, Inc.
This file is part of GDB.
GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
struct gld_opcode
{
char *name;
unsigned long opcode;
unsigned long mask;
char *args;
int length;
};
/* We store four bytes of opcode for all opcodes because that
is the most any of them need. The actual length of an instruction
is always at least 2 bytes, and at most four. The length of the
instruction is based on the opcode.
The mask component is a mask saying which bits must match
particular opcode in order for an instruction to be an instance
of that opcode.
The args component is a string containing characters
that are used to format the arguments to the instruction. */
/* Kinds of operands:
r Register in first field
R Register in second field
b Base register in first field
B Base register in second field
v Vector register in first field
V Vector register in first field
A Optional address register (base register)
X Optional index register
I Immediate data (16bits signed)
O Offset field (16bits signed)
h Offset field (15bits signed)
d Offset field (14bits signed)
S Shift count field
any other characters are printed as is...
*/
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
must be consecutive.
*/
struct gld_opcode gld_opcodes[] =
{
{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 },
{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 },
{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 },
{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 },
{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 },
{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 },
{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 },
{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 },
{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 },
{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 },
{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 },
{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 },
{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 },
{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 },
{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 },
{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 },
{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 },
{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 },
{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 },
{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 },
{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 },
{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 },
{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 },
{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 },
{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 },
{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 },
{ "bei", 0x00060000, 0xffff0000, "", 2 },
{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 },
{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 },
{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 },
{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 },
{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 },
{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 },
{ "bsub", 0x5c080000, 0xff8f0000, "", 2 },
{ "bsubm", 0x28080000, 0xfc080000, "", 4 },
{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 },
{ "call", 0x28080000, 0xfc0f0000, "", 2 },
{ "callm", 0x5c080000, 0xff880000, "", 4 },
{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 },
{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 },
{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 },
{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 },
{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 },
{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 },
{ "cea", 0x000f0000, 0xffff0000, "", 2 },
{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 },
{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 },
{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 },
{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 },
{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 },
{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 },
{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 },
{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 },
{ "dae", 0x000e0000, 0xffff0000, "", 2 },
{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 },
{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 },
{ "di", 0xfc010000, 0xfc07ffff, "I", 4 },
{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 },
{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 },
{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 },
{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 },
{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 },
{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 },
{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 },
{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 },
{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 },
{ "eae", 0x00080000, 0xffff0000, "", 2 },
{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 },
{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 },
{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 },
{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 },
{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 },
{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 },
{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 },
{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 },
{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 },
{ "es", 0x00040000, 0xfc7f0000, "r", 2 },
{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 },
{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 },
{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 },
{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 },
{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 },
{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 },
{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 },
{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 },
{ "halt", 0x00000000, 0xffff0000, "", 2 },
{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 },
{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 },
{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 },
{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 },
{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 },
{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 },
{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 },
{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 },
{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 },
{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 },
{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 },
{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 },
{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 },
{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 },
{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 },
{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 },
{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 },
{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 },
{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 },
{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 },
{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 },
{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 },
{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 },
{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 },
{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 },
{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 },
{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 },
{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 },
{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 },
{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 },
{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 },
{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 },
{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 },
{ "nop", 0x00020000, 0xffff0000, "", 2 },
{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 },
{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 },
{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 },
{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 },
{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 },
{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 },
{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 },
{ "return", 0x280e0000, 0xfc7f0000, "", 2 },
{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 },
{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 },
{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 },
{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 },
{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 },
{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 },
{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 },
{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 },
{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 },
{ "sea", 0x000d0000, 0xffff0000, "", 2 },
{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 },
{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 },
{ "sipu", 0x000a0000, 0xffff0000, "", 2 },
{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 },
{ "slad", 0x20400000, 0xfc600000, "r,S", 2 },
{ "slc", 0x24400000, 0xfc600000, "r,S", 2 },
{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 },
{ "slld", 0x20600000, 0xfc600000, "r,S", 2 },
{ "smc", 0x04070000, 0xfc070000, "", 2 },
{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 },
{ "srad", 0x20000000, 0xfc600000, "r,S", 2 },
{ "src", 0x24000000, 0xfc600000, "r,S", 2 },
{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 },
{ "srld", 0x20200000, 0xfc600000, "r,S", 2 },
{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 },
{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 },
{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 },
{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 },
{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 },
{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 },
{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 },
{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 },
{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 },
{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 },
{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 },
{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 },
{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 },
{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 },
{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 },
{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 },
{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 },
{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 },
{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 },
{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 },
{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 },
{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 },
{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 },
{ "svc", 0xc8060000, 0xffff0000, "", 4 },
{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 },
{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 },
{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 },
{ "tccr", 0x28040000, 0xfc7f0000, "", 2 },
{ "td", 0xfc050000, 0xfc070000, "r,f", 4 },
{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 },
{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 },
{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 },
{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 },
{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 },
{ "trcc", 0x28050000, 0xfc7f0000, "", 2 },
{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 },
{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 },
{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 },
{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 },
{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 },
{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 },
{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 },
{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 },
{ "uei", 0x00070000, 0xffff0000, "", 2 },
{ "wait", 0x00010000, 0xffff0000, "", 2 },
{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 },
{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 },
{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 },
{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 },
{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 },
{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 },
{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 },
{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 },
{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 },
{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 },
{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 },
{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 },
};
int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]);
struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) /
sizeof(gld_opcodes[0]);

413
contrib/toolchain/binutils/include/opcode/ppc.h Normal file
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/* ppc.h -- Header file for PowerPC opcode table
Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef PPC_H
#define PPC_H
#include "bfd_stdint.h"
typedef uint64_t ppc_cpu_t;
/* The opcode table is an array of struct powerpc_opcode. */
struct powerpc_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned long opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned long mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
are listed below. */
ppc_cpu_t flags;
/* One bit flags for the opcode. These are used to indicate which
specific processors no longer support the instructions. The defined
values are listed below. */
ppc_cpu_t deprecated;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
extern const struct powerpc_opcode vle_opcodes[];
extern const int vle_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
/* Opcode is defined for the PowerPC architecture. */
#define PPC_OPCODE_PPC 1
/* Opcode is defined for the POWER (RS/6000) architecture. */
#define PPC_OPCODE_POWER 2
/* Opcode is defined for the POWER2 (Rios 2) architecture. */
#define PPC_OPCODE_POWER2 4
/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
but it also supports many additional POWER instructions. */
#define PPC_OPCODE_601 8
/* Opcode is supported in both the Power and PowerPC architectures
(ie, compiler's -mcpu=common or assembler's -mcom). More than just
the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
and PPC_OPCODE_POWER2 because many instructions changed mnemonics
between POWER and POWERPC. */
#define PPC_OPCODE_COMMON 0x10
/* Opcode is supported for any Power or PowerPC platform (this is
for the assembler's -many option, and it eliminates duplicates). */
#define PPC_OPCODE_ANY 0x20
/* Opcode is only defined on 64 bit architectures. */
#define PPC_OPCODE_64 0x40
/* Opcode is supported as part of the 64-bit bridge. */
#define PPC_OPCODE_64_BRIDGE 0x80
/* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC 0x100
/* Opcode is supported by PowerPC 403 processor. */
#define PPC_OPCODE_403 0x200
/* Opcode is supported by PowerPC BookE processor. */
#define PPC_OPCODE_BOOKE 0x400
/* Opcode is supported by PowerPC 440 processor. */
#define PPC_OPCODE_440 0x800
/* Opcode is only supported by Power4 architecture. */
#define PPC_OPCODE_POWER4 0x1000
/* Opcode is only supported by Power7 architecture. */
#define PPC_OPCODE_POWER7 0x2000
/* Opcode is only supported by e500x2 Core. */
#define PPC_OPCODE_SPE 0x4000
/* Opcode is supported by e500x2 Integer select APU. */
#define PPC_OPCODE_ISEL 0x8000
/* Opcode is an e500 SPE floating point instruction. */
#define PPC_OPCODE_EFS 0x10000
/* Opcode is supported by branch locking APU. */
#define PPC_OPCODE_BRLOCK 0x20000
/* Opcode is supported by performance monitor APU. */
#define PPC_OPCODE_PMR 0x40000
/* Opcode is supported by cache locking APU. */
#define PPC_OPCODE_CACHELCK 0x80000
/* Opcode is supported by machine check APU. */
#define PPC_OPCODE_RFMCI 0x100000
/* Opcode is only supported by Power5 architecture. */
#define PPC_OPCODE_POWER5 0x200000
/* Opcode is supported by PowerPC e300 family. */
#define PPC_OPCODE_E300 0x400000
/* Opcode is only supported by Power6 architecture. */
#define PPC_OPCODE_POWER6 0x800000
/* Opcode is only supported by PowerPC Cell family. */
#define PPC_OPCODE_CELL 0x1000000
/* Opcode is supported by CPUs with paired singles support. */
#define PPC_OPCODE_PPCPS 0x2000000
/* Opcode is supported by Power E500MC */
#define PPC_OPCODE_E500MC 0x4000000
/* Opcode is supported by PowerPC 405 processor. */
#define PPC_OPCODE_405 0x8000000
/* Opcode is supported by Vector-Scalar (VSX) Unit */
#define PPC_OPCODE_VSX 0x10000000
/* Opcode is supported by A2. */
#define PPC_OPCODE_A2 0x20000000
/* Opcode is supported by PowerPC 476 processor. */
#define PPC_OPCODE_476 0x40000000
/* Opcode is supported by AppliedMicro Titan core */
#define PPC_OPCODE_TITAN 0x80000000
/* Opcode which is supported by the e500 family */
#define PPC_OPCODE_E500 0x100000000ull
/* Opcode is supported by Extended Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC2 0x200000000ull
/* Opcode is supported by Power E6500 */
#define PPC_OPCODE_E6500 0x400000000ull
/* Opcode is supported by Thread management APU */
#define PPC_OPCODE_TMR 0x800000000ull
/* Opcode which is supported by the VLE extension. */
#define PPC_OPCODE_VLE 0x1000000000ull
/* Opcode is only supported by Power8 architecture. */
#define PPC_OPCODE_POWER8 0x2000000000ull
/* Opcode which is supported by the Hardware Transactional Memory extension. */
/* Currently, this is the same as the POWER8 mask. If another cpu comes out
that isn't a superset of POWER8, we can define this to its own mask. */
#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
/* A macro to determine if the instruction is a 2-byte VLE insn. */
#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
/* A macro to extract the major opcode from a VLE instruction. */
#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
/* A macro to convert a VLE opcode to a VLE opcode segment. */
#define VLE_OP_TO_SEG(i) ((i) >> 1)
/* The operands table is an array of struct powerpc_operand. */
struct powerpc_operand
{
/* A bitmask of bits in the operand. */
unsigned int bitm;
/* The shift operation to be applied to the operand. No shift
is made if this is zero. For positive values, the operand
is shifted left by SHIFT. For negative values, the operand
is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
that BITM and SHIFT cannot be used to determine where the
operand goes in the insn. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
if (o->shift >= 0)
i |= (op & o->bitm) << o->shift;
else
i |= (op & o->bitm) >> -o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert)
(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
if (o->shift >= 0)
op = (i >> o->shift) & o->bitm;
else
op = (i << -o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
is the result).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
/* One bit syntax flags. */
unsigned long flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the powerpc_opcodes table. */
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
/* Use with the shift field of a struct powerpc_operand to indicate
that BITM and SHIFT cannot be used to determine where the operand
goes in the insn. */
#define PPC_OPSHIFT_INV (-1 << 31)
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
#define PPC_OPERAND_SIGNED (0x1)
/* This operand takes signed values, but also accepts a full positive
range of values when running in 32 bit mode. That is, if bits is
16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
this flag is ignored. */
#define PPC_OPERAND_SIGNOPT (0x2)
/* This operand does not actually exist in the assembler input. This
is used to support extended mnemonics such as mr, for which two
operands fields are identical. The assembler should call the
insert function with any op value. The disassembler should call
the extract function, ignore the return value, and check the value
placed in the valid argument. */
#define PPC_OPERAND_FAKE (0x4)
/* The next operand should be wrapped in parentheses rather than
separated from this one by a comma. This is used for the load and
store instructions which want their operands to look like
reg,displacement(reg)
*/
#define PPC_OPERAND_PARENS (0x8)
/* This operand may use the symbolic names for the CR fields, which
are
lt 0 gt 1 eq 2 so 3 un 3
cr0 0 cr1 1 cr2 2 cr3 3
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
#define PPC_OPERAND_CR_BIT (0x10)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define PPC_OPERAND_GPR (0x20)
/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
#define PPC_OPERAND_GPR_0 (0x40)
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define PPC_OPERAND_FPR (0x80)
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define PPC_OPERAND_RELATIVE (0x100)
/* This operand is an absolute branch address. The disassembler
prints these symbolically if possible. */
#define PPC_OPERAND_ABSOLUTE (0x200)
/* This operand is optional, and is zero if omitted. This is used for
example, in the optional BF field in the comparison instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
#define PPC_OPERAND_OPTIONAL (0x400)
/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
is omitted, then for the next operand use this operand value plus
1, ignoring the next operand field for the opcode. This wretched
hack is needed because the Power rotate instructions can take
either 4 or 5 operands. The disassembler should print this operand
out regardless of the PPC_OPERAND_OPTIONAL field. */
#define PPC_OPERAND_NEXT (0x800)
/* This operand should be regarded as a negative number for the
purposes of overflow checking (i.e., the normal most negative
number is disallowed and one more than the normal most positive
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (0x1000)
/* This operand names a vector unit register. The disassembler
prints these with a leading 'v'. */
#define PPC_OPERAND_VR (0x2000)
/* This operand is for the DS field in a DS form instruction. */
#define PPC_OPERAND_DS (0x4000)
/* This operand is for the DQ field in a DQ form instruction. */
#define PPC_OPERAND_DQ (0x8000)
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
/* Xilinx APU and FSL related operands */
#define PPC_OPERAND_FSL (0x20000)
#define PPC_OPERAND_FCR (0x40000)
#define PPC_OPERAND_UDI (0x80000)
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
/* This is a CR FIELD that does not use symbolic names. */
#define PPC_OPERAND_CR_REG (0x200000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
array of struct powerpc_macro. */
struct powerpc_macro
{
/* The macro name. */
const char *name;
/* The number of operands the macro takes. */
unsigned int operands;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The values are the
same as those for the struct powerpc_opcode flags field. */
ppc_cpu_t flags;
/* A format string to turn the macro into a normal instruction.
Each %N in the string is replaced with operand number N (zero
based). */
const char *format;
};
extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
#endif /* PPC_H */

305
contrib/toolchain/binutils/include/opcode/pyr.h Normal file
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/* pyramid.opcode.h -- gdb initial attempt.
Copyright 2001, 2010 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
/* pyramid opcode table: wot to do with this
particular opcode */
struct pyr_datum
{
char nargs;
char * args; /* how to compile said opcode */
unsigned long mask; /* Bit vector: which operand modes are valid
for this opcode */
unsigned char code; /* op-code (always 6(?) bits */
};
typedef struct pyr_insn_format
{
unsigned int mode :4;
unsigned int operator :8;
unsigned int index_scale :2;
unsigned int index_reg :6;
unsigned int operand_1 :6;
unsigned int operand_2:6;
} pyr_insn_format;
/* We store four bytes of opcode for all opcodes.
Pyramid is sufficiently RISCy that:
- insns are always an integral number of words;
- the length of any insn can be told from the first word of
the insn. (ie, if there are zero, one, or two words of
immediate operand/offset).
The args component is a string containing two characters for each
operand of the instruction. The first specifies the kind of operand;
the second, the place it is stored. */
/* Kinds of operands:
mask assembler syntax description
0x0001: movw Rn,Rn register to register
0x0002: movw K,Rn quick immediate to register
0x0004: movw I,Rn long immediate to register
0x0008: movw (Rn),Rn register indirect to register
movw (Rn)[x],Rn register indirect to register
0x0010: movw I(Rn),Rn offset register indirect to register
movw I(Rn)[x],Rn offset register indirect, indexed, to register
0x0020: movw Rn,(Rn) register to register indirect
0x0040: movw K,(Rn) quick immediate to register indirect
0x0080: movw I,(Rn) long immediate to register indirect
0x0100: movw (Rn),(Rn) register indirect to-register indirect
0x0100: movw (Rn),(Rn) register indirect to-register indirect
0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect
0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect
0x0400: movw Rn,I(Rn) register to register indirect+offset
0x0800: movw K,I(Rn) quick immediate to register indirect+offset
0x1000: movw I,I(Rn) long immediate to register indirect+offset
0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset
0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect
+offset
0x0000: (irregular) ???
Each insn has a four-bit field encoding the type(s) of its operands.
*/
/* Some common combinations
*/
/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/
#define GEN_TO_REG (31)
#define UNKNOWN ((unsigned long)-1)
#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15))
#define CONVERT (1|8|0x10|0x20|0x200)
#define K_TO_REG (2)
#define I_TO_REG (4)
#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG)
#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG)
/* The assembler requires that this array be sorted as follows:
all instances of the same mnemonic must be consecutive.
All instances of the same mnemonic with the same number of operands
must be consecutive.
*/
struct pyr_opcode /* pyr opcode text */
{
char * name; /* opcode name: lowercase string [key] */
struct pyr_datum datum; /* rest of opcode table [datum] */
};
#define pyr_how args
#define pyr_nargs nargs
#define pyr_mask mask
#define pyr_name name
struct pyr_opcode pyr_opcodes[] =
{
{"movb", { 2, "", UNKNOWN, 0x11}, },
{"movh", { 2, "", UNKNOWN, 0x12} },
{"movw", { 2, "", ANY, 0x10} },
{"movl", { 2, "", ANY, 0x13} },
{"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} },
{"mnegf", { 2, "", 0x1, 0x15} },
{"mnegd", { 2, "", 0x1, 0x16} },
{"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} },
{"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} },
{"mabsf", { 2, "", 0x1, 0x19} },
{"mabsd", { 2, "", 0x1, 0x1a} },
{"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} },
{"mtstf", { 2, "", 0x1, 0x1d} },
{"mtstd", { 2, "", 0x1, 0x1e} },
{"mova", { 2, "", 0x8|0x10, 0x1f} },
{"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} },
{"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} },
/* 2 insns out of order here */
{"movbl", { 2, "", 1, 0x4f} },
{"filbl", { 2, "", 1, 0x4e} },
{"cvtbw", { 2, "", CONVERT, 0x22} },
{"cvthw", { 2, "", CONVERT, 0x23} },
{"cvtwb", { 2, "", CONVERT, 0x24} },
{"cvtwh", { 2, "", CONVERT, 0x25} },
{"cvtwf", { 2, "", CONVERT, 0x26} },
{"cvtwd", { 2, "", CONVERT, 0x27} },
{"cvtfw", { 2, "", CONVERT, 0x28} },
{"cvtfd", { 2, "", CONVERT, 0x29} },
{"cvtdw", { 2, "", CONVERT, 0x2a} },
{"cvtdf", { 2, "", CONVERT, 0x2b} },
{"addw", { 2, "", GEN_TO_REG, 0x40} },
{"addwc", { 2, "", GEN_TO_REG, 0x41} },
{"subw", { 2, "", GEN_TO_REG, 0x42} },
{"subwb", { 2, "", GEN_TO_REG, 0x43} },
{"rsubw", { 2, "", GEN_TO_REG, 0x44} },
{"mulw", { 2, "", GEN_TO_REG, 0x45} },
{"emul", { 2, "", GEN_TO_REG, 0x47} },
{"umulw", { 2, "", GEN_TO_REG, 0x46} },
{"divw", { 2, "", GEN_TO_REG, 0x48} },
{"ediv", { 2, "", GEN_TO_REG, 0x4a} },
{"rdivw", { 2, "", GEN_TO_REG, 0x4b} },
{"udivw", { 2, "", GEN_TO_REG, 0x49} },
{"modw", { 2, "", GEN_TO_REG, 0x4c} },
{"umodw", { 2, "", GEN_TO_REG, 0x4d} },
{"addf", { 2, "", 1, 0x50} },
{"addd", { 2, "", 1, 0x51} },
{"subf", { 2, "", 1, 0x52} },
{"subd", { 2, "", 1, 0x53} },
{"mulf", { 2, "", 1, 0x56} },
{"muld", { 2, "", 1, 0x57} },
{"divf", { 2, "", 1, 0x58} },
{"divd", { 2, "", 1, 0x59} },
{"cmpb", { 2, "", UNKNOWN, 0x61} },
{"cmph", { 2, "", UNKNOWN, 0x62} },
{"cmpw", { 2, "", UNKNOWN, 0x60} },
{"ucmpb", { 2, "", UNKNOWN, 0x66} },
/* WHY no "ucmph"??? */
{"ucmpw", { 2, "", UNKNOWN, 0x65} },
{"xchw", { 2, "", UNKNOWN, 0x0f} },
{"andw", { 2, "", GEN_TO_REG, 0x30} },
{"orw", { 2, "", GEN_TO_REG, 0x31} },
{"xorw", { 2, "", GEN_TO_REG, 0x32} },
{"bicw", { 2, "", GEN_TO_REG, 0x33} },
{"lshlw", { 2, "", GEN_TO_REG, 0x38} },
{"ashlw", { 2, "", GEN_TO_REG, 0x3a} },
{"ashll", { 2, "", GEN_TO_REG, 0x3c} },
{"ashrw", { 2, "", GEN_TO_REG, 0x3b} },
{"ashrl", { 2, "", GEN_TO_REG, 0x3d} },
{"rotlw", { 2, "", GEN_TO_REG, 0x3e} },
{"rotrw", { 2, "", GEN_TO_REG, 0x3f} },
/* push and pop insns are "going away next release". */
{"pushw", { 2, "", GEN_TO_REG, 0x0c} },
{"popw", { 2, "", (0x1|0x8|0x10), 0x0d} },
{"pusha", { 2, "", (0x8|0x10), 0x0e} },
{"bitsw", { 2, "", UNKNOWN, 0x35} },
{"bitcw", { 2, "", UNKNOWN, 0x36} },
/* some kind of ibra/dbra insns??*/
{"icmpw", { 2, "", UNKNOWN, 0x67} },
{"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/
{"acmpw", { 2, "", 1, 0x6b} },
/* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op
insn with a 2nd op of tr14. The assembler will have to grok this. */
{"call", { 2, "", GEN_TO_REG, 0x04} },
{"call", { 1, "", GEN_TO_REG, 0x04} },
{"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/
/* Ret is usually written as a 0-op insn, but gets disassembled as a
1-op insn. The operand is always tr15. */
{"ret", { 0, "", UNKNOWN, 0x09} },
{"ret", { 1, "", UNKNOWN, 0x09} },
{"adsf", { 2, "", (1|2|4), 0x08} },
{"retd", { 2, "", UNKNOWN, 0x0a} },
{"btc", { 2, "", UNKNOWN, 0x01} },
{"bfc", { 2, "", UNKNOWN, 0x02} },
/* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */
{"jump", { 1, "", UNKNOWN, 0x00} },
{"btp", { 2, "", UNKNOWN, 0xf00} },
/* read control-stack pointer is another 1-or-2 operand insn. */
{"rcsp", { 2, "", UNKNOWN, 0x01f} },
{"rcsp", { 1, "", UNKNOWN, 0x01f} }
};
/* end: pyramid.opcode.h */
/* One day I will have to take the time to find out what operands
are valid for these insns, and guess at what they mean.
I can't imagine what the "I???" insns (iglob, etc) do.
the arithmetic-sounding insns ending in "p" sound awfully like BCD
arithmetic insns:
dshlp -> Decimal SHift Left Packed
dshrp -> Decimal SHift Right Packed
and cvtlp would be convert long to packed.
I have no idea how the operands are interpreted; but having them be
a long register with (address, length) of an in-memory packed BCD operand
would not be surprising.
They are unlikely to be a packed bcd string: 64 bits of long give
is only 15 digits+sign, which isn't enough for COBOL.
*/
#if 0
{"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/
/* The OSx Operating System Porting Guide claims SSL does things
with tr12 (a register reserved to it) to do with static block-structure
references. SSL=Set Static Link? It's "Going away next release". */
{"ssl", { 2, "", UNKNOWN, 0x00} },
{"ccmps", { 2, "", UNKNOWN, 0x00} },
{"lcd", { 2, "", UNKNOWN, 0x00} },
{"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/
{"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/
{"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/
{"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/
{"ldti", { 2, "", UNKNOWN, 0x00} },
{"ldb", { 2, "", UNKNOWN, 0x00} },
{"stp", { 2, "", UNKNOWN, 0x00} },
{"stti", { 2, "", UNKNOWN, 0x00} },
{"stb", { 2, "", UNKNOWN, 0x00} },
{"stu", { 2, "", UNKNOWN, 0x00} },
{"addp", { 2, "", UNKNOWN, 0x00} },
{"subp", { 2, "", UNKNOWN, 0x00} },
{"mulp", { 2, "", UNKNOWN, 0x00} },
{"divp", { 2, "", UNKNOWN, 0x00} },
{"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */
{"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */
{"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/
{"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/
{"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/
{"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/
{"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/
{"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/
{"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/
{"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/
{"cmovs", { 2, "", UNKNOWN, 0x00} },
{"rsubw", { 2, "", UNKNOWN, 0x00} },
{"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */
{"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */
{"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */
{"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/
{"callr", { 2, "", UNKNOWN, 0x00} },
{"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/
{"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/
{"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/
{"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/
{"ssi", { 2, "", UNKNOWN, 0x00} },
{"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/
{"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */
{"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/
{"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/
{"flic", { 2, "", UNKNOWN, 0x00} },
{"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */
{"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */
{"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */
{"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */
{"lamst", { 2, "", UNKNOWN, 0x00} },
{"tio", { 2, "", UNKNOWN, 0x00} },
#endif

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/* Opcode decoder for the Renesas RL78
Copyright 2011
Free Software Foundation, Inc.
Written by DJ Delorie <dj@redhat.com>
This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* The RL78 decoder in libopcodes is used by the simulator, gdb's
analyzer, and the disassembler. Given an opcode data source, it
decodes the next opcode into the following structures. */
#ifndef RL78_OPCODES_H_INCLUDED
#define RL78_OPCODES_H_INCLUDED
/* For the purposes of these structures, the RL78 registers are as
follows, despite most of these being memory-mapped and
bank-switched: */
typedef enum {
RL78_Reg_None,
/* The order of these matches the encodings. */
RL78_Reg_X,
RL78_Reg_A,
RL78_Reg_C,
RL78_Reg_B,
RL78_Reg_E,
RL78_Reg_D,
RL78_Reg_L,
RL78_Reg_H,
/* The order of these matches the encodings. */
RL78_Reg_AX,
RL78_Reg_BC,
RL78_Reg_DE,
RL78_Reg_HL,
/* Unordered. */
RL78_Reg_SP,
RL78_Reg_PSW,
RL78_Reg_CS,
RL78_Reg_ES,
RL78_Reg_PMC,
RL78_Reg_MEM
} RL78_Register;
typedef enum
{
RL78_Byte = 0,
RL78_Word
} RL78_Size;
typedef enum {
RL78_Condition_T,
RL78_Condition_F,
RL78_Condition_C,
RL78_Condition_NC,
RL78_Condition_H,
RL78_Condition_NH,
RL78_Condition_Z,
RL78_Condition_NZ
} RL78_Condition;
typedef enum {
RL78_Operand_None = 0,
RL78_Operand_Immediate, /* #addend */
RL78_Operand_Register, /* reg */
RL78_Operand_Indirect, /* [reg + reg2 + addend] */
RL78_Operand_Bit, /* reg.bit */
RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */
RL78_Operand_PreDec, /* [--reg] = push */
RL78_Operand_PostInc /* [reg++] = pop */
} RL78_Operand_Type;
typedef enum
{
RLO_unknown,
RLO_add, /* d += s */
RLO_addc, /* d += s + CY */
RLO_and, /* d &= s (byte, word, bit) */
RLO_branch, /* pc = d */
RLO_branch_cond, /* pc = d if cond(src) */
RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */
RLO_break, /* BRK */
RLO_call, /* call */
RLO_cmp, /* cmp d, s */
RLO_divhu, /* DIVHU */
RLO_divwu, /* DIVWU */
RLO_halt, /* HALT */
RLO_mov, /* d = s */
RLO_mach, /* MACH */
RLO_machu, /* MACHU */
RLO_mulu, /* MULU */
RLO_mulh, /* MULH */
RLO_mulhu, /* MULHU */
RLO_nop, /* NOP */
RLO_or, /* d |= s */
RLO_ret, /* RET */
RLO_reti, /* RETI */
RLO_rol, /* d <<= s, MSB to LSB and CY */
RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */
RLO_ror, /* d >>= s, LSB to MSB and CY */
RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */
RLO_sar, /* d >>= s, signed */
RLO_sel, /* rb = s */
RLO_shr, /* d >>= s, unsigned */
RLO_shl, /* d <<= s */
RLO_skip, /* skip next insn is cond(s) */
RLO_stop, /* STOP */
RLO_sub, /* d -= s */
RLO_subc, /* d -= s - CY */
RLO_xch, /* swap d, s */
RLO_xor, /* d ^= s */
} RL78_Opcode_ID;
typedef struct {
RL78_Operand_Type type;
int addend;
RL78_Register reg : 8;
RL78_Register reg2 : 8;
unsigned char bit_number : 4;
unsigned char condition : 3;
unsigned char use_es : 1;
} RL78_Opcode_Operand;
/* PSW flag bits */
#define RL78_PSW_IE 0x80
#define RL78_PSW_Z 0x40
#define RL78_PSW_RBS1 0x20
#define RL78_PSW_AC 0x10
#define RL78_PSW_RBS0 0x08
#define RL78_PSW_ISP1 0x04
#define RL78_PSW_ISP0 0x02
#define RL78_PSW_CY 0x01
#define RL78_SFR_SP 0xffff8
#define RL78_SFR_PSW 0xffffa
#define RL78_SFR_CS 0xffffc
#define RL78_SFR_ES 0xffffd
#define RL78_SFR_PMC 0xffffe
#define RL78_SFR_MEM 0xfffff
typedef struct
{
int lineno;
RL78_Opcode_ID id:24;
unsigned flags:8; /* PSW mask, for side effects only */
int n_bytes;
char * syntax;
RL78_Size size;
/* By convention, these are destination, source. */
RL78_Opcode_Operand op[2];
} RL78_Opcode_Decoded;
int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *);
#endif

215
contrib/toolchain/binutils/include/opcode/rx.h Normal file
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/* Opcode decoder for the Renesas RX
Copyright 2008, 2009, 2010
Free Software Foundation, Inc.
Written by DJ Delorie <dj@redhat.com>
This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* The RX decoder in libopcodes is used by the simulator, gdb's
analyzer, and the disassembler. Given an opcode data source,
it decodes the next opcode into the following structures. */
typedef enum
{
RX_AnySize = 0,
RX_Byte, /* undefined extension */
RX_UByte,
RX_SByte,
RX_Word, /* undefined extension */
RX_UWord,
RX_SWord,
RX_3Byte,
RX_Long,
} RX_Size;
typedef enum
{
RX_Operand_None,
RX_Operand_Immediate, /* #addend */
RX_Operand_Register, /* Rn */
RX_Operand_Indirect, /* [Rn + addend] */
RX_Operand_Postinc, /* [Rn+] */
RX_Operand_Predec, /* [-Rn] */
RX_Operand_Condition, /* eq, gtu, etc */
RX_Operand_Flag, /* [UIOSZC] */
RX_Operand_TwoReg, /* [Rn + scale*R2] */
} RX_Operand_Type;
typedef enum
{
RXO_unknown,
RXO_mov, /* d = s (signed) */
RXO_movbi, /* d = [s,s2] (signed) */
RXO_movbir, /* [s,s2] = d (signed) */
RXO_pushm, /* s..s2 */
RXO_popm, /* s..s2 */
RXO_xchg, /* s <-> d */
RXO_stcc, /* d = s if cond(s2) */
RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */
/* These are all either d OP= s or, if s2 is set, d = s OP s2. Note
that d may be "None". */
RXO_and,
RXO_or,
RXO_xor,
RXO_add,
RXO_sub,
RXO_mul,
RXO_div,
RXO_divu,
RXO_shll,
RXO_shar,
RXO_shlr,
RXO_adc, /* d = d + s + carry */
RXO_sbb, /* d = d - s - ~carry */
RXO_abs, /* d = |s| */
RXO_max, /* d = max(d,s) */
RXO_min, /* d = min(d,s) */
RXO_emul, /* d:64 = d:32 * s */
RXO_emulu, /* d:64 = d:32 * s (unsigned) */
RXO_rolc, /* d <<= 1 through carry */
RXO_rorc, /* d >>= 1 through carry*/
RXO_rotl, /* d <<= #s without carry */
RXO_rotr, /* d >>= #s without carry*/
RXO_revw, /* d = revw(s) */
RXO_revl, /* d = revl(s) */
RXO_branch, /* pc = d if cond(s) */
RXO_branchrel,/* pc += d if cond(s) */
RXO_jsr, /* pc = d */
RXO_jsrrel, /* pc += d */
RXO_rts,
RXO_nop,
RXO_nop2,
RXO_nop3,
RXO_scmpu,
RXO_smovu,
RXO_smovb,
RXO_suntil,
RXO_swhile,
RXO_smovf,
RXO_sstr,
RXO_rmpa,
RXO_mulhi,
RXO_mullo,
RXO_machi,
RXO_maclo,
RXO_mvtachi,
RXO_mvtaclo,
RXO_mvfachi,
RXO_mvfacmi,
RXO_mvfaclo,
RXO_racw,
RXO_sat, /* sat(d) */
RXO_satr,
RXO_fadd, /* d op= s */
RXO_fcmp,
RXO_fsub,
RXO_ftoi,
RXO_fmul,
RXO_fdiv,
RXO_round,
RXO_itof,
RXO_bset, /* d |= (1<<s) */
RXO_bclr, /* d &= ~(1<<s) */
RXO_btst, /* s & (1<<s2) */
RXO_bnot, /* d ^= (1<<s) */
RXO_bmcc, /* d<s> = cond(s2) */
RXO_clrpsw, /* flag index in d */
RXO_setpsw, /* flag index in d */
RXO_mvtipl, /* new IPL in s */
RXO_rtfi,
RXO_rte,
RXO_rtd, /* undocumented */
RXO_brk,
RXO_dbt, /* undocumented */
RXO_int, /* vector id in s */
RXO_stop,
RXO_wait,
RXO_sccnd, /* d = cond(s) ? 1 : 0 */
} RX_Opcode_ID;
/* Condition bitpatterns, as registers. */
#define RXC_eq 0
#define RXC_z 0
#define RXC_ne 1
#define RXC_nz 1
#define RXC_c 2
#define RXC_nc 3
#define RXC_gtu 4
#define RXC_leu 5
#define RXC_pz 6
#define RXC_n 7
#define RXC_ge 8
#define RXC_lt 9
#define RXC_gt 10
#define RXC_le 11
#define RXC_o 12
#define RXC_no 13
#define RXC_always 14
#define RXC_never 15
typedef struct
{
RX_Operand_Type type;
int reg;
int addend;
RX_Size size;
} RX_Opcode_Operand;
typedef struct
{
RX_Opcode_ID id;
int n_bytes;
int prefix;
char * syntax;
RX_Size size;
/* By convention, these are destination, source1, source2. */
RX_Opcode_Operand op[3];
/* The logic here is:
newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
Only the O, S, Z, and C flags are affected. */
char flags_0; /* This also clears out flags-to-be-set. */
char flags_1;
char flags_s;
} RX_Opcode_Decoded;
/* Within the syntax, %c-style format specifiers are as follows:
%% = '%' character
%0 = operand[0] (destination)
%1 = operand[1] (source)
%2 = operand[2] (2nd source)
%s = operation size (b/w/l)
%SN = operand size [N] (N=0,1,2)
%aN = op[N] as an address (N=0,1,2)
Register numbers 0..15 are general registers. 16..31 are control
registers. 32..47 are condition codes. */
int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);

154
contrib/toolchain/binutils/include/opcode/s390.h Normal file
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/* s390.h -- Header file for S390 opcode table
Copyright 2000, 2001, 2003, 2010 Free Software Foundation, Inc.
Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef S390_H
#define S390_H
/* List of instruction sets variations. */
enum s390_opcode_mode_val
{
S390_OPCODE_ESA = 0,
S390_OPCODE_ZARCH
};
enum s390_opcode_cpu_val
{
S390_OPCODE_G5 = 0,
S390_OPCODE_G6,
S390_OPCODE_Z900,
S390_OPCODE_Z990,
S390_OPCODE_Z9_109,
S390_OPCODE_Z9_EC,
S390_OPCODE_Z10,
S390_OPCODE_Z196,
S390_OPCODE_ZEC12,
S390_OPCODE_MAXCPU
};
/* The opcode table is an array of struct s390_opcode. */
struct s390_opcode
{
/* The opcode name. */
const char * name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned char opcode[6];
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned char mask[6];
/* The opcode length in bytes. */
int oplen;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[6];
/* Bitmask of execution modes this opcode is available for. */
unsigned int modes;
/* First cpu this opcode is available for. */
enum s390_opcode_cpu_val min_cpu;
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct s390_opcode s390_opcodes[];
extern const int s390_num_opcodes;
/* A opcode format table for the .insn pseudo mnemonic. */
extern const struct s390_opcode s390_opformats[];
extern const int s390_num_opformats;
/* Values defined for the flags field of a struct powerpc_opcode. */
/* The operands table is an array of struct s390_operand. */
struct s390_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* One bit syntax flags. */
unsigned long flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the powerpc_opcodes table. */
extern const struct s390_operand s390_operands[];
/* Values defined for the flags field of a struct s390_operand. */
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define S390_OPERAND_GPR 0x1
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define S390_OPERAND_FPR 0x2
/* This operand names an access register. The disassembler
prints these with a leading 'a'. */
#define S390_OPERAND_AR 0x4
/* This operand names a control register. The disassembler
prints these with a leading 'c'. */
#define S390_OPERAND_CR 0x8
/* This operand is a displacement. */
#define S390_OPERAND_DISP 0x10
/* This operand names a base register. */
#define S390_OPERAND_BASE 0x20
/* This operand names an index register, it can be skipped. */
#define S390_OPERAND_INDEX 0x40
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define S390_OPERAND_PCREL 0x80
/* This operand takes signed values. */
#define S390_OPERAND_SIGNED 0x100
/* This operand is a length. */
#define S390_OPERAND_LENGTH 0x200
/* This operand is optional. Only a single operand at the end of
the instruction may be optional. */
#define S390_OPERAND_OPTIONAL 0x400
/* The operand needs to be a valid GP or FP register pair. */
#define S390_OPERAND_REG_PAIR 0x800
#endif /* S390_H */

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/* score-datadep.h -- Score Instructions data dependency table
Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING3. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifndef SCORE_DATA_DEPENDENCY_H
#define SCORE_DATA_DEPENDENCY_H
#define INSN_NAME_LEN 16
enum insn_type_for_dependency
{
D_mtcr,
D_all_insn
};
struct insn_to_dependency
{
char *insn_name;
enum insn_type_for_dependency type;
};
struct data_dependency
{
enum insn_type_for_dependency pre_insn_type;
char pre_reg[6];
enum insn_type_for_dependency cur_insn_type;
char cur_reg[6];
int bubblenum_7;
int bubblenum_3;
int warn_or_error; /* warning - 0; error - 1 */
};
static const struct insn_to_dependency insn_to_dependency_table[] =
{
/* move spectial instruction. */
{"mtcr", D_mtcr},
};
static const struct data_dependency data_dependency_table[] =
{
/* Status regiser. */
{D_mtcr, "cr0", D_all_insn, "", 5, 1, 0},
};
#endif

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/* score-inst.h -- Score Instructions Table
Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
Contributed by:
Brain.lin (brain.lin@sunplusct.com)
Mei Ligang (ligang@sunnorth.com.cn)
Pei-Lin Tsai (pltsai@sunplus.com)
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING3. If not, write to the Free
Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef SCORE_INST_H
#define SCORE_INST_H
#define LDST_UNALIGN_MASK 0x0000007f
#define UA_LCB 0x00000060
#define UA_LCW 0x00000062
#define UA_LCE 0x00000066
#define UA_SCB 0x00000068
#define UA_SCW 0x0000006a
#define UA_SCE 0x0000006e
#define UA_LL 0x0000000c
#define UA_SC 0x0000000e
#define LDST16_RR_MASK 0x0000000f
#define N16_LW 8
#define N16_LH 9
#define N16_POP 10
#define N16_LBU 11
#define N16_SW 12
#define N16_SH 13
#define N16_PUSH 14
#define N16_SB 15
#define LDST16_RI_MASK 0x7007
#define N16_LWP 0x7000
#define N16_LHP 0x7001
#define N16_LBUP 0x7003
#define N16_SWP 0x7004
#define N16_SHP 0x7005
#define N16_SBP 0x7007
#define N16_LIU 0x5000
#define OPC_PSEUDOLDST_MASK 0x00000007
enum
{
INSN_LW = 0,
INSN_LH = 1,
INSN_LHU = 2,
INSN_LB = 3,
INSN_SW = 4,
INSN_SH = 5,
INSN_LBU = 6,
INSN_SB = 7,
};
/* Sub opcdoe opcode. */
enum
{
INSN16_LBU = 11,
INSN16_LH = 9,
INSN16_LW = 8,
INSN16_SB = 15,
INSN16_SH = 13,
INSN16_SW = 12,
};
enum
{
LDST_NOUPDATE = 0,
LDST_PRE = 1,
LDST_POST = 2,
};
enum score_insn_type
{
Rd_I4,
Rd_I5,
Rd_rvalueBP_I5,
Rd_lvalueBP_I5,
Rd_Rs_I5,
x_Rs_I5,
x_I5_x,
Rd_I8,
Rd_Rs_I14,
I15,
Rd_I16,
Rd_I30,
Rd_I32,
Rd_rvalueRs_SI10,
Rd_lvalueRs_SI10,
Rd_rvalueRs_preSI12,
Rd_rvalueRs_postSI12,
Rd_lvalueRs_preSI12,
Rd_lvalueRs_postSI12,
Rd_Rs_SI14,
Rd_rvalueRs_SI15,
Rd_lvalueRs_SI15,
Rd_SI5,
Rd_SI6,
Rd_SI16,
PC_DISP8div2,
PC_DISP11div2,
PC_DISP19div2,
PC_DISP24div2,
Rd_Rs_Rs,
x_Rs_x,
x_Rs_Rs,
Rd_Rs_x,
Rd_x_Rs,
Rd_x_x,
Rd_Rs,
Rd_HighRs,
Rd_lvalueRs,
Rd_rvalueRs,
Rd_lvalue32Rs,
Rd_rvalue32Rs,
x_Rs,
NO_OPD,
NO16_OPD,
OP5_rvalueRs_SI15,
I5_Rs_Rs_I5_OP5,
x_rvalueRs_post4,
Rd_rvalueRs_post4,
Rd_x_I5,
Rd_lvalueRs_post4,
x_lvalueRs_post4,
Rd_LowRs,
Rd_Rs_Rs_imm,
Insn_Type_PCE,
Insn_Type_SYN,
Insn_GP,
Insn_PIC,
Insn_internal,
Insn_BCMP,
Ra_I9_I5,
};
enum score_data_type
{
_IMM4 = 0,
_IMM5,
_IMM8,
_IMM14,
_IMM15,
_IMM16,
_SIMM10 = 6,
_SIMM12,
_SIMM14,
_SIMM15,
_SIMM16,
_SIMM14_NEG = 11,
_IMM16_NEG,
_SIMM16_NEG,
_IMM20,
_IMM25,
_DISP8div2 = 16,
_DISP11div2,
_DISP19div2,
_DISP24div2,
_VALUE,
_VALUE_HI16,
_VALUE_LO16,
_VALUE_LDST_LO16 = 23,
_SIMM16_LA,
_IMM5_RSHIFT_1,
_IMM5_RSHIFT_2,
_SIMM16_LA_POS,
_IMM5_RANGE_8_31,
_IMM10_RSHIFT_2,
_GP_IMM15 = 30,
_GP_IMM14 = 31,
_SIMM16_pic = 42, /* Index in score_df_range. */
_IMM16_LO16_pic = 43,
_IMM16_pic = 44,
_SIMM5 = 45,
_SIMM6 = 46,
_IMM32 = 47,
_SIMM32 = 48,
_IMM11 = 49,
_IMM5_MULTI_LOAD = 50,
};
#define REG_TMP 1
#define OP_REG_TYPE (1 << 6)
#define OP_IMM_TYPE (1 << 7)
#define OP_SH_REGD (OP_REG_TYPE |20)
#define OP_SH_REGS1 (OP_REG_TYPE |15)
#define OP_SH_REGS2 (OP_REG_TYPE |10)
#define OP_SH_I (OP_IMM_TYPE | 1)
#define OP_SH_RI15 (OP_IMM_TYPE | 0)
#define OP_SH_I12 (OP_IMM_TYPE | 3)
#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
#define OP_SH_I5 (OP_IMM_TYPE |10)
#define OP_SH_I10 (OP_IMM_TYPE | 5)
#define OP_SH_COPID (OP_IMM_TYPE | 5)
#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
#define OP_SH_I15 (OP_IMM_TYPE |10)
#define OP16_SH_REGD (OP_REG_TYPE | 8)
#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
#define OP16_SH_I45 (OP_IMM_TYPE | 3)
#define OP16_SH_I8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
enum insn_class
{
INSN_CLASS_16,
INSN_CLASS_32,
INSN_CLASS_48,
INSN_CLASS_PCE,
INSN_CLASS_SYN
};
/* s3_s7: Globals for both tc-score.c and elf32-score.c. */
extern int score3;
extern int score7;
#endif

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/* Definitions for opcode table for the sparc.
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
2003, 2005, 2010, 2011 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
the GNU Binutils.
GAS/GDB is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS/GDB is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#include "ansidecl.h"
/* The SPARC opcode table (and other related data) is defined in
the opcodes library in sparc-opc.c. If you change anything here, make
sure you fix up that file, and vice versa. */
/* FIXME-someday: perhaps the ,a's and such should be embedded in the
instruction's name rather than the args. This would make gas faster, pinsn
slower, but would mess up some macros a bit. xoxorich. */
/* List of instruction sets variations.
These values are such that each element is either a superset of a
preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
returns non-zero.
The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
Don't change this without updating sparc-opc.c. */
enum sparc_opcode_arch_val
{
SPARC_OPCODE_ARCH_V6 = 0,
SPARC_OPCODE_ARCH_V7,
SPARC_OPCODE_ARCH_V8,
SPARC_OPCODE_ARCH_LEON,
SPARC_OPCODE_ARCH_SPARCLET,
SPARC_OPCODE_ARCH_SPARCLITE,
/* V9 variants must appear last. */
SPARC_OPCODE_ARCH_V9,
SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
};
/* The highest architecture in the table. */
#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
insn encoding/decoding. */
#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
/* Table of cpu variants. */
typedef struct sparc_opcode_arch
{
const char *name;
/* Mask of sparc_opcode_arch_val's supported.
EG: For v7 this would be
(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
These are short's because sparc_opcode.architecture is. */
short supported;
} sparc_opcode_arch;
extern const struct sparc_opcode_arch sparc_opcode_archs[];
/* Given architecture name, look up it's sparc_opcode_arch_val value. */
extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
/* Return the bitmask of supported architectures for ARCH. */
#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
/* Non-zero if ARCH1 conflicts with ARCH2.
IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
!= SPARC_OPCODE_SUPPORTED (ARCH2)))
/* Structure of an opcode table entry. */
typedef struct sparc_opcode
{
const char *name;
unsigned long match; /* Bits that must be set. */
unsigned long lose; /* Bits that must not be set. */
const char *args;
/* This was called "delayed" in versions before the flags. */
unsigned int flags;
unsigned int hwcaps;
short architecture; /* Bitmask of sparc_opcode_arch_val's. */
} sparc_opcode;
/* FIXME: Add F_ANACHRONISTIC flag for v9. */
#define F_DELAYED 0x00000001 /* Delayed branch. */
#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */
#define F_UNBR 0x00000004 /* Unconditional branch. */
#define F_CONDBR 0x00000008 /* Conditional branch. */
#define F_JSR 0x00000010 /* Subroutine call. */
#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
#define F_FBR 0x00000040 /* Floating point branch. */
#define F_PREFERRED 0x00000080 /* A preferred alias. */
#define F_PREF_ALIAS (F_ALIAS|F_PREFERRED)
/* These must match the HWCAP_* values precisely. */
#define HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
#define HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
#define HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
#define HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
#define HWCAP_POPC 0x00000010 /* 'popc' insn */
#define HWCAP_VIS 0x00000020 /* VIS insns */
#define HWCAP_VIS2 0x00000040 /* VIS2 insns */
#define HWCAP_ASI_BLK_INIT \
0x00000080 /* block init ASIs */
#define HWCAP_FMAF 0x00000100 /* fused multiply-add */
#define HWCAP_VIS3 0x00000400 /* VIS3 insns */
#define HWCAP_HPC 0x00000800 /* HPC insns */
#define HWCAP_RANDOM 0x00001000 /* 'random' insn */
#define HWCAP_TRANS 0x00002000 /* transaction insns */
#define HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
#define HWCAP_IMA 0x00008000 /* integer multiply-add */
#define HWCAP_ASI_CACHE_SPARING \
0x00010000 /* cache sparing ASIs */
#define HWCAP_AES 0x00020000 /* AES crypto insns */
#define HWCAP_DES 0x00040000 /* DES crypto insns */
#define HWCAP_KASUMI 0x00080000 /* KASUMI crypto insns */
#define HWCAP_CAMELLIA 0x00100000 /* CAMELLIA crypto insns */
#define HWCAP_MD5 0x00200000 /* MD5 hashing insns */
#define HWCAP_SHA1 0x00400000 /* SHA1 hashing insns */
#define HWCAP_SHA256 0x00800000 /* SHA256 hashing insns */
#define HWCAP_SHA512 0x01000000 /* SHA512 hashing insns */
#define HWCAP_MPMUL 0x02000000 /* Multiple Precision Multiply */
#define HWCAP_MONT 0x04000000 /* Montgomery Mult/Sqrt */
#define HWCAP_PAUSE 0x08000000 /* Pause insn */
#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
The match component is a mask saying which bits must match a particular
opcode in order for an instruction to be an instance of that opcode.
The args component is a string containing one character for each operand of the
instruction.
Kinds of operands:
# Number used by optimizer. It is ignored.
1 rs1 register.
2 rs2 register.
d rd register.
e frs1 floating point register.
v frs1 floating point register (double/even).
V frs1 floating point register (quad/multiple of 4).
f frs2 floating point register.
B frs2 floating point register (double/even).
R frs2 floating point register (quad/multiple of 4).
4 frs3 floating point register.
5 frs3 floating point register (doube/even).
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
m alternate space register (asr) in rd
M alternate space register (asr) in rs1
h 22 high bits.
X 5 bit unsigned immediate
Y 6 bit unsigned immediate
3 SIAM mode (3 bits). (v9b)
K MEMBAR mask (7 bits). (v9)
j 10 bit Immediate. (v9)
I 11 bit Immediate. (v9)
i 13 bit Immediate.
n 22 bit immediate.
k 2+14 bit PC relative immediate. (v9)
G 19 bit PC relative immediate. (v9)
l 22 bit PC relative immediate.
L 30 bit PC relative immediate.
a Annul. The annul bit is set.
A Alternate address space. Stored as 8 bits.
C Coprocessor state register.
F floating point state register.
p Processor state register.
N Branch predict clear ",pn" (v9)
T Branch predict set ",pt" (v9)
z %icc. (v9)
Z %xcc. (v9)
q Floating point queue.
r Single register that is both rs1 and rd.
O Single register that is both rs2 and rd.
Q Coprocessor queue.
S Special case.
t Trap base register.
w Window invalid mask register.
y Y register.
u sparclet coprocessor registers in rd position
U sparclet coprocessor registers in rs1 position
E %ccr. (v9)
s %fprs. (v9)
P %pc. (v9)
W %tick. (v9)
o %asi. (v9)
6 %fcc0. (v9)
7 %fcc1. (v9)
8 %fcc2. (v9)
9 %fcc3. (v9)
! Privileged Register in rd (v9)
? Privileged Register in rs1 (v9)
* Prefetch function constant. (v9)
x OPF field (v9 impdep).
0 32/64 bit immediate for set or setx (v9) insns
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
( entire floating point state register (%efsr)
) 5 bit immediate placed in RS3 field
= 2+8 bit PC relative immediate. (v9) */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
#define F1(x) (OP (x))
#define DISP30(x) ((x) & 0x3fffffff)
#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
#define ASI_RS2(x) (SIMM13 (x))
#define MEMBAR(x) ((x) & 0x7f)
#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
#define ANNUL (1 << 29)
#define BPRED (1 << 19) /* V9. */
#define IMMED F3I (1)
#define RD_G0 RD (~0)
#define RS1_G0 RS1 (~0)
#define RS2_G0 RS2 (~0)
extern const struct sparc_opcode sparc_opcodes[];
extern const int sparc_num_opcodes;
extern int sparc_encode_asi (const char *);
extern const char *sparc_decode_asi (int);
extern int sparc_encode_membar (const char *);
extern const char *sparc_decode_membar (int);
extern int sparc_encode_prefetch (const char *);
extern const char *sparc_decode_prefetch (int);
extern int sparc_encode_sparclet_cpreg (const char *);
extern const char *sparc_decode_sparclet_cpreg (int);
/* Local Variables:
fill-column: 131
comment-column: 0
End: */

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contrib/toolchain/binutils/include/opcode/spu-insns.h Normal file
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/* SPU ELF support for BFD.
Copyright 2006, 2007, 2010 Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* SPU Opcode Table
-=-=-= FORMAT =-=-=-
+----+-------+-------+-------+-------+ +------------+-------+-------+-------+
RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT |
+----+-------+-------+-------+-------+ +------------+-------+-------+-------+
0 3 1 1 2 3 0 1 1 2 3
0 7 4 1 0 7 4 1
+-----------+--------+-------+-------+ +---------+----------+-------+-------+
RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT |
+-----------+--------+-------+-------+ +---------+----------+-------+-------+
0 9 1 2 3 0 7 1 2 3
7 4 1 7 4 1
+----------+-----------------+-------+ +--------+-------------------+-------+
RI16 | op | I16 | RT | RI18 | op | I18 | RT |
+----------+-----------------+-------+ +--------+-------------------+-------+
0 8 2 3 0 6 2 3
4 1 4 1
+------------+-------+-------+-------+ +-------+--+-----------------+-------+
RR | op | RB | RA | RT | LBT | op |RO| I16 | RO |
+------------+-------+-------+-------+ +-------+--+-----------------+-------+
0 1 1 2 3 0 6 8 2 3
0 7 4 1 4 1
+------------+----+--+-------+-------+
LBTI | op | // |RO| RA | RO |
+------------+----+--+-------+-------+
0 1 1 1 2 3
0 5 7 4 1
-=-=-= OPCODE =-=-=-
OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this
case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700,
since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000.
-=-=-= ASM_FORMAT =-=-=-
RRR category RI7 category
ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4
ASM_RI7 mnemonic RT, RA, I7
RI8 category RI10 category
ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10
ASM_RI10 mnemonic RT, RA, R10
ASM_RI10IDX mnemonic RT, I10(RA)
RI16 category RI18 category
ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18
ASM_RI16 mnemonic RT, I16
ASM_RI16W mnemonic RT, I16W
RR category LBT category
ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg
ASM_MTSPR mnemonic SA, RT
ASM_NOOP mnemonic LBTI category
ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA
ASM_RAB mnemonic RA, RB
ASM_RDCH mnemonic RT, CA
ASM_RR mnemonic RT, RA, RB
ASM_RT mnemonic RT
ASM_RTA mnemonic RT, RA
ASM_WRCH mnemonic CA, RT
Note that RRR instructions have the names for RC and RT reversed from
what's in the ISA, in order to put RT in the same position it appears
for other formats.
-=-=-= DEPENDENCY =-=-=-
DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target.
The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits.
If the digit is 0, this means the corresponding register is not used in the instruction.
If the digit is 1, this means the corresponding register is used as a source in the instruction.
If the digit is 2, this means the corresponding register is used as a target in the instruction.
If the digit is 3, this means the corresponding register is used as both source and target in the instruction.
For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are
used as sources and RT is the target.
-=-=-= PIPE =-=-=-
This field shows which execution pipe is used for the instruction
pipe0 execution pipelines:
FP6 SP floating pipeline
FP7 integer operations executed in SP floating pipeline
FPD DP floating pipeline
FX2 FXU pipeline
FX3 Rotate/Shift pipeline
FXB Byte pipeline
NOP No pipeline
pipe1 execution pipelines:
BR Branch pipeline
LNOP No pipeline
LS Load/Store pipeline
SHUF Shuffle pipeline
SPR SPR/CH pipeline
*/
#define _A0() {0}
#define _A1(a) {1,a}
#define _A2(a,b) {2,a,b}
#define _A3(a,b,c) {3,a,b,c}
#define _A4(a,b,c,d) {4,a,b,c,d}
/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */
/* 0[RC][RB][RA][RT] */
/* 1:src, 2:target */
APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */
APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */
APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */
APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */
APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */
APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */
APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */
APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */
APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */
APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */
APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */
APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */
APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */
APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */
APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */
APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */
APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */
APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */
APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */
APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */
APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */
APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */
APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */
APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */
APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */
APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */
APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */
APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */
APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */
APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */
APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */
APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */
APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */
APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */
APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */
APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */
APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */
APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */
APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */
APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */
APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */
APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */
APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */
APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */
APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */
APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */
APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */
APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */
APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */
APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */
APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */
APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */
APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */
APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */
APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */
APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */
APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */
APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */
APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */
APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */
APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */
APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */
APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */
APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */
APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */
APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */
APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */
APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */
APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */
APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */
APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */
APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */
APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */
APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */
APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */
APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */
APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */
APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */
APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */
APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */
APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */
APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */
APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */
APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */
APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */
APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */
APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */
APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */
APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */
APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */
APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */
APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */
APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */
APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */
APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */
APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */
APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */
APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */
APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */
APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */
APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */
APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */
APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */
APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */
APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */
APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */
APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */
APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */
APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */
APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */
APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */
APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */
APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */
APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */
APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */
APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */
APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */
APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */
APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */
APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */
APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */
APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */
APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */
APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */
APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */
APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */
/* for system function call, this uses op-code of mtspr */
APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
/*
pseudo instruction:
system call
value of I9 operation
0 halt
1 rt[0] = open(MEM[ra[0]], ra[1])
2 rt[0] = close(ra[0])
3 rt[0] = read(ra[0], MEM[ra[1]], ra[2])
4 rt[0] = write(ra[0], MEM[ra[1]], ra[2])
5 printf(MEM[ra[0]], ra[1], ra[2], ra[3])
42 rt[0] = clock()
52 rt[0] = lseek(ra0, ra1, ra2)
*/
/* new multiprecision add/sub */
APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
/*
The following ops are a subset of above except with feature bits set.
Feature bits are bits 11-17 of the instruction:
11 - C & P feature bit
12 - disable interrupts
13 - enable interrupts
*/
APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */
APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */
APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */
APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */
APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */
APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */
APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */
/* Synonyms required by the AS manual. */
APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */
APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
/* New soma double-float insns. */
APUOP(M_DFCEQ, RR, 0x3c3, "dfceq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCEQ RT<-(RA=RB) */
APUOP(M_DFCMEQ, RR, 0x3cb, "dfcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMEQ RT<-(|RA|=|RB|) */
APUOP(M_DFCGT, RR, 0x2c3, "dfcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCGT RT<-(RA>RB) */
APUOP(M_DFCMGT, RR, 0x2cb, "dfcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMGT RT<-(|RA|>|RB|) */
APUOP(M_DFTSV, RI7, 0x3bf, "dftsv", _A3(A_T,A_A,A_U7), 00012, FX2) /* DFTSV RT<-testspecial(RA,I7) */
#undef _A0
#undef _A1
#undef _A2
#undef _A3
#undef _A4

125
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/* SPU ELF support for BFD.
Copyright 2006, 2010 Free Software Foundation, Inc.
This file is part of GDB, GAS, and the GNU binutils.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* These two enums are from rel_apu/common/spu_asm_format.h */
/* definition of instruction format */
typedef enum {
RRR,
RI18,
RI16,
RI10,
RI8,
RI7,
RR,
LBT,
LBTI,
IDATA,
UNKNOWN_IFORMAT
} spu_iformat;
/* These values describe assembly instruction arguments. They indicate
* how to encode, range checking and which relocation to use. */
typedef enum {
A_T, /* register at pos 0 */
A_A, /* register at pos 7 */
A_B, /* register at pos 14 */
A_C, /* register at pos 21 */
A_S, /* special purpose register at pos 7 */
A_H, /* channel register at pos 7 */
A_P, /* parenthesis, this has to separate regs from immediates */
A_S3,
A_S6,
A_S7N,
A_S7,
A_U7A,
A_U7B,
A_S10B,
A_S10,
A_S11,
A_S11I,
A_S14,
A_S16,
A_S18,
A_R18,
A_U3,
A_U5,
A_U6,
A_U7,
A_U14,
A_X16,
A_U18,
A_MAX
} spu_aformat;
enum spu_insns {
#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
TAG,
#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
TAG,
#include "opcode/spu-insns.h"
#undef APUOP
#undef APUOPFB
M_SPU_MAX
};
struct spu_opcode
{
spu_iformat insn_type;
unsigned int opcode;
char *mnemonic;
int arg[5];
};
#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))
#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))
#define DECODE_INSN_RT(insn) (insn & 0x7f)
#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)
#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)
#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)
#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)
#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)
/* For branching, immediate loads, hbr and lqa/stqa. */
#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)
#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)
/* for stop */
#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)
/* For ila */
#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)
#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)
/* For rotate and shift and generate control mask */
#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)
#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)
/* For float <-> int conversion */
#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14)
#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)
/* For hbr */
#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))
#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))
#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))

232
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/*
* Ported by the State University of New York at Buffalo by the Distributed
* Computer Systems Lab, Department of Computer Science, 1991.
*/
/* Copyright 2012 Free Software Foundation, Inc.
This file is part of GDB and BINUTILS.
GDB and BINUTILS are free software; you can redistribute them and/or
modify them under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3, or (at
your option) any later version.
GDB and BINUTILS are distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB or BINUTILS; see the file COPYING3. If not, write
to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifndef tahoe_opcodeT
#define tahoe_opcodeT int
#endif /* no tahoe_opcodeT */
struct vot_wot /* tahoe opcode table: wot to do with this */
/* particular opcode */
{
char * args; /* how to compile said opcode */
tahoe_opcodeT code; /* op-code (may be > 8 bits!) */
};
struct vot /* tahoe opcode text */
{
char * name; /* opcode name: lowercase string [key] */
struct vot_wot detail; /* rest of opcode table [datum] */
};
#define vot_how args
#define vot_code code
#define vot_detail detail
#define vot_name name
static struct vot
votstrs[] =
{
{ "halt", {"", 0x00 } },
{ "sinf", {"", 0x05 } },
{ "ldf", {"rl", 0x06 } },
{ "ldd", {"rq", 0x07 } },
{ "addb2", {"rbmb", 0x08 } },
{ "movb", {"rbwb", 0x09 } },
{ "addw2", {"rwmw", 0x0a } },
{ "movw", {"rwww", 0x0b } },
{ "addl2", {"rlml", 0x0c } },
{ "movl", {"rlwl", 0x0d } },
{ "bbs", {"rlvlbw", 0x0e } },
{ "nop", {"", 0x10 } },
{ "brb", {"bb", 0x11 } },
{ "brw", {"bw", 0x13 } },
{ "cosf", {"", 0x15 } },
{ "lnf", {"rl", 0x16 } },
{ "lnd", {"rq", 0x17 } },
{ "addb3", {"rbrbwb", 0x18 } },
{ "cmpb", {"rbwb", 0x19 } },
{ "addw3", {"rwrwww", 0x1a } },
{ "cmpw", {"rwww", 0x1b } },
{ "addl3", {"rlrlwl", 0x1c } },
{ "cmpl", {"rlwl", 0x1d } },
{ "bbc", {"rlvlbw", 0x1e } },
{ "rei", {"", 0x20 } },
{ "bneq", {"bb", 0x21 } },
{ "bnequ", {"bb", 0x21 } },
{ "cvtwl", {"rwwl", 0x23 } },
{ "stf", {"wl", 0x26 } },
{ "std", {"wq", 0x27 } },
{ "subb2", {"rbmb", 0x28 } },
{ "mcomb", {"rbwb", 0x29 } },
{ "subw2", {"rwmw", 0x2a } },
{ "mcomw", {"rwww", 0x2b } },
{ "subl2", {"rlml", 0x2c } },
{ "mcoml", {"rlwl", 0x2d } },
{ "emul", {"rlrlrlwq", 0x2e } },
{ "aoblss", {"rlmlbw", 0x2f } },
{ "bpt", {"", 0x30 } },
{ "beql", {"bb", 0x31 } },
{ "beqlu", {"bb", 0x31 } },
{ "cvtwb", {"rwwb", 0x33 } },
{ "logf", {"", 0x35 } },
{ "cmpf", {"rl", 0x36 } },
{ "cmpd", {"rq", 0x37 } },
{ "subb3", {"rbrbwb", 0x38 } },
{ "bitb", {"rbrb", 0x39 } },
{ "subw3", {"rwrwww", 0x3a } },
{ "bitw", {"rwrw", 0x3b } },
{ "subl3", {"rlrlwl", 0x3c } },
{ "bitl", {"rlrl", 0x3d } },
{ "ediv", {"rlrqwlwl", 0x3e } },
{ "aobleq", {"rlmlbw", 0x3f } },
{ "ret", {"", 0x40 } },
{ "bgtr", {"bb", 0x41 } },
{ "sqrtf", {"", 0x45 } },
{ "cmpf2", {"rl", 0x46 } },
{ "cmpd2", {"rqrq", 0x47 } },
{ "shll", {"rbrlwl", 0x48 } },
{ "clrb", {"wb", 0x49 } },
{ "shlq", {"rbrqwq", 0x4a } },
{ "clrw", {"ww", 0x4b } },
{ "mull2", {"rlml", 0x4c } },
{ "clrl", {"wl", 0x4d } },
{ "shal", {"rbrlwl", 0x4e } },
{ "bleq", {"bb", 0x51 } },
{ "expf", {"", 0x55 } },
{ "tstf", {"", 0x56 } },
{ "tstd", {"", 0x57 } },
{ "shrl", {"rbrlwl", 0x58 } },
{ "tstb", {"rb", 0x59 } },
{ "shrq", {"rbrqwq", 0x5a } },
{ "tstw", {"rw", 0x5b } },
{ "mull3", {"rlrlwl", 0x5c } },
{ "tstl", {"rl", 0x5d } },
{ "shar", {"rbrlwl", 0x5e } },
{ "bbssi", {"rlmlbw", 0x5f } },
{ "ldpctx", {"", 0x60 } },
{ "pushd", {"", 0x67 } },
{ "incb", {"mb", 0x69 } },
{ "incw", {"mw", 0x6b } },
{ "divl2", {"rlml", 0x6c } },
{ "incl", {"ml", 0x6d } },
{ "cvtlb", {"rlwb", 0x6f } },
{ "svpctx", {"", 0x70 } },
{ "jmp", {"ab", 0x71 } },
{ "cvlf", {"rl", 0x76 } },
{ "cvld", {"rl", 0x77 } },
{ "decb", {"mb", 0x79 } },
{ "decw", {"mw", 0x7b } },
{ "divl3", {"rlrlwl", 0x7c } },
{ "decl", {"ml", 0x7d } },
{ "cvtlw", {"rlww", 0x7f } },
{ "bgeq", {"bb", 0x81 } },
{ "movs2", {"abab", 0x82 } },
{ "cvfl", {"wl", 0x86 } },
{ "cvdl", {"wl", 0x87 } },
{ "orb2", {"rbmb", 0x88 } },
{ "cvtbl", {"rbwl", 0x89 } },
{ "orw2", {"rwmw", 0x8a } },
{ "bispsw", {"rw", 0x8b } },
{ "orl2", {"rlml", 0x8c } },
{ "adwc", {"rlml", 0x8d } },
{ "adda", {"rlml", 0x8e } },
{ "blss", {"bb", 0x91 } },
{ "cmps2", {"abab", 0x92 } },
{ "ldfd", {"rl", 0x97 } },
{ "orb3", {"rbrbwb", 0x98 } },
{ "cvtbw", {"rbww", 0x99 } },
{ "orw3", {"rwrwww", 0x9a } },
{ "bicpsw", {"rw", 0x9b } },
{ "orl3", {"rlrlwl", 0x9c } },
{ "sbwc", {"rlml", 0x9d } },
{ "suba", {"rlml", 0x9e } },
{ "bgtru", {"bb", 0xa1 } },
{ "cvdf", {"", 0xa6 } },
{ "andb2", {"rbmb", 0xa8 } },
{ "movzbl", {"rbwl", 0xa9 } },
{ "andw2", {"rwmw", 0xaa } },
{ "loadr", {"rwal", 0xab } },
{ "andl2", {"rlml", 0xac } },
{ "mtpr", {"rlrl", 0xad } },
{ "ffs", {"rlwl", 0xae } },
{ "blequ", {"bb", 0xb1 } },
{ "negf", {"", 0xb6 } },
{ "negd", {"", 0xb7 } },
{ "andb3", {"rbrbwb", 0xb8 } },
{ "movzbw", {"rbww", 0xb9 } },
{ "andw3", {"rwrwww", 0xba } },
{ "storer", {"rwal", 0xbb } },
{ "andl3", {"rlrlwl", 0xbc } },
{ "mfpr", {"rlwl", 0xbd } },
{ "ffc", {"rlwl", 0xbe } },
{ "calls", {"rbab", 0xbf } },
{ "prober", {"rbabrl", 0xc0 } },
{ "bvc", {"bb", 0xc1 } },
{ "movs3", {"ababrw", 0xc2 } },
{ "movzwl", {"rwwl", 0xc3 } },
{ "addf", {"rl", 0xc6 } },
{ "addd", {"rq", 0xc7 } },
{ "xorb2", {"rbmb", 0xc8 } },
{ "movob", {"rbwb", 0xc9 } },
{ "xorw2", {"rwmw", 0xca } },
{ "movow", {"rwww", 0xcb } },
{ "xorl2", {"rlml", 0xcc } },
{ "movpsl", {"wl", 0xcd } },
{ "kcall", {"rw", 0xcf } },
{ "probew", {"rbabrl", 0xd0 } },
{ "bvs", {"bb", 0xd1 } },
{ "cmps3", {"ababrw", 0xd2 } },
{ "subf", {"rq", 0xd6 } },
{ "subd", {"rq", 0xd7 } },
{ "xorb3", {"rbrbwb", 0xd8 } },
{ "pushb", {"rb", 0xd9 } },
{ "xorw3", {"rwrwww", 0xda } },
{ "pushw", {"rw", 0xdb } },
{ "xorl3", {"rlrlwl", 0xdc } },
{ "pushl", {"rl", 0xdd } },
{ "insque", {"abab", 0xe0 } },
{ "bcs", {"bb", 0xe1 } },
{ "bgequ", {"bb", 0xe1 } },
{ "mulf", {"rq", 0xe6 } },
{ "muld", {"rq", 0xe7 } },
{ "mnegb", {"rbwb", 0xe8 } },
{ "movab", {"abwl", 0xe9 } },
{ "mnegw", {"rwww", 0xea } },
{ "movaw", {"awwl", 0xeb } },
{ "mnegl", {"rlwl", 0xec } },
{ "moval", {"alwl", 0xed } },
{ "remque", {"ab", 0xf0 } },
{ "bcc", {"bb", 0xf1 } },
{ "blssu", {"bb", 0xf1 } },
{ "divf", {"rq", 0xf6 } },
{ "divd", {"rq", 0xf7 } },
{ "movblk", {"alalrw", 0xf8 } },
{ "pushab", {"ab", 0xf9 } },
{ "pushaw", {"aw", 0xfb } },
{ "casel", {"rlrlrl", 0xfc } },
{ "pushal", {"al", 0xfd } },
{ "callf", {"rbab", 0xfe } },
{ "" , "" } /* empty is end sentinel */
};

691
contrib/toolchain/binutils/include/opcode/tic30.h Normal file
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/* tic30.h -- Header file for TI TMS320C30 opcode table
Copyright 1998, 2005, 2009, 2010 Free Software Foundation, Inc.
Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
header file. */
#ifndef _TMS320_H_
#define _TMS320_H_
struct _register
{
char *name;
unsigned char opcode;
unsigned char regtype;
};
typedef struct _register reg;
#define REG_Rn 0x01
#define REG_ARn 0x02
#define REG_DP 0x03
#define REG_OTHER 0x04
static const reg tic30_regtab[] = {
{ "r0", 0x00, REG_Rn },
{ "r1", 0x01, REG_Rn },
{ "r2", 0x02, REG_Rn },
{ "r3", 0x03, REG_Rn },
{ "r4", 0x04, REG_Rn },
{ "r5", 0x05, REG_Rn },
{ "r6", 0x06, REG_Rn },
{ "r7", 0x07, REG_Rn },
{ "ar0",0x08, REG_ARn },
{ "ar1",0x09, REG_ARn },
{ "ar2",0x0A, REG_ARn },
{ "ar3",0x0B, REG_ARn },
{ "ar4",0x0C, REG_ARn },
{ "ar5",0x0D, REG_ARn },
{ "ar6",0x0E, REG_ARn },
{ "ar7",0x0F, REG_ARn },
{ "dp", 0x10, REG_DP },
{ "ir0",0x11, REG_OTHER },
{ "ir1",0x12, REG_OTHER },
{ "bk", 0x13, REG_OTHER },
{ "sp", 0x14, REG_OTHER },
{ "st", 0x15, REG_OTHER },
{ "ie", 0x16, REG_OTHER },
{ "if", 0x17, REG_OTHER },
{ "iof",0x18, REG_OTHER },
{ "rs", 0x19, REG_OTHER },
{ "re", 0x1A, REG_OTHER },
{ "rc", 0x1B, REG_OTHER },
{ "R0", 0x00, REG_Rn },
{ "R1", 0x01, REG_Rn },
{ "R2", 0x02, REG_Rn },
{ "R3", 0x03, REG_Rn },
{ "R4", 0x04, REG_Rn },
{ "R5", 0x05, REG_Rn },
{ "R6", 0x06, REG_Rn },
{ "R7", 0x07, REG_Rn },
{ "AR0",0x08, REG_ARn },
{ "AR1",0x09, REG_ARn },
{ "AR2",0x0A, REG_ARn },
{ "AR3",0x0B, REG_ARn },
{ "AR4",0x0C, REG_ARn },
{ "AR5",0x0D, REG_ARn },
{ "AR6",0x0E, REG_ARn },
{ "AR7",0x0F, REG_ARn },
{ "DP", 0x10, REG_DP },
{ "IR0",0x11, REG_OTHER },
{ "IR1",0x12, REG_OTHER },
{ "BK", 0x13, REG_OTHER },
{ "SP", 0x14, REG_OTHER },
{ "ST", 0x15, REG_OTHER },
{ "IE", 0x16, REG_OTHER },
{ "IF", 0x17, REG_OTHER },
{ "IOF",0x18, REG_OTHER },
{ "RS", 0x19, REG_OTHER },
{ "RE", 0x1A, REG_OTHER },
{ "RC", 0x1B, REG_OTHER },
{ "", 0, 0 }
};
static const reg *const tic30_regtab_end
= tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);
/* Indirect Addressing Modes Modification Fields */
/* Indirect Addressing with Displacement */
#define PreDisp_Add 0x00
#define PreDisp_Sub 0x01
#define PreDisp_Add_Mod 0x02
#define PreDisp_Sub_Mod 0x03
#define PostDisp_Add_Mod 0x04
#define PostDisp_Sub_Mod 0x05
#define PostDisp_Add_Circ 0x06
#define PostDisp_Sub_Circ 0x07
/* Indirect Addressing with Index Register IR0 */
#define PreIR0_Add 0x08
#define PreIR0_Sub 0x09
#define PreIR0_Add_Mod 0x0A
#define PreIR0_Sub_Mod 0x0B
#define PostIR0_Add_Mod 0x0C
#define PostIR0_Sub_Mod 0x0D
#define PostIR0_Add_Circ 0x0E
#define PostIR0_Sub_Circ 0x0F
/* Indirect Addressing with Index Register IR1 */
#define PreIR1_Add 0x10
#define PreIR1_Sub 0x11
#define PreIR1_Add_Mod 0x12
#define PreIR1_Sub_Mod 0x13
#define PostIR1_Add_Mod 0x14
#define PostIR1_Sub_Mod 0x15
#define PostIR1_Add_Circ 0x16
#define PostIR1_Sub_Circ 0x17
/* Indirect Addressing (Special Cases) */
#define IndirectOnly 0x18
#define PostIR0_Add_BitRev 0x19
typedef struct {
char *syntax;
unsigned char modfield;
unsigned char displacement;
} ind_addr_type;
#define IMPLIED_DISP 0x01
#define DISP_REQUIRED 0x02
#define NO_DISP 0x03
static const ind_addr_type tic30_indaddr_tab[] = {
{ "*+ar", PreDisp_Add, IMPLIED_DISP },
{ "*-ar", PreDisp_Sub, IMPLIED_DISP },
{ "*++ar", PreDisp_Add_Mod, IMPLIED_DISP },
{ "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP },
{ "*ar++", PostDisp_Add_Mod, IMPLIED_DISP },
{ "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP },
{ "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP },
{ "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP },
{ "*+ar()", PreDisp_Add, DISP_REQUIRED },
{ "*-ar()", PreDisp_Sub, DISP_REQUIRED },
{ "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED },
{ "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED },
{ "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED },
{ "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED },
{ "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED },
{ "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED },
{ "*+ar(ir0)", PreIR0_Add, NO_DISP },
{ "*-ar(ir0)", PreIR0_Sub, NO_DISP },
{ "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP },
{ "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP },
{ "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP },
{ "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP },
{ "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP },
{ "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP },
{ "*+ar(ir1)", PreIR1_Add, NO_DISP },
{ "*-ar(ir1)", PreIR1_Sub, NO_DISP },
{ "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP },
{ "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP },
{ "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP },
{ "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP },
{ "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP },
{ "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP },
{ "*ar", IndirectOnly, NO_DISP },
{ "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
{ "", 0,0 }
};
static const ind_addr_type *const tic30_indaddrtab_end
= tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);
/* Possible operand types */
/* Register types */
#define Rn 0x0001
#define ARn 0x0002
#define DPReg 0x0004
#define OtherReg 0x0008
/* Addressing mode types */
#define Direct 0x0010
#define Indirect 0x0020
#define Imm16 0x0040
#define Disp 0x0080
#define Imm24 0x0100
#define Abs24 0x0200
/* 3 operand addressing mode types */
#define op3T1 0x0400
#define op3T2 0x0800
/* Interrupt vector */
#define IVector 0x1000
/* Not required */
#define NotReq 0x2000
#define GAddr1 Rn | Direct | Indirect | Imm16
#define GAddr2 GAddr1 | AllReg
#define TAddr1 op3T1 | Rn | Indirect
#define TAddr2 op3T2 | Rn | Indirect
#define Reg Rn | ARn
#define AllReg Reg | DPReg | OtherReg
typedef struct _template
{
char *name;
unsigned int operands; /* how many operands */
unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
the same instruction */
unsigned int opcode_modifier;
/* opcode_modifier bits: */
#define AddressMode 0x00600000
#define PCRel 0x02000000
#define StackOp 0x001F0000
#define Rotate StackOp
/* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g.
'operand_types[i] = Reg|Imm' specifies that operand i can be
either a register or an immediate operand */
unsigned int operand_types[3];
/* This defines the number type of an immediate argument to an instruction. */
int imm_arg_type;
#define Imm_None 0
#define Imm_Float 1
#define Imm_SInt 2
#define Imm_UInt 3
}
insn_template;
static const insn_template tic30_optab[] = {
{ "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
{ "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
{ "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt },
{ "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt },
{ "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt },
{ "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt },
{ "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None },
{ "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
{ "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None },
{ "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float },
{ "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt },
{ "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None },
{ "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None },
{ "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */
{ "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None },
{ "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None },
{ "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt },
{ "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */
{ "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */
{ "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
{ "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None },
{ "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/
{ "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None },
{ "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None },
{ "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None },
{ "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None },
{ "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None },
{ "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None },
{ "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None },
{ "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None },
{ "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None },
{ "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None },
{ "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None },
{ "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None },
{ "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None },
{ "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None },
{ "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None },
{ "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None },
{ "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None },
{ "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None },
{ "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None },
{ "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None },
{ "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None },
{ "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None },
{ "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None },
{ "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None },
{ "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None },
{ "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None },
{ "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None },
{ "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None },
{ "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None },
{ "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None },
{ "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None },
{ "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None },
{ "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None },
{ "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None },
{ "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None },
{ "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None },
{ "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None },
{ "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None },
{ "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None },
{ "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None },
{ "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None },
{ "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None },
{ "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None },
{ "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None },
{ "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None },
{ "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None },
{ "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None },
{ "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None },
{ "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None },
{ "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None },
{ "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None },
{ "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None },
{ "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None },
{ "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None },
{ "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None },
{ "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None },
{ "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None },
{ "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None },
{ "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None },
{ "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None },
{ "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None },
{ "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None },
{ "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None },
{ "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None },
{ "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt },
{ "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt },
{ "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None },
{ "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
{ "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
{ "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
{ "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
{ "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
{ "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
{ "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
{ "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None },
{ "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None },
{ "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None },
{ "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None },
{ "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None },
{ "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None },
{ "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None },
{ "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None },
{ "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None },
{ "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None },
{ "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None },
{ "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None },
{ "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None },
{ "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None },
{ "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None },
{ "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None },
{ "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None },
{ "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None },
{ "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None },
{ "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None },
{ "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None },
{ "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None },
{ "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None },
{ "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
{ "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
{ "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
{ "" ,0,0x00000000,0, { 0, 0, 0 }, 0 }
};
static const insn_template *const tic30_optab_end =
tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
typedef struct {
char *name;
unsigned int operands_1;
unsigned int operands_2;
unsigned int base_opcode;
unsigned int operand_types[2][3];
/* Which operand fits into which part of the final opcode word. */
int oporder;
} partemplate;
/* oporder defines - not very descriptive. */
#define OO_4op1 0
#define OO_4op2 1
#define OO_4op3 2
#define OO_5op1 3
#define OO_5op2 4
#define OO_PField 5
static const partemplate tic30_paroptab[] = {
{ "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
OO_5op2 },
{ "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
OO_4op2 },
{ "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
OO_4op2 },
{ "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
OO_5op2 },
{ "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn },
{ Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
{ "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn },
{ Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
{ "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn },
{ Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
{ "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn },
{ Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
{ "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
OO_4op1 },
{ "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
OO_4op3 },
{ "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
OO_4op3 },
{ "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
OO_5op2 },
{ "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
OO_5op2 },
{ "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
OO_5op1 },
{ "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 }
};
static const partemplate *const tic30_paroptab_end =
tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]);
#endif

1079
contrib/toolchain/binutils/include/opcode/tic4x.h Normal file
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163
contrib/toolchain/binutils/include/opcode/tic54x.h Normal file
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/* tic54x.h -- Header file for TI TMS320C54X opcode table
Copyright 1999, 2000, 2001, 2005, 2009, 2010 Free Software Foundation, Inc.
Written by Timothy Wall (twall@cygnus.com)
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
#ifndef _opcode_tic54x_h_
#define _opcode_tic54x_h_
typedef struct _symbol
{
const char *name;
unsigned short value;
} symbol;
enum optype {
OPT = 0x8000,
OP_None = 0x0,
OP_Xmem, /* AR3 or AR4, indirect */
OP_Ymem, /* AR3 or AR4, indirect */
OP_pmad, /* PROG mem, direct */
OP_dmad, /* DATA mem, direct */
OP_Smem,
OP_Lmem, /* 32-bit single-addressed (direct/indirect) */
OP_MMR,
OP_PA,
OP_Sind,
OP_xpmad,
OP_xpmad_ms7,
OP_MMRX,
OP_MMRY,
OP_SRC1, /* src accumulator in bit 8 */
OP_SRC, /* src accumulator in bit 9 */
OP_RND, /* rounded result dst accumulator, opposite of bit 8 */
OP_DST, /* dst accumulator in bit 8 */
OP_ARX, /* arX in bits 0-3 */
OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */
OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */
OP_B, /* ACC B only */
OP_A, /* ACC A only */
OP_lk, /* 16-bit immediate, '#' optional */
OP_TS,
OP_k8, /* -128 <= k <= 128 */
OP_16, /* literal "16" */
OP_BITC, /* 0 to 16 */
OP_CC, /* condition code */
OP_CC2, /* 4-bit condition code */
OP_CC3, /* 2-bit condition code */
OP_123, /* 1, 2, or 3 */
OP_031, /* 0-31, numeric */
OP_k5, /* 0 to 31 */
OP_k8u, /* 0 to 255 */
OP_ASM, /* "ASM" */
OP_T, /* "T" */
OP_DP, /* "DP" */
OP_ARP, /* "ARP" */
OP_k3, /* 0-7 */
OP_lku, /* 0 to 65535 */
OP_N, /* 0/1 or ST0/ST1 */
OP_SBIT, /* status bit or 0-15 */
OP_12, /* one or two */
OP_k9, /* 9 bits of data page (DP) address */
OP_TRN, /* "TRN" */
};
typedef struct _template
{
/* The opcode mnemonic */
const char *name;
unsigned int words; /* insn size in words */
int minops, maxops; /* min/max operand count */
/* The significant bits in the opcode. Other bits are zero.
Instructions with more than 16 bits of opcode store the rest in the upper
16 bits.
*/
unsigned short opcode;
#define INDIRECT(OP) ((OP)&0x80)
#define MOD(OP) (((OP)>>3)&0xF)
#define ARF(OP) ((OP)&0x7)
#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12)
#define SRC(OP) ((OP)&0x200)
#define DST(OP) ((OP)&0x100)
#define SRC1(OP) ((OP)&0x100)
#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F))
#define SHFT(OP) ((OP)&0xF)
#define ARX(OP) ((OP)&0x7)
#define XMEM(OP) (((OP)&0x00F0)>>4)
#define YMEM(OP) ((OP)&0x000F)
#define XMOD(C) (((C)&0xC)>>2)
#define XARX(C) (((C)&0x3)+2)
#define CC3(OP) (((OP)>>8)&0x3)
#define SBIT(OP) ((OP)&0xF)
#define MMR(OP) ((OP)&0x7F)
#define MMRX(OP) ((((OP)>>4)&0xF)+16)
#define MMRY(OP) (((OP)&0xF)+16)
#define OPTYPE(X) ((X)&~OPT)
/* Ones in this mask indicate which bits must match the opcode field.
Zeroes indicate don't care bits (operands and/or opcode options) */
unsigned short mask;
/* An array of operand codes (at most 4 operands) */
#define MAX_OPERANDS 4
enum optype operand_types[MAX_OPERANDS];
/* Special purpose flags (e.g. branch type, parallel, delay, etc)
*/
unsigned short flags;
#define B_NEXT 0 /* normal execution, next insn is next address */
#define B_BRANCH 1 /* next insn is in opcode */
#define B_RET 2 /* next insn is on stack */
#define B_BACC 3 /* next insn is in acc */
#define B_REPEAT 4 /* next insn repeats */
#define FL_BMASK 0x07
#define FL_DELAY 0x10 /* instruction uses delay slots */
#define FL_EXT 0x20 /* instruction takes two words */
#define FL_FAR 0x40 /* far mode addressing */
#define FL_LP 0x80 /* LP-only instruction */
#define FL_NR 0x100 /* no repeat allowed */
#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */
#define FL_PAR 0x400 /* Parallel instruction. */
unsigned short opcode2, mask2; /* some insns have an extended opcode */
const char* parname;
enum optype paroperand_types[MAX_OPERANDS];
} insn_template;
extern const insn_template tic54x_unknown_opcode;
extern const insn_template tic54x_optab[];
extern const insn_template tic54x_paroptab[];
extern const symbol mmregs[], regs[];
extern const symbol condition_codes[], cc2_codes[], status_bits[];
extern const symbol cc3_codes[];
extern const char *misc_symbols[];
struct disassemble_info;
extern const insn_template* tic54x_get_insn (struct disassemble_info *,
bfd_vma, unsigned short, int *);
#endif /* _opcode_tic54x_h_ */

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contrib/toolchain/binutils/include/opcode/tic6x-control-registers.h Normal file
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/* TI C6X control register information.
Copyright 2010
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* Define the CTRL macro before including this file; it takes as
arguments the fields from tic6x_ctrl (defined in tic6x.h). The
control register name is given as an identifier; the isa_variants
field without the leading TIC6X_INSN_; the rw field without the
leading tic6x_rw_. */
CTRL(amr, C62X, read_write, 0x0, 0x10)
CTRL(csr, C62X, read_write, 0x1, 0x10)
CTRL(dnum, C64XP, read, 0x11, 0x1f)
CTRL(ecr, C64XP, write, 0x1d, 0x1f)
CTRL(efr, C64XP, read, 0x1d, 0x1f)
CTRL(fadcr, C67X, read_write, 0x12, 0x1f)
CTRL(faucr, C67X, read_write, 0x13, 0x1f)
CTRL(fmcr, C67X, read_write, 0x14, 0x1f)
CTRL(gfpgfr, C64X, read_write, 0x18, 0x1f)
CTRL(gplya, C64XP, read_write, 0x16, 0x1f)
CTRL(gplyb, C64XP, read_write, 0x17, 0x1f)
CTRL(icr, C62X, write, 0x3, 0x10)
CTRL(ier, C62X, read_write, 0x4, 0x10)
CTRL(ierr, C64XP, read_write, 0x1f, 0x1f)
CTRL(ifr, C62X, read, 0x2, 0x1d)
CTRL(ilc, C64XP, read_write, 0xd, 0x1f)
CTRL(irp, C62X, read_write, 0x6, 0x10)
CTRL(isr, C62X, write, 0x2, 0x10)
CTRL(istp, C62X, read_write, 0x5, 0x10)
CTRL(itsr, C64XP, read_write, 0x1b, 0x1f)
CTRL(nrp, C62X, read_write, 0x7, 0x10)
CTRL(ntsr, C64XP, read_write, 0x1c, 0x1f)
CTRL(pce1, C62X, read, 0x10, 0xf)
CTRL(rep, C64XP, read_write, 0xf, 0x1f)
CTRL(rilc, C64XP, read_write, 0xe, 0x1f)
CTRL(ssr, C64XP, read_write, 0x15, 0x1f)
CTRL(tsch, C64XP, read, 0xb, 0x1f)
/* Contrary to Table 3-26 in SPRUFE8, this register is read-write, as
documented in section 2.9.13. */
CTRL(tscl, C64XP, read_write, 0xa, 0x1f)
CTRL(tsr, C64XP, read_write, 0x1a, 0x1f)

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/* TI C6X instruction format information.
Copyright 2010-2013 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
/* Define the FMT macro before including this file; it takes a name
and the fields from tic6x_insn_format (defined in tic6x.h). */
/* Expansion fields values for 16 bits insn. */
#define SAT(a) (((a) & 1) << TIC6X_COMPACT_SAT_POS)
#define BR(a) (((a) & 1) << TIC6X_COMPACT_BR_POS)
#define DSZ(a) (((a) & 7) << TIC6X_COMPACT_DSZ_POS)
/* Composite fields for 16 bits insn. */
#define BFLD(low_pos, width, pos) { (low_pos), (width), (pos) }
#define BFLD1(a) 1, { a }
#define BFLD2(a, b) 2, { a, b }
#define BFLD3(a, b, c) 3, { a, b, c }
#define BFLD4(a, b, c, d) 4, { a, b, c, d }
#define COMPFLD(name, bitfields) { CONCAT2(tic6x_field_,name), bitfields }
/**/
#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), BFLD1(BFLD(pos, width, 0)) }
#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
#define CFLDS2(a, b) 5, { CFLDS, a, b }
#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d }
#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e }
#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f }
#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g }
#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h }
#define NFLDS FLD(p, 0, 1)
#define NFLDS1(a) 2, { NFLDS, a }
#define NFLDS2(a, b) 3, { NFLDS, a, b }
#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c }
#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
/* 16 bits insn */
#define FLDS1(a) 1, { a }
#define FLDS2(a, b) 2, { a, b }
#define FLDS3(a, b, c) 3, { a, b, c }
#define FLDS4(a, b, c, d) 4, { a, b, c, d }
#define FLDS5(a, b, c, d, e) 5, { a, b, c, d, e }
#define SFLDS FLD(s, 0, 1)
#define SFLDS1(a) 2, { SFLDS, a }
#define SFLDS2(a, b) 3, { SFLDS, a, b }
#define SFLDS3(a, b, c) 4, { SFLDS, a, b, c }
#define SFLDS4(a, b, c, d) 5, { SFLDS, a, b, c, d }
#define SFLDS5(a, b, c, d, e) 6, { SFLDS, a, b, c, d, e }
#define SFLDS6(a, b, c, d, e, f) 7, { SFLDS, a, b, c, d, e, f }
#define SFLDS7(a, b, c, d, e, f, g) 8, { SFLDS, a, b, c, d, e, f, g }
/**/
/* These are in the order from SPRUFE8, appendices C-H. */
/* Appendix C 32-bit formats. */
FMT(d_1_or_2_src, 32, 0x40, 0x7c,
CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
FLD(dst, 23, 5)))
FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c,
CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
FMT(d_load_store, 32, 0x4, 0xc,
CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1),
FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5),
FLD(srcdst, 23, 5)))
/* The nonaligned loads and stores have the formats shown in the
individual instruction descriptions; the appendix is incorrect. */
FMT(d_load_nonaligned, 32, 0x124, 0x17c,
CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4)))
FMT(d_store_nonaligned, 32, 0x174, 0x17c,
CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4)))
FMT(d_load_store_long, 32, 0xc, 0xc,
CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
FLD(dst, 23, 5)))
FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
FLD(dst, 23, 5)))
/* Appendix C 16-bit formats will go here. */
/* C-8 */
FMT(d_doff4_dsz_0xx, 16, DSZ(0) | 0x0004, DSZ(0x4) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_100, 16, DSZ(4) | 0x0004, DSZ(0x7) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_000, 16, DSZ(0) | 0x0004, DSZ(0x7) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_x01, 16, DSZ(1) | 0x0004, DSZ(0x3) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_01x, 16, DSZ(2) | 0x0004, DSZ(0x6) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_111, 16, DSZ(7) | 0x0004, DSZ(0x7) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_x11, 16, DSZ(3) | 0x0004, DSZ(0x3) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_010, 16, DSZ(2) | 0x0004, DSZ(0x7) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
FMT(d_doff4_dsz_110, 16, DSZ(6) | 0x0004, DSZ(0x7) | 0x0406,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
/* C-9 */
FMT(d_doff4dw, 16, DSZ(4) | 0x0004, DSZ(0x4) | 0x0406,
SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
/* C-10 */
FMT(d_dind_dsz_0xx, 16, DSZ(0) | 0x0404, DSZ(0x4) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_x01, 16, DSZ(1) | 0x0404, DSZ(0x3) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_x11, 16, DSZ(3) | 0x0404, DSZ(0x3) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_01x, 16, DSZ(2) | 0x0404, DSZ(0x6) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_000, 16, DSZ(0) | 0x0404, DSZ(0x7) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_010, 16, DSZ(2) | 0x0404, DSZ(0x7) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_100, 16, DSZ(4) | 0x0404, DSZ(0x7) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_110, 16, DSZ(6) | 0x0404, DSZ(0x7) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
FMT(d_dind_dsz_111, 16, DSZ(7) | 0x0404, DSZ(0x7) | 0x0c06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(src1, 13, 3)))
/* C-11 */
FMT(d_dinddw, 16, DSZ(4) | 0x0404, DSZ(0x4) | 0x0c06,
SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
FLD(sz, 9, 1), FLD(t, 12, 1), FLD(src1, 13, 3)))
/* C-12 */
FMT(d_dinc_dsz_x01, 16, DSZ(1) | 0x0c04, DSZ(0x3) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_0xx, 16, DSZ(0) | 0x0c04, DSZ(0x4) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_01x, 16, DSZ(2) | 0x0c04, DSZ(0x6) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_x11,16, DSZ(3) | 0x0c04, DSZ(0x3) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_000, 16, DSZ(0) | 0x0c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_010, 16, DSZ(2) | 0x0c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_100, 16, DSZ(4) | 0x0c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_110, 16, DSZ(6) | 0x0c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_dinc_dsz_111, 16, DSZ(7) | 0x0c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
/* C-13*/
FMT(d_dincdw, 16, DSZ(4) | 0x0c04, DSZ(0x4) | 0xcc06,
SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1)))
/* C-14 */
FMT(d_ddec_dsz_01x, 16, DSZ(2) | 0x4c04, DSZ(0x6) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_0xx, 16, DSZ(0) | 0x4c04, DSZ(0x4) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_x01, 16, DSZ(1) | 0x4c04, DSZ(0x3) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_x11, 16, DSZ(3) | 0x4c04, DSZ(0x3) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_000, 16, DSZ(0) | 0x4c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_010, 16, DSZ(2) | 0x4c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_100, 16, DSZ(4) | 0x4c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_110, 16, DSZ(6) | 0x4c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
FMT(d_ddec_dsz_111, 16, DSZ(7) | 0x4c04, DSZ(0x7) | 0xcc06,
SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
FLD(t, 12, 1), FLD(cst, 13, 1)))
/* C-15 */
FMT(d_ddecdw, 16, DSZ(4) | 0x4c04, DSZ(0x4) | 0xcc06,
SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1)))
/* C-16 */
FMT(d_dstk, 16, 0x8c04, 0x8c06,
SFLDS4(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(t, 12, 1),
COMPFLD(cst, BFLD2(BFLD(7, 3, 2), BFLD(13, 2, 0)))))
/* C-17 */
FMT(d_dx2op, 16, 0x0036, 0x047e,
SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), FLD(srcdst, 13, 3)))
/* C-18 */
FMT(d_dx5, 16, 0x0436, 0x047e,
SFLDS2(FLD(dst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
/* C-19 */
FMT(d_dx5p, 16, 0x0c76, 0x1c7e,
SFLDS2(FLD(op, 7, 1),
COMPFLD(cst, BFLD2(BFLD(8, 2, 3), BFLD(13, 3, 0)))))
/* C-20 */
FMT(d_dx1, 16, 0x1876, 0x1c7e,
SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
/* C-21 */
FMT(d_dpp, 16, 0x0077, 0x087f,
SFLDS5(FLD(srcdst, 7, 4), FLD(t, 12, 1), FLD(cst, 13, 1), FLD(op, 14, 1),
FLD(dw, 15, 1)))
/* Appendix D 32-bit formats. */
FMT(l_1_or_2_src, 32, 0x18, 0x1c,
CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c,
NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
FMT(l_unary, 32, 0x358, 0xffc,
CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
FLD(dst, 23, 5)))
/* Appendix D 16-bit formats will go here. */
/* D-4 */
FMT(l_l3_sat_0, 16, SAT(0) | 0x0000, SAT(1) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(src1, 13, 3)))
FMT(l_l3_sat_1, 16, SAT(1) | 0x0000, SAT(1) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(src1, 13, 3)))
/* D-5 - combine cst3 and n fields into a single field cst */
FMT(l_l3i, 16, 0x0400, 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(sn, 11, 1), FLD(x, 12, 1),
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
/* D-6 Mtbd ? */
/* D-7 */
FMT(l_l2c, 16, 0x0408, 0x040e,
SFLDS5(FLD(dst, 4, 1), FLD(src2, 7, 3), FLD(x, 12, 1), FLD(src1, 13, 3),
COMPFLD(op, BFLD2(BFLD(5, 2, 0), BFLD(11, 1, 2)))))
/* D-8 */
FMT(l_lx5, 16, 0x0426, 0x047e,
SFLDS2(FLD(dst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
/* D-9 */
FMT(l_lx3c, 16, 0x0026, 0x147e,
SFLDS3(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 3)))
/* D-10 */
FMT(l_lx1c, 16, 0x1026, 0x147e,
SFLDS4(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 1), FLD(op, 14, 2)))
/* D-11 */
FMT(l_lx1, 16, 0x1866, 0x1c7e,
SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
/* Appendix E 32-bit formats. */
FMT(m_compound, 32, 0x30, 0x83c,
CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c,
NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
/* Contrary to SPRUFE8, this does have predicate fields. */
FMT(m_unary, 32, 0xf0, 0xffc,
CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
FLD(dst, 23, 5)))
/* M-unit formats missing from Appendix E. */
FMT(m_mpy, 32, 0x0, 0x7c,
CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
/* Appendix E 16-bit formats will go here. */
FMT(m_m3_sat_0, 16, SAT(0) | 0x001e, SAT(1) | 0x001e,
SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2),
FLD(x, 12, 1), FLD(src1, 13, 3)))
FMT(m_m3_sat_1, 16, SAT(1) | 0x001e, SAT(1) | 0x001e,
SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2),
FLD(x, 12, 1), FLD(src1, 13, 3)))
/* Appendix F 32-bit formats. */
FMT(s_1_or_2_src, 32, 0x20, 0x3c,
CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23 ,5)))
FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c,
CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c,
NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1)))
FMT(s_unary, 32, 0xf20, 0xffc,
CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
FLD(dst, 23, 5)))
FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c,
CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21)))
FMT(s_call_imm_nop, 32, 0x10, 0xe000007c,
NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1)))
FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc,
CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12)))
FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc,
CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5)))
FMT(s_branch, 32, 0x360, 0xf83effc,
CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5)))
FMT(s_mvk, 32, 0x28, 0x3c,
CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
FMT(s_field, 32, 0x8, 0x3c,
CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5),
FLD(src2, 18, 5), FLD(dst, 23, 5)))
/* S-unit formats missing from Appendix F. */
FMT(s_addk, 32, 0x50, 0x7c,
CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
FMT(s_addkpc, 32, 0x160, 0x1ffc,
CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5)))
FMT(s_b_irp, 32, 0x1800e0, 0x7feffc,
CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc,
CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
FMT(s_bdec, 32, 0x1020, 0x1ffc,
CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
FMT(s_bpos, 32, 0x20, 0x1ffc,
CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
/* Appendix F 16-bit formats will go here. */
/* F-17 Sbs7 Instruction Format */
FMT(s_sbs7, 16, BR(1) | 0x000a, BR(1) | 0x003e,
SFLDS2(FLD(cst, 6, 7), FLD(n, 13, 3)))
/* F-18 Sbu8 Instruction Format */
FMT(s_sbu8, 16, BR(1) | 0xc00a, BR(1) | 0xc03e,
SFLDS1(FLD(cst, 6, 8)))
/* F-19 Scs10 Instruction Format */
FMT(s_scs10, 16, BR(1) | 0x001a, BR(1) | 0x003e,
SFLDS1(FLD(cst, 6, 10)))
/* F-20 Sbs7c Instruction Format */
FMT(s_sbs7c, 16, BR(1) | 0x002a, BR(1) | 0x002e,
SFLDS3(FLD(z, 4, 1), FLD(cst, 6, 7), FLD(n, 13, 3)))
/* F-21 Sbu8c Instruction Format */
FMT(s_sbu8c, 16, BR(1) | 0xc02a, BR(1) | 0xc02e,
SFLDS2(FLD(z, 4, 1), FLD(cst, 6, 8)))
/* F-22 S3 Instruction Format */
FMT(s_s3, 16, BR(0) | 0x000a, BR(1) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(src1, 13, 3)))
FMT(s_s3_sat_x, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(0) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(src1, 13, 3)))
FMT(s_s3_sat_0, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(1) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(src1, 13, 3)))
FMT(s_s3_sat_1, 16, BR(0) | SAT(1) | 0x000a, BR(1) | SAT(1) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(src1, 13, 3)))
/* F-23 S3i Instruction Format */
FMT(s_s3i, 16, BR(0) | 0x040a, BR(1) | 0x040e,
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(cst, 13, 3)))
/* F-24 Smvk8 Instruction Format */
FMT(s_smvk8, 16, 0x0012, 0x001e,
SFLDS2(FLD(dst, 7, 3),
COMPFLD(cst, BFLD4(BFLD(10, 1, 7), BFLD(5, 2, 5), BFLD(11, 2, 3), BFLD(13, 3, 0)))))
/* F-25 Ssh5 Instruction Format */
FMT(s_ssh5_sat_x, 16, SAT(0) | 0x0402, SAT(0) | 0x041e,
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
FMT(s_ssh5_sat_0, 16, SAT(0) | 0x0402, SAT(1) | 0x041e,
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
FMT(s_ssh5_sat_1, 16, SAT(1) | 0x0402, SAT(1) | 0x041e,
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
/* F-26 S2sh Instruction Format */
FMT(s_s2sh, 16, 0x0462, 0x047e,
SFLDS3(FLD(srcdst, 7, 3), FLD(op, 11, 2), FLD(src1, 13, 3)))
/* F-27 Sc5 Instruction Format */
FMT(s_sc5, 16, 0x0002, 0x041e,
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
/* F-28 S2ext Instruction Format */
FMT(s_s2ext, 16, 0x0062, 0x047e,
SFLDS3(FLD(src, 7, 3), FLD(op, 11, 2), FLD(dst, 13, 3)))
/* F-29 Sx2op Instruction Format */
FMT(s_sx2op, 16, 0x002e, 0x047e,
SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
FLD(srcdst, 13, 3)))
/* F-30 Sx5 Instruction Format */
FMT(s_sx5, 16, 0x042e, 0x047e,
SFLDS2(FLD(dst, 7, 3),
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
/* F-31 Sx1 Instruction Format */
FMT(s_sx1, 16, 0x186e, 0x1c7e,
SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
/* F-32 Sx1b Instruction Format */
FMT(s_sx1b, 16, 0x006e, 0x187e,
SFLDS2(FLD(src2, 7, 4), FLD(n, 13, 3)))
/* Appendix G 16-bit formats will go here. */
FMT(lsdmvto, 16, 0x0006, 0x0066,
SFLDS4(FLD(unit, 3, 2),
FLD(x, 12, 1), FLD(dst, 13, 3),
COMPFLD(src2, BFLD2(BFLD(10, 2, 3), BFLD(7, 3, 0)))))
FMT(lsdmvfr, 16, 0x0046, 0x0066,
SFLDS4(FLD(unit, 3, 2), FLD(src2, 7, 3), FLD(x, 12, 1),
COMPFLD(dst, BFLD2(BFLD(10, 2, 3), BFLD(13, 3, 0)))))
/* G-3 */
FMT(lsdx1c, 16, 0x0866, 0x1c66,
SFLDS4(FLD(unit, 3, 2), FLD(dst, 7, 3), FLD(cst, 13, 1),
FLD(cc, 14, 2)))
/* G-4 */
FMT(lsdx1, 16, 0x1866, 0x1c66,
SFLDS3(FLD(unit, 3, 2), FLD(srcdst, 7, 3), FLD(op, 13, 3)))
/* Appendix H 32-bit formats. */
FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc,
CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5)))
/* Corrected relative to Appendix H. */
FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc,
NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4)))
/* No-unit formats missing from Appendix H (given the NOP and IDLE
correction). */
FMT(nfu_dint, 32, 0x10004000, 0xfffffffc,
NFLDS1(FLD(s, 1, 1)))
FMT(nfu_rint, 32, 0x10006000, 0xfffffffc,
NFLDS1(FLD(s, 1, 1)))
FMT(nfu_swe, 32, 0x10000000, 0xfffffffc,
NFLDS1(FLD(s, 1, 1)))
FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc,
NFLDS1(FLD(s, 1, 1)))
/* Although formally covered by the loop buffer format, the fields in
that format are not useful for all such instructions and not all
instructions can be predicated. */
FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc,
NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6)))
FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc,
NFLDS1(FLD(s, 1, 1)))
FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8)))
/* Appendix H 16-bit formats will go here. */
/* H-5 */
FMT(nfu_uspl, 16, 0x0c66, 0xbc7e,
FLDS2(FLD(op, 0, 1), COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3)))))
/* H-6 */
/* make up some fields to pretend to have s and z fields s for this format
so as to fit in other predicated compact instruction to avoid special-
casing this instruction in tic6x-dis.c
use op field as a predicate adress register selector (s field)
use the first zeroed bit as a z value as this insn only supports [a0]
and [b0] predicate forms.
*/
FMT(nfu_uspldr, 16, 0x8c66, 0xbc7e,
FLDS4(FLD(op, 0, 1), FLD(s, 0, 1), FLD(z, 3, 1),
COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3)))))
/* H-7 */
FMT(nfu_uspk, 16, 0x1c66, 0x3c7e,
FLDS1(COMPFLD(fstgfcyc, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
/* H-8a */
FMT(nfu_uspma, 16, 0x2c66, 0x3c7e,
FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
/* H-8b */
FMT(nfu_uspmb, 16, 0x3c66, 0x3c7e,
FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
/* H-9 */
FMT(nfu_unop, 16, 0x0c6e, 0x1fff,
FLDS1(FLD(n, 13, 3)))
#undef FLD
#undef CFLDS
#undef CFLDS2
#undef CFLDS3
#undef CFLDS4
#undef CFLDS5
#undef CFLDS6
#undef CFLDS7
#undef CFLDS8
#undef NFLDS
#undef NFLDS1
#undef NFLDS2
#undef NFLDS3
#undef NFLDS5
#undef NFLDS6
#undef NFLDS7
#undef SFLDS
#undef SFLDS1
#undef SFLDS2
#undef SFLDS3
#undef SFLDS4
#undef SFLDS5
#undef SFLDS6
#undef SFLDS7
#undef BFLD
#undef BFLD1
#undef BFLD2
#undef BFLD3
#undef BFLD4
#undef FLDS1
#undef FLDS2
#undef FLDS3
#undef FLDS4
#undef FLDS5
#undef COMPFLD
#undef DSZ
#undef BR
#undef SAT

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contrib/toolchain/binutils/include/opcode/tic6x.h Normal file
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/* TI C6X opcode information.
Copyright 2010-2013 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef OPCODE_TIC6X_H
#define OPCODE_TIC6X_H
#include "bfd.h"
#include "symcat.h"
/* A field in an instruction format. The names are based on those
used in the architecture manuals. */
typedef enum
{
tic6x_field_baseR,
tic6x_field_cc,
tic6x_field_creg,
tic6x_field_cst,
tic6x_field_csta,
tic6x_field_cstb,
tic6x_field_dst,
tic6x_field_dstms,
tic6x_field_dw,
tic6x_field_fstgfcyc,
tic6x_field_h,
tic6x_field_ii,
tic6x_field_mask,
tic6x_field_mode,
tic6x_field_n,
tic6x_field_na,
tic6x_field_offsetR,
tic6x_field_op,
tic6x_field_p,
tic6x_field_ptr,
tic6x_field_r,
tic6x_field_s,
tic6x_field_sc,
tic6x_field_src,
tic6x_field_src1,
tic6x_field_src2,
tic6x_field_srcdst,
tic6x_field_srcms,
tic6x_field_sn,
tic6x_field_sz,
tic6x_field_unit,
tic6x_field_t,
tic6x_field_x,
tic6x_field_y,
tic6x_field_z
} tic6x_insn_field_id;
typedef struct
{
/* The least-significant bit position in the field. */
unsigned short low_pos;
/* The number of bits in the field. */
unsigned short width;
/* The position of the bitfield in the field. */
unsigned short pos;
} tic6x_bitfield;
/* Maximum number of subfields in composite field. */
#define TIC6X_MAX_BITFIELDS 4
typedef struct
{
/* The name used to reference the field. */
tic6x_insn_field_id field_id;
unsigned int num_bitfields;
tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS];
} tic6x_insn_field;
/* Maximum number of variable fields in an instruction format. */
#define TIC6X_MAX_INSN_FIELDS 11
/* A particular instruction format. */
typedef struct
{
/* How many bits in the instruction. */
unsigned int num_bits;
/* Constant bits in the instruction. */
unsigned int cst_bits;
/* Mask matching those bits. */
unsigned int mask;
/* The number of instruction fields. */
unsigned int num_fields;
/* Descriptions of instruction fields. */
tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS];
} tic6x_insn_format;
/* An index into the table of instruction formats. */
typedef enum
{
#define FMT(name, num_bits, cst_bits, mask, fields) \
CONCAT2(tic6x_insn_format_, name),
#include "tic6x-insn-formats.h"
#undef FMT
tic6x_insn_format_max
} tic6x_insn_format_id;
/* The table itself. */
extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max];
/* If instruction format FMT has a field FIELD, return a pointer to
the description of that field; otherwise return NULL. */
const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt,
tic6x_insn_field_id field);
/* Description of a field (in an instruction format) whose value is
fixed, or constrained to be in a particular range, in a particular
opcode. */
typedef struct
{
/* The name of the field. */
tic6x_insn_field_id field_id;
/* The least value of the field in this instruction. */
unsigned int min_val;
/* The greatest value of the field in this instruction. */
unsigned int max_val;
} tic6x_fixed_field;
/* Pseudo opcode fields position for compact instructions
If 16 bits instruction detected, the opcode is enriched
[DSZ/3][BR][SAT][opcode] */
#define TIC6X_COMPACT_SAT_POS 16
#define TIC6X_COMPACT_BR_POS 17
#define TIC6X_COMPACT_DSZ_POS 18
/* Bit-masks for defining instructions present on some subset of
processors; each indicates an instruction present on that processor
and those that are supersets of it. The options passed to the
assembler determine a bit-mask ANDed with the bit-mask indicating
when the instruction was added to determine whether the instruction
is enabled. */
#define TIC6X_INSN_C62X 0x0001
#define TIC6X_INSN_C64X 0x0002
#define TIC6X_INSN_C64XP 0x0004
#define TIC6X_INSN_C67X 0x0008
#define TIC6X_INSN_C67XP 0x0010
#define TIC6X_INSN_C674X 0x0020
/* Flags with further information about an opcode table entry. */
/* Only used by the assembler, not the disassembler. */
#define TIC6X_FLAG_MACRO 0x0001
/* Must be first in its execute packet. */
#define TIC6X_FLAG_FIRST 0x0002
/* Multi-cycle NOP (not used for the NOP n instruction itself, which
is only a multicycle NOP if n > 1). */
#define TIC6X_FLAG_MCNOP 0x0004
/* Cannot be in parallel with a multi-cycle NOP. */
#define TIC6X_FLAG_NO_MCNOP 0x0008
/* Load instruction. */
#define TIC6X_FLAG_LOAD 0x0010
/* Store instruction. */
#define TIC6X_FLAG_STORE 0x0020
/* Unaligned memory operation. */
#define TIC6X_FLAG_UNALIGNED 0x0040
/* Only on side B. */
#define TIC6X_FLAG_SIDE_B_ONLY 0x0080
/* Only on data path T2. */
#define TIC6X_FLAG_SIDE_T2_ONLY 0x0100
/* Does not support cross paths. */
#define TIC6X_FLAG_NO_CROSS 0x0200
/* Annotate this branch instruction as a call. */
#define TIC6X_FLAG_CALL 0x0400
/* Annotate this branch instruction as a return. */
#define TIC6X_FLAG_RETURN 0x0800
/* This instruction starts a software pipelined loop. */
#define TIC6X_FLAG_SPLOOP 0x1000
/* This instruction ends a software pipelined loop. */
#define TIC6X_FLAG_SPKERNEL 0x2000
/* This instruction takes a list of functional units as parameters;
although described as having one parameter, the number may be 0 to
8. */
#define TIC6X_FLAG_SPMASK 0x4000
/* When more than one opcode matches the assembly source, prefer the
one with the highest value for this bit-field. If two opcode table
entries can match the same syntactic form, they must have different
values here. */
#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15)
#define TIC6X_FLAG_PREFER(n) ((n) << 15)
/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */
#define TIC6X_FLAG_INSN16_SPRED 0x00100000
/* 16 bits opcode ignores RS bit of fetch packet header */
#define TIC6X_FLAG_INSN16_NORS 0x00200000
/* 16 bits opcode only on side B */
#define TIC6X_FLAG_INSN16_BSIDE 0x00400000
/* 16 bits opcode ptr reg is b15 */
#define TIC6X_FLAG_INSN16_B15PTR 0x00800000
/* 16 bits opcode memory access modes */
#define TIC6X_INSN16_MEM_MODE(n) ((n) << 16)
#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16)
#define TIC6X_MEM_MODE_NEGATIVE 0
#define TIC6X_MEM_MODE_POSITIVE 1
#define TIC6X_MEM_MODE_REG_NEGATIVE 4
#define TIC6X_MEM_MODE_REG_POSITIVE 5
#define TIC6X_MEM_MODE_PREDECR 8
#define TIC6X_MEM_MODE_PREINCR 9
#define TIC6X_MEM_MODE_POSTDECR 10
#define TIC6X_MEM_MODE_POSTINCR 11
#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode)
#define TIC6X_NUM_PREFER 2
/* Maximum number of fixed fields for a particular opcode. */
#define TIC6X_MAX_FIXED_FIELDS 4
/* Maximum number of operands in the opcode table for a particular
opcode. */
#define TIC6X_MAX_OPERANDS 4
/* Maximum number of operands in the source code for a particular
opcode (different from the number in the opcode table for SPMASK
and SPMASKR). */
#define TIC6X_MAX_SOURCE_OPERANDS 8
/* Maximum number of variable fields for a particular opcode. */
#define TIC6X_MAX_VAR_FIELDS 7
/* Which functional units an opcode uses. This only describes the
basic choice of D, L, M, S or no functional unit; other fields are
used to describe further restrictions (instructions only operating
on one side), use of cross paths and load/store instructions using
one side for the address and the other side for the source or
destination register. */
typedef enum
{
tic6x_func_unit_d,
tic6x_func_unit_l,
tic6x_func_unit_m,
tic6x_func_unit_s,
tic6x_func_unit_nfu
} tic6x_func_unit_base;
/* Possible forms of source operand. */
typedef enum
{
/* An assembly-time constant. */
tic6x_operand_asm_const,
/* A link-time constant. */
tic6x_operand_link_const,
/* A register, from the same side as the functional unit
selected. */
tic6x_operand_reg,
/* A register, from the same side as the functional unit
selected that ignore RS header bit */
tic6x_operand_reg_nors,
/* A register, from the b side */
tic6x_operand_reg_bside,
/* A register, from the b side and from the low register set */
tic6x_operand_reg_bside_nors,
/* A register, that is from the other side if a cross path is
used. */
tic6x_operand_xreg,
/* A register, that is from the side of the data path
selected. */
tic6x_operand_dreg,
/* An address register usable with 15-bit offsets (B14 or B15).
This is from the same side as the functional unit if a cross
path is not used, and the other side if a cross path is
used. */
tic6x_operand_areg,
/* The B15 register */
tic6x_operand_b15reg,
/* A register coded as an offset from either A16 or B16 depending
on the value of the t bit. */
tic6x_operand_treg,
/* A register (A0 or B0), from the same side as the
functional unit selected. */
tic6x_operand_zreg,
/* A return address register (A3 or B3), from the same side as the
functional unit selected. */
tic6x_operand_retreg,
/* A register pair, from the same side as the functional unit
selected. */
tic6x_operand_regpair,
/* A register pair, that is from the other side if a cross path is
used. */
tic6x_operand_xregpair,
/* A register pair, from the side of the data path selected. */
tic6x_operand_dregpair,
/* A register pair coded as an offset from either A16 or B16 depending
on the value of the t bit. */
tic6x_operand_tregpair,
/* The literal string "irp" (case-insensitive). */
tic6x_operand_irp,
/* The literal string "nrp" (case-insensitive). */
tic6x_operand_nrp,
/* The literal string "ilc" (case-insensitive). */
tic6x_operand_ilc,
/* A control register. */
tic6x_operand_ctrl,
/* A memory reference (base and offset registers from the side of
the functional unit selected), using either unsigned 5-bit
constant or register offset, if any offset; register offsets
cannot use unscaled () syntax. */
tic6x_operand_mem_short,
/* A memory reference (base and offset registers from the side of
the functional unit selected), using either unsigned 5-bit
constant or register offset, if any offset; register offsets
can use unscaled () syntax (for LDNDW and STNDW). */
tic6x_operand_mem_ndw,
/* A memory reference using 15-bit link-time constant offset
relative to B14 or B15. */
tic6x_operand_mem_long,
/* A memory reference that only dereferences a register with no
further adjustments (*REG), that register being from the side
of the functional unit selected. */
tic6x_operand_mem_deref,
/* A functional unit name or a list thereof (for SPMASK and
SPMASKR). */
tic6x_operand_func_unit,
/* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits
instruction formats - spru732j.pdf Appendix F.4 */
tic6x_operand_hw_const_minus_1,
tic6x_operand_hw_const_0,
tic6x_operand_hw_const_1,
tic6x_operand_hw_const_5,
tic6x_operand_hw_const_16,
tic6x_operand_hw_const_24,
tic6x_operand_hw_const_31
} tic6x_operand_form;
/* Whether something is, or can be, read or written. */
typedef enum
{
tic6x_rw_none,
tic6x_rw_read,
tic6x_rw_write,
tic6x_rw_read_write
} tic6x_rw;
/* Description of a source operand and how it is used. */
typedef struct
{
/* The syntactic form of the operand. */
tic6x_operand_form form;
/* For non-constant operands, the size in bytes (1, 2, 4, 5 or
8). Ignored for constant operands. */
unsigned int size;
/* Whether the operand is read, written or both. In addition to the
operations described here, address registers are read on cycle 1
regardless of when the memory operand is read or written, and may
be modified as described by the addressing mode, and control
registers may be implicitly read by some instructions. There are
also some special cases not fully described by this
structure.
- For mpydp, the low part of src2 is read on cycles 1 and 3 but
not 2, and the high part on cycles 2 and 4 but not 3.
- The swap2 pseudo-operation maps to packlh2, reading the first
operand of swap2 twice. */
tic6x_rw rw;
/* The first and last cycles (1 for E1, etc.) at which the operand,
or the low part for two-register operands, is read or
written. */
unsigned short low_first;
unsigned short low_last;
/* Likewise, for the high part. */
unsigned short high_first;
unsigned short high_last;
} tic6x_operand_info;
/* Ways of converting an operand or functional unit specifier to a
field value. */
typedef enum
{
/* Store an unsigned assembly-time constant (which must fit) in
the field. */
tic6x_coding_ucst,
/* Store a signed constant (which must fit) in the field. This
may be used both for assembly-time constants and for link-time
constants. */
tic6x_coding_scst,
/* Subtract one from an unsigned assembly-time constant (which
must be strictly positive before the subtraction) and store the
value (which must fit) in the field. */
tic6x_coding_ucst_minus_one,
/* Negate a signed assembly-time constant, and store the result of
negation (which must fit) in the field. Used only for
pseudo-operations. */
tic6x_coding_scst_negate,
/* Store an unsigned link-time constant, implicitly DP-relative
and counting in bytes, in the field. For expression operands,
assembly-time constants are encoded as-is. For memory
reference operands, the offset is encoded as-is if [] syntax is
used and shifted if () is used. */
tic6x_coding_ulcst_dpr_byte,
/* Store an unsigned link-time constant, implicitly DP-relative
and counting in half-words, in the field. For expression
operands, assembly-time constants are encoded as-is. For
memory reference operands, the offset is encoded as-is if []
syntax is used and shifted if () is used. */
tic6x_coding_ulcst_dpr_half,
/* Store an unsigned link-time constant, implicitly DP-relative
and counting in words, in the field. For expression operands,
assembly-time constants are encoded as-is. For memory
reference operands, the offset is encoded as-is if [] syntax is
used and shifted if () is used. */
tic6x_coding_ulcst_dpr_word,
/* Store the low 16 bits of a link-time constant in the field;
considered unsigned for disassembly. */
tic6x_coding_lcst_low16,
/* Store the high 16 bits of a link-time constant in the field;
considered unsigned for disassembly. */
tic6x_coding_lcst_high16,
/* Store a signed PC-relative value (address of label minus
address of fetch packet containing the current instruction,
counted in words) in the field. */
tic6x_coding_pcrel,
/* Likewise, but counting in half-words if in a header-based fetch
packet. */
tic6x_coding_pcrel_half,
/* Store an unsigned PC-relative value used in compact insn */
tic6x_coding_pcrel_half_unsigned,
/* Encode the register number (even number for a register pair) in
the field. When applied to a memory reference, encode the base
register. */
tic6x_coding_reg,
/* Encode the register-pair's lsb (even register) for instructions
that use src1 as port for loading lsb of double-precision
operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp). */
tic6x_coding_regpair_lsb,
/* Encode the register-pair's msb (odd register), see above. */
tic6x_coding_regpair_msb,
/* Store 0 for register B14, 1 for register B15. When applied to
a memory reference, encode the base register. */
tic6x_coding_areg,
/* Compact instruction offset base register */
tic6x_coding_reg_ptr,
/* Store the low part of a control register address. */
tic6x_coding_crlo,
/* Store the high part of a control register address. */
tic6x_coding_crhi,
/* Encode the even register number for a register pair, shifted
right by one bit. */
tic6x_coding_reg_shift,
/* Store either the offset register or the 5-bit unsigned offset
for a memory reference. If an offset uses the unscaled ()
form, which is only permitted with constants, it is scaled
according to the access size of the operand before being
stored. */
tic6x_coding_mem_offset,
/* Store either the offset register or the 5-bit unsigned offset
for a memory reference, but with no scaling applied to the
offset (for nonaligned doubleword operations). */
tic6x_coding_mem_offset_noscale,
/* Store the addressing mode for a memory reference. */
tic6x_coding_mem_mode,
/* Store whether a memory reference is scaled. */
tic6x_coding_scaled,
/* Store the stage in an SPKERNEL instruction in the upper part of
the field. */
tic6x_coding_fstg,
/* Store the cycle in an SPKERNEL instruction in the lower part of
the field. */
tic6x_coding_fcyc,
/* Store the mask bits for functional units in the field in an
SPMASK or SPMASKR instruction. */
tic6x_coding_spmask,
/* Store the number of a register that is unused, or minimally
used, in this execute packet. The number must be the same for
all uses of this coding in a single instruction, but may be
different for different instructions in the execute packet.
This is for the "zero" pseudo-operation. This is not safe when
reads may occur from instructions in previous execute packets;
in such cases the programmer or compiler should use explicit
"sub" instructions for those cases of "zero" that cannot be
implemented as "mvk" for the processor specified. */
tic6x_coding_reg_unused,
/* Store 1 if the functional unit used is on side B, 0 for side
A. */
tic6x_coding_fu,
/* Store 1 if the data path used (source register for store,
destination for load) is on side B, 0 for side A. */
tic6x_coding_data_fu,
/* Store 1 if the cross path is being used, 0 otherwise. */
tic6x_coding_xpath,
/* L3i constant coding */
tic6x_coding_scst_l3i,
/* S3i constant coding */
tic6x_coding_cst_s3i,
/* mem offset minus 1 */
tic6x_coding_mem_offset_minus_one,
/* non aligned mem offset minus 1 */
tic6x_coding_mem_offset_minus_one_noscale,
tic6x_coding_rside
} tic6x_coding_method;
/* How to generate the value of a particular field. */
typedef struct
{
/* The name of the field. */
tic6x_insn_field_id field_id;
/* How it is encoded. */
tic6x_coding_method coding_method;
/* Source operand number, if any. */
unsigned int operand_num;
} tic6x_coding_field;
/* Types of instruction for pipeline purposes. The type determines
functional unit and cross path latency (when the same functional
unit can be used by other instructions, when the same cross path
can be used by other instructions). */
typedef enum
{
tic6x_pipeline_nop,
tic6x_pipeline_1cycle,
tic6x_pipeline_1616_m,
tic6x_pipeline_store,
tic6x_pipeline_mul_ext,
tic6x_pipeline_load,
tic6x_pipeline_branch,
tic6x_pipeline_2cycle_dp,
tic6x_pipeline_4cycle,
tic6x_pipeline_intdp,
tic6x_pipeline_dpcmp,
tic6x_pipeline_addsubdp,
tic6x_pipeline_mpyi,
tic6x_pipeline_mpyid,
tic6x_pipeline_mpydp,
tic6x_pipeline_mpyspdp,
tic6x_pipeline_mpysp2dp
} tic6x_pipeline_type;
/* Description of a control register. */
typedef struct
{
/* The name of the register. */
const char *name;
/* Which ISA variants include this control register. */
unsigned short isa_variants;
/* Whether it can be read, written or both (in supervisor mode).
Some registers use the same address, but different names, for
reading and writing. */
tic6x_rw rw;
/* crlo value for this register. */
unsigned int crlo;
/* Mask that, ANDed with the crhi value in the instruction, must be
0. 0 is always generated when generating code. */
unsigned int crhi_mask;
} tic6x_ctrl;
/* An index into the table of control registers. */
typedef enum
{
#define CTRL(name, isa, rw, crlo, crhi_mask) \
CONCAT2(tic6x_ctrl_,name),
#include "tic6x-control-registers.h"
#undef CTRL
tic6x_ctrl_max
} tic6x_ctrl_id;
/* The table itself. */
extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max];
/* An entry in the opcode table. */
typedef struct
{
/* The name of the instruction. */
const char *name;
/* Functional unit used by this instruction (basic information). */
tic6x_func_unit_base func_unit;
/* The format of this instruction. */
tic6x_insn_format_id format;
/* The pipeline type of this instruction. */
tic6x_pipeline_type type;
/* Which ISA variants include this instruction. */
unsigned short isa_variants;
/* Flags for this instruction. */
unsigned int flags;
/* Number of fixed fields, or fields with restricted value ranges,
for this instruction. */
unsigned int num_fixed_fields;
/* Values of fields fixed for this instruction. */
tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS];
/* The number of operands in the source form of this
instruction. */
unsigned int num_operands;
/* Information about individual operands. */
tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS];
/* The number of variable fields for this instruction with encoding
instructions explicitly given. */
unsigned int num_variable_fields;
/* How fields (other than ones with fixed value) are computed from
the source operands and functional unit specifiers. In addition
to fields specified here:
- creg, if present, is set from the predicate, along with z which
must be present if creg is present.
- p, if present (on all non-compact instructions), is set from
the parallel bars.
*/
tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS];
} tic6x_opcode;
/* An index into the table of opcodes. */
typedef enum
{
#define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \
CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
CONCAT4(tic6x_opcode_,name,_,e),
#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \
CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
CONCAT6(tic6x_opcode_,name,_,func_unit,_,e),
#include "tic6x-opcode-table.h"
#undef INSN
#undef INSNE
#undef INSNU
#undef INSNUE
tic6x_opcode_max
} tic6x_opcode_id;
/* The table itself. */
extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max];
/* A linked list of opcodes. */
typedef struct tic6x_opcode_list_tag
{
tic6x_opcode_id id;
struct tic6x_opcode_list_tag *next;
} tic6x_opcode_list;
/* The information from a fetch packet header. */
typedef struct
{
/* The header itself. */
unsigned int header;
/* Whether each word uses compact instructions. */
bfd_boolean word_compact[7];
/* Whether loads are protected. */
bfd_boolean prot;
/* Whether instructions use the high register set. */
bfd_boolean rs;
/* Data size. */
unsigned int dsz;
/* Whether compact instructions in the S unit are decoded as
branches. */
bfd_boolean br;
/* Whether compact instructions saturate. */
bfd_boolean sat;
/* P-bits. */
bfd_boolean p_bits[14];
} tic6x_fetch_packet_header;
#endif /* OPCODE_TIC6X_H */

283
contrib/toolchain/binutils/include/opcode/tic80.h Normal file
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/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table
Copyright 1996, 1997, 2003, 2010 Free Software Foundation, Inc.
Written by Fred Fish (fnf@cygnus.com), Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef TIC80_H
#define TIC80_H
/* The opcode table is an array of struct tic80_opcode. */
struct tic80_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with operands
are zeroes. */
unsigned long opcode;
/* The opcode mask. This is used by the disassembler. This is a mask
containing ones indicating those bits which must match the opcode
field, and zeroes indicating those bits which need not match (and are
presumably filled in by operands). */
unsigned long mask;
/* Special purpose flags for this opcode. */
unsigned char flags;
/* An array of operand codes. Each code is an index into the operand
table. They appear in the order which the operands must appear in
assembly code, and are terminated by a zero. FIXME: Adjust size to
match actual requirements when TIc80 support is complete */
unsigned char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise in
the order in which the disassembler should consider instructions.
FIXME: This isn't currently true. */
extern const struct tic80_opcode tic80_opcodes[];
extern const int tic80_num_opcodes;
/* The operands table is an array of struct tic80_operand. */
struct tic80_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert)
(unsigned long instruction, long op, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if ((o->flags & TIC80_OPERAND_SIGNED) != 0
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) (unsigned long instruction, int *invalid);
/* One bit syntax flags. */
unsigned long flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the tic80_opcodes table. */
extern const struct tic80_operand tic80_operands[];
/* Values defined for the flags field of a struct tic80_operand.
Note that flags for all predefined symbols, such as the general purpose
registers (ex: r10), control registers (ex: FPST), condition codes (ex:
eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be
or'd into an int where the lower bits contain the actual numeric value
that correponds to this predefined symbol. This way a single int can
contain both the value of the symbol and it's type.
*/
/* This operand must be an even register number. Floating point numbers
for example are stored in even/odd register pairs. */
#define TIC80_OPERAND_EVEN (1 << 0)
/* This operand must be an odd register number and must be one greater than
the register number of the previous operand. I.E. the second register in
an even/odd register pair. */
#define TIC80_OPERAND_ODD (1 << 1)
/* This operand takes signed values. */
#define TIC80_OPERAND_SIGNED (1 << 2)
/* This operand may be either a predefined constant name or a numeric value.
An example would be a condition code like "eq0.b" which has the numeric
value 0x2. */
#define TIC80_OPERAND_NUM (1 << 3)
/* This operand should be wrapped in parentheses rather than separated
from the previous one by a comma. This is used for various
instructions, like the load and store instructions, which want
their operands to look like "displacement(reg)" */
#define TIC80_OPERAND_PARENS (1 << 4)
/* This operand is a PC relative branch offset. The disassembler prints
these symbolically if possible. Note that the offsets are taken as word
offsets. */
#define TIC80_OPERAND_PCREL (1 << 5)
/* This flag is a hint to the disassembler for using hex as the prefered
printing format, even for small positive or negative immediate values.
Normally values in the range -999 to 999 are printed as signed decimal
values and other values are printed in hex. */
#define TIC80_OPERAND_BITFIELD (1 << 6)
/* This operand may have a ":m" modifier specified by bit 17 in a short
immediate form instruction. */
#define TIC80_OPERAND_M_SI (1 << 7)
/* This operand may have a ":m" modifier specified by bit 15 in a long
immediate or register form instruction. */
#define TIC80_OPERAND_M_LI (1 << 8)
/* This operand may have a ":s" modifier specified in bit 11 in a long
immediate or register form instruction. */
#define TIC80_OPERAND_SCALED (1 << 9)
/* This operand is a floating point value */
#define TIC80_OPERAND_FLOAT (1 << 10)
/* This operand is an byte offset from a base relocation. The lower
two bits of the final relocated address are ignored when the value is
written to the program counter. */
#define TIC80_OPERAND_BASEREL (1 << 11)
/* This operand is an "endmask" field for a shift instruction.
It is treated special in that it can have values of 0-32,
where 0 and 32 result in the same instruction. The assembler
must be able to accept both endmask values. This disassembler
has no way of knowing from the instruction which value was
given at assembly time, so it just uses '0'. */
#define TIC80_OPERAND_ENDMASK (1 << 12)
/* This operand is one of the 32 general purpose registers.
The disassembler prints these with a leading 'r'. */
#define TIC80_OPERAND_GPR (1 << 27)
/* This operand is a floating point accumulator register.
The disassembler prints these with a leading 'a'. */
#define TIC80_OPERAND_FPA ( 1 << 28)
/* This operand is a control register number, either numeric or
symbolic (like "EIF", "EPC", etc).
The disassembler prints these symbolically. */
#define TIC80_OPERAND_CR (1 << 29)
/* This operand is a condition code, either numeric or
symbolic (like "eq0.b", "ne0.w", etc).
The disassembler prints these symbolically. */
#define TIC80_OPERAND_CC (1 << 30)
/* This operand is a bit number, either numeric or
symbolic (like "eq.b", "or.f", etc).
The disassembler prints these symbolically.
Note that they appear in the instruction in 1's complement relative
to the values given in the manual. */
#define TIC80_OPERAND_BITNUM (1 << 31)
/* This mask is used to strip operand bits from an int that contains
both operand bits and a numeric value in the lsbs. */
#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
/* Flag bits for the struct tic80_opcode flags field. */
#define TIC80_VECTOR 01 /* Is a vector instruction */
#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */
/* The opcodes library contains a table that allows translation from predefined
symbol names to numeric values, and vice versa. */
/* Structure to hold information about predefined symbols. */
struct predefined_symbol
{
char *name; /* name to recognize */
int value;
};
#define PDS_NAME(pdsp) ((pdsp) -> name)
#define PDS_VALUE(pdsp) ((pdsp) -> value)
/* Translation array. */
extern const struct predefined_symbol tic80_predefined_symbols[];
/* How many members in the array. */
extern const int tic80_num_predefined_symbols;
/* Translate value to symbolic name. */
const char *tic80_value_to_symbol (int val, int class);
/* Translate symbolic name to value. */
int tic80_symbol_to_value (char *name, int class);
const struct predefined_symbol *tic80_next_predefined_symbol
(const struct predefined_symbol *);
#endif /* TIC80_H */

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/* v850.h -- Header file for NEC V850 opcode table
Copyright 1996-2013 Free Software Foundation, Inc.
Written by J.T. Conklin, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING3. If not, write to the Free
Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef V850_H
#define V850_H
/* The opcode table is an array of struct v850_opcode. */
struct v850_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned long opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned long mask;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
unsigned char operands[8];
/* Which (if any) operand is a memory operand. */
unsigned int memop;
/* Target processor(s). A bit field of processors which support
this instruction. Note a bit field is used as some instructions
are available on multiple, different processor types, whereas
other instructions are only available on one specific type. */
unsigned int processors;
};
/* Values for architecture number. */
#define arch_V850 0
#define arch_V850E (arch_V850 + 1)
#define arch_V850E1 (arch_V850E + 1)
#define arch_V850E2 (arch_V850E1 + 1)
#define arch_V850E2V3 (arch_V850E2 + 1)
#define arch_V850E3V5 (arch_V850E2V3 + 1)
#define arch_separator (arch_V850E3V5 + 1)
#define opt_EXTENSION (arch_separator)
#define opt_ALIAS (opt_EXTENSION + 1)
/* Values for the processors field in the v850_opcode structure. */
#define PROCESSOR_V850 (1 << (arch_V850)) /* Just the V850. */
#define PROCESSOR_V850E (1 << (arch_V850E)) /* Just the V850E. */
#define PROCESSOR_V850E1 (1 << (arch_V850E1)) /* Just the V850E1. */
#define PROCESSOR_V850E2 (1 << (arch_V850E2)) /* Just the V850E2. */
#define PROCESSOR_V850E2V3 (1 << (arch_V850E2V3)) /* Just the V850E2V3. */
#define PROCESSOR_V850E3V5 (1 << (arch_V850E3V5)) /* Just the V850E3V5. */
/* UPPERS */
#define PROCESSOR_V850E3V5_UP (PROCESSOR_V850E3V5)
#define PROCESSOR_V850E2V3_UP (PROCESSOR_V850E2V3 | PROCESSOR_V850E3V5_UP)
#define PROCESSOR_V850E2_UP (PROCESSOR_V850E2 | PROCESSOR_V850E2V3_UP)
#define PROCESSOR_V850E_UP (PROCESSOR_V850E | PROCESSOR_V850E1 | PROCESSOR_V850E2_UP)
#define PROCESSOR_ALL (PROCESSOR_V850 | PROCESSOR_V850E_UP)
#define PROCESSOR_MASK (PROCESSOR_ALL)
#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */
#define PROCESSOR_UNKNOWN ~(PROCESSOR_MASK)
/* OPTIONS */
#define PROCESSOR_OPTION_EXTENSION (1 << (opt_EXTENSION)) /* Enable extension opcodes. */
#define PROCESSOR_OPTION_ALIAS (1 << (opt_ALIAS)) /* Enable alias opcodes. */
#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct v850_opcode v850_opcodes[];
extern const int v850_num_opcodes;
/* The operands table is an array of struct v850_operand. */
struct v850_operand
{
/* The number of bits in the operand. */
/* If this value is -1 then the operand's bits are in a discontinous
distribution in the instruction. */
int bits;
/* (bits >= 0): How far the operand is left shifted in the instruction. */
/* (bits == -1): Bit mask of the bits in the operand. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (* insert)
(unsigned long instruction, long op, const char ** errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
if (o->flags & V850_OPERAND_SIGNED)
op = (op << (32 - o->bits)) >> (32 - o->bits);
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
unsigned long (* extract) (unsigned long instruction, int * invalid);
/* One bit syntax flags. */
int flags;
int default_reloc;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the v850_opcodes table. */
extern const struct v850_operand v850_operands[];
/* Values defined for the flags field of a struct v850_operand. */
/* This operand names a general purpose register. */
#define V850_OPERAND_REG 0x01
/* This operand is the ep register. */
#define V850_OPERAND_EP 0x02
/* This operand names a system register. */
#define V850_OPERAND_SRG 0x04
/* Prologue eilogue type instruction, V850E specific. */
#define V850E_OPERAND_REG_LIST 0x08
/* This operand names a condition code used in the setf instruction. */
#define V850_OPERAND_CC 0x10
#define V850_OPERAND_FLOAT_CC 0x20
/* This operand names a vector purpose register. */
#define V850_OPERAND_VREG 0x40
/* 16 bit immediate follows instruction, V850E specific. */
#define V850E_IMMEDIATE16 0x80
/* hi16 bit immediate follows instruction, V850E specific. */
#define V850E_IMMEDIATE16HI 0x100
/* 23 bit immediate follows instruction, V850E specific. */
#define V850E_IMMEDIATE23 0x200
/* 32 bit immediate follows instruction, V850E specific. */
#define V850E_IMMEDIATE32 0x400
/* This is a relaxable operand. Only used for D9->D22 branch relaxing
right now. We may need others in the future (or maybe handle them like
promoted operands on the mn10300?). */
#define V850_OPERAND_RELAX 0x800
/* This operand takes signed values. */
#define V850_OPERAND_SIGNED 0x1000
/* This operand is a displacement. */
#define V850_OPERAND_DISP 0x2000
/* This operand is a PC displacement. */
#define V850_PCREL 0x4000
/* The register specified must be even number. */
#define V850_REG_EVEN 0x8000
/* The register specified must not be r0. */
#define V850_NOT_R0 0x20000
/* The register specified must not be 0. */
#define V850_NOT_IMM0 0x40000
/* The condition code must not be SA CONDITION. */
#define V850_NOT_SA 0x80000
/* The operand has '!' prefix. */
#define V850_OPERAND_BANG 0x100000
/* The operand has '%' prefix. */
#define V850_OPERAND_PERCENT 0x200000
/* This operand is a cache oparation. */
#define V850_OPERAND_CACHEOP 0x400000
/* This operand is a prefetch oparation. */
#define V850_OPERAND_PREFOP 0x800000
/* A PC-relative displacement where a positive value indicates a backwards displacement. */
#define V850_INVERSE_PCREL 0x1000000
extern int v850_msg_is_out_of_range (const char *);
#endif /* V850_H */

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/* Vax opcde list.
Copyright 1989, 1991, 1992, 1995, 2010 Free Software Foundation, Inc.
This file is part of GDB and GAS.
GDB and GAS are free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GDB and GAS are distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GDB or GAS; see the file COPYING3. If not, write to
the Free Software Foundation, 51 Franklin Street - Fifth Floor,
Boston, MA 02110-1301, USA. */
#ifndef vax_opcodeT
#define vax_opcodeT int
#endif /* no vax_opcodeT */
struct vot_wot /* vax opcode table: wot to do with this */
/* particular opcode */
{
const char *args; /* how to compile said opcode */
vax_opcodeT code; /* op-code (may be > 8 bits!) */
};
struct vot /* vax opcode text */
{
const char *name; /* opcode name: lowercase string [key] */
struct vot_wot detail; /* rest of opcode table [datum] */
};
#define vot_how args
#define vot_code code
#define vot_detail detail
#define vot_name name
static const struct vot
votstrs[] =
{
{ "halt", {"", 0x00 } },
{ "nop", {"", 0x01 } },
{ "rei", {"", 0x02 } },
{ "bpt", {"", 0x03 } },
{ "ret", {"", 0x04 } },
{ "rsb", {"", 0x05 } },
{ "ldpctx", {"", 0x06 } },
{ "svpctx", {"", 0x07 } },
{ "cvtps", {"rwabrwab", 0x08 } },
{ "cvtsp", {"rwabrwab", 0x09 } },
{ "index", {"rlrlrlrlrlwl", 0x0a } },
{ "crc", {"abrlrwab", 0x0b } },
{ "prober", {"rbrwab", 0x0c } },
{ "probew", {"rbrwab", 0x0d } },
{ "insque", {"abab", 0x0e } },
{ "remque", {"abwl", 0x0f } },
{ "bsbb", {"bb", 0x10 } },
{ "brb", {"bb", 0x11 } },
{ "bneq", {"bb", 0x12 } },
{ "bnequ", {"bb", 0x12 } },
{ "beql", {"bb", 0x13 } },
{ "beqlu", {"bb", 0x13 } },
{ "bgtr", {"bb", 0x14 } },
{ "bleq", {"bb", 0x15 } },
{ "jsb", {"ab", 0x16 } },
{ "jmp", {"ab", 0x17 } },
{ "bgeq", {"bb", 0x18 } },
{ "blss", {"bb", 0x19 } },
{ "bgtru", {"bb", 0x1a } },
{ "blequ", {"bb", 0x1b } },
{ "bvc", {"bb", 0x1c } },
{ "bvs", {"bb", 0x1d } },
{ "bcc", {"bb", 0x1e } },
{ "bgequ", {"bb", 0x1e } },
{ "blssu", {"bb", 0x1f } },
{ "bcs", {"bb", 0x1f } },
{ "addp4", {"rwabrwab", 0x20 } },
{ "addp6", {"rwabrwabrwab", 0x21 } },
{ "subp4", {"rwabrwab", 0x22 } },
{ "subp6", {"rwabrwabrwab", 0x23 } },
{ "cvtpt", {"rwababrwab", 0x24 } },
{ "mulp", {"rwabrwabrwab", 0x25 } },
{ "cvttp", {"rwababrwab", 0x26 } },
{ "divp", {"rwabrwabrwab", 0x27 } },
{ "movc3", {"rwabab", 0x28 } },
{ "cmpc3", {"rwabab", 0x29 } },
{ "scanc", {"rwababrb", 0x2a } },
{ "spanc", {"rwababrb", 0x2b } },
{ "movc5", {"rwabrbrwab", 0x2c } },
{ "cmpc5", {"rwabrbrwab", 0x2d } },
{ "movtc", {"rwabrbabrwab", 0x2e } },
{ "movtuc", {"rwabrbabrwab", 0x2f } },
{ "bsbw", {"bw", 0x30 } },
{ "brw", {"bw", 0x31 } },
{ "cvtwl", {"rwwl", 0x32 } },
{ "cvtwb", {"rwwb", 0x33 } },
{ "movp", {"rwabab", 0x34 } },
{ "cmpp3", {"rwabab", 0x35 } },
{ "cvtpl", {"rwabwl", 0x36 } },
{ "cmpp4", {"rwabrwab", 0x37 } },
{ "editpc", {"rwababab", 0x38 } },
{ "matchc", {"rwabrwab", 0x39 } },
{ "locc", {"rbrwab", 0x3a } },
{ "skpc", {"rbrwab", 0x3b } },
{ "movzwl", {"rwwl", 0x3c } },
{ "acbw", {"rwrwmwbw", 0x3d } },
{ "movaw", {"awwl", 0x3e } },
{ "pushaw", {"aw", 0x3f } },
{ "addf2", {"rfmf", 0x40 } },
{ "addf3", {"rfrfwf", 0x41 } },
{ "subf2", {"rfmf", 0x42 } },
{ "subf3", {"rfrfwf", 0x43 } },
{ "mulf2", {"rfmf", 0x44 } },
{ "mulf3", {"rfrfwf", 0x45 } },
{ "divf2", {"rfmf", 0x46 } },
{ "divf3", {"rfrfwf", 0x47 } },
{ "cvtfb", {"rfwb", 0x48 } },
{ "cvtfw", {"rfww", 0x49 } },
{ "cvtfl", {"rfwl", 0x4a } },
{ "cvtrfl", {"rfwl", 0x4b } },
{ "cvtbf", {"rbwf", 0x4c } },
{ "cvtwf", {"rwwf", 0x4d } },
{ "cvtlf", {"rlwf", 0x4e } },
{ "acbf", {"rfrfmfbw", 0x4f } },
{ "movf", {"rfwf", 0x50 } },
{ "cmpf", {"rfrf", 0x51 } },
{ "mnegf", {"rfwf", 0x52 } },
{ "tstf", {"rf", 0x53 } },
{ "emodf", {"rfrbrfwlwf", 0x54 } },
{ "polyf", {"rfrwab", 0x55 } },
{ "cvtfd", {"rfwd", 0x56 } },
/* opcode 57 is not defined yet */
{ "adawi", {"rwmw", 0x58 } },
/* opcode 59 is not defined yet */
/* opcode 5a is not defined yet */
/* opcode 5b is not defined yet */
{ "insqhi", {"abaq", 0x5c } },
{ "insqti", {"abaq", 0x5d } },
{ "remqhi", {"aqwl", 0x5e } },
{ "remqti", {"aqwl", 0x5f } },
{ "addd2", {"rdmd", 0x60 } },
{ "addd3", {"rdrdwd", 0x61 } },
{ "subd2", {"rdmd", 0x62 } },
{ "subd3", {"rdrdwd", 0x63 } },
{ "muld2", {"rdmd", 0x64 } },
{ "muld3", {"rdrdwd", 0x65 } },
{ "divd2", {"rdmd", 0x66 } },
{ "divd3", {"rdrdwd", 0x67 } },
{ "cvtdb", {"rdwb", 0x68 } },
{ "cvtdw", {"rdww", 0x69 } },
{ "cvtdl", {"rdwl", 0x6a } },
{ "cvtrdl", {"rdwl", 0x6b } },
{ "cvtbd", {"rbwd", 0x6c } },
{ "cvtwd", {"rwwd", 0x6d } },
{ "cvtld", {"rlwd", 0x6e } },
{ "acbd", {"rdrdmdbw", 0x6f } },
{ "movd", {"rdwd", 0x70 } },
{ "cmpd", {"rdrd", 0x71 } },
{ "mnegd", {"rdwd", 0x72 } },
{ "tstd", {"rd", 0x73 } },
{ "emodd", {"rdrbrdwlwd", 0x74 } },
{ "polyd", {"rdrwab", 0x75 } },
{ "cvtdf", {"rdwf", 0x76 } },
/* opcode 77 is not defined yet */
{ "ashl", {"rbrlwl", 0x78 } },
{ "ashq", {"rbrqwq", 0x79 } },
{ "emul", {"rlrlrlwq", 0x7a } },
{ "ediv", {"rlrqwlwl", 0x7b } },
{ "clrd", {"wd", 0x7c } },
{ "clrg", {"wg", 0x7c } },
{ "clrq", {"wd", 0x7c } },
{ "movq", {"rqwq", 0x7d } },
{ "movaq", {"aqwl", 0x7e } },
{ "movad", {"adwl", 0x7e } },
{ "pushaq", {"aq", 0x7f } },
{ "pushad", {"ad", 0x7f } },
{ "addb2", {"rbmb", 0x80 } },
{ "addb3", {"rbrbwb", 0x81 } },
{ "subb2", {"rbmb", 0x82 } },
{ "subb3", {"rbrbwb", 0x83 } },
{ "mulb2", {"rbmb", 0x84 } },
{ "mulb3", {"rbrbwb", 0x85 } },
{ "divb2", {"rbmb", 0x86 } },
{ "divb3", {"rbrbwb", 0x87 } },
{ "bisb2", {"rbmb", 0x88 } },
{ "bisb3", {"rbrbwb", 0x89 } },
{ "bicb2", {"rbmb", 0x8a } },
{ "bicb3", {"rbrbwb", 0x8b } },
{ "xorb2", {"rbmb", 0x8c } },
{ "xorb3", {"rbrbwb", 0x8d } },
{ "mnegb", {"rbwb", 0x8e } },
{ "caseb", {"rbrbrb", 0x8f } },
{ "movb", {"rbwb", 0x90 } },
{ "cmpb", {"rbrb", 0x91 } },
{ "mcomb", {"rbwb", 0x92 } },
{ "bitb", {"rbrb", 0x93 } },
{ "clrb", {"wb", 0x94 } },
{ "tstb", {"rb", 0x95 } },
{ "incb", {"mb", 0x96 } },
{ "decb", {"mb", 0x97 } },
{ "cvtbl", {"rbwl", 0x98 } },
{ "cvtbw", {"rbww", 0x99 } },
{ "movzbl", {"rbwl", 0x9a } },
{ "movzbw", {"rbww", 0x9b } },
{ "rotl", {"rbrlwl", 0x9c } },
{ "acbb", {"rbrbmbbw", 0x9d } },
{ "movab", {"abwl", 0x9e } },
{ "pushab", {"ab", 0x9f } },
{ "addw2", {"rwmw", 0xa0 } },
{ "addw3", {"rwrwww", 0xa1 } },
{ "subw2", {"rwmw", 0xa2 } },
{ "subw3", {"rwrwww", 0xa3 } },
{ "mulw2", {"rwmw", 0xa4 } },
{ "mulw3", {"rwrwww", 0xa5 } },
{ "divw2", {"rwmw", 0xa6 } },
{ "divw3", {"rwrwww", 0xa7 } },
{ "bisw2", {"rwmw", 0xa8 } },
{ "bisw3", {"rwrwww", 0xa9 } },
{ "bicw2", {"rwmw", 0xaa } },
{ "bicw3", {"rwrwww", 0xab } },
{ "xorw2", {"rwmw", 0xac } },
{ "xorw3", {"rwrwww", 0xad } },
{ "mnegw", {"rwww", 0xae } },
{ "casew", {"rwrwrw", 0xaf } },
{ "movw", {"rwww", 0xb0 } },
{ "cmpw", {"rwrw", 0xb1 } },
{ "mcomw", {"rwww", 0xb2 } },
{ "bitw", {"rwrw", 0xb3 } },
{ "clrw", {"ww", 0xb4 } },
{ "tstw", {"rw", 0xb5 } },
{ "incw", {"mw", 0xb6 } },
{ "decw", {"mw", 0xb7 } },
{ "bispsw", {"rw", 0xb8 } },
{ "bicpsw", {"rw", 0xb9 } },
{ "popr", {"rw", 0xba } },
{ "pushr", {"rw", 0xbb } },
{ "chmk", {"rw", 0xbc } },
{ "chme", {"rw", 0xbd } },
{ "chms", {"rw", 0xbe } },
{ "chmu", {"rw", 0xbf } },
{ "addl2", {"rlml", 0xc0 } },
{ "addl3", {"rlrlwl", 0xc1 } },
{ "subl2", {"rlml", 0xc2 } },
{ "subl3", {"rlrlwl", 0xc3 } },
{ "mull2", {"rlml", 0xc4 } },
{ "mull3", {"rlrlwl", 0xc5 } },
{ "divl2", {"rlml", 0xc6 } },
{ "divl3", {"rlrlwl", 0xc7 } },
{ "bisl2", {"rlml", 0xc8 } },
{ "bisl3", {"rlrlwl", 0xc9 } },
{ "bicl2", {"rlml", 0xca } },
{ "bicl3", {"rlrlwl", 0xcb } },
{ "xorl2", {"rlml", 0xcc } },
{ "xorl3", {"rlrlwl", 0xcd } },
{ "mnegl", {"rlwl", 0xce } },
{ "casel", {"rlrlrl", 0xcf } },
{ "movl", {"rlwl", 0xd0 } },
{ "cmpl", {"rlrl", 0xd1 } },
{ "mcoml", {"rlwl", 0xd2 } },
{ "bitl", {"rlrl", 0xd3 } },
{ "clrf", {"wf", 0xd4 } },
{ "clrl", {"wl", 0xd4 } },
{ "tstl", {"rl", 0xd5 } },
{ "incl", {"ml", 0xd6 } },
{ "decl", {"ml", 0xd7 } },
{ "adwc", {"rlml", 0xd8 } },
{ "sbwc", {"rlml", 0xd9 } },
{ "mtpr", {"rlrl", 0xda } },
{ "mfpr", {"rlwl", 0xdb } },
{ "movpsl", {"wl", 0xdc } },
{ "pushl", {"rl", 0xdd } },
{ "moval", {"alwl", 0xde } },
{ "movaf", {"afwl", 0xde } },
{ "pushal", {"al", 0xdf } },
{ "pushaf", {"af", 0xdf } },
{ "bbs", {"rlvbbb", 0xe0 } },
{ "bbc", {"rlvbbb", 0xe1 } },
{ "bbss", {"rlvbbb", 0xe2 } },
{ "bbcs", {"rlvbbb", 0xe3 } },
{ "bbsc", {"rlvbbb", 0xe4 } },
{ "bbcc", {"rlvbbb", 0xe5 } },
{ "bbssi", {"rlvbbb", 0xe6 } },
{ "bbcci", {"rlvbbb", 0xe7 } },
{ "blbs", {"rlbb", 0xe8 } },
{ "blbc", {"rlbb", 0xe9 } },
{ "ffs", {"rlrbvbwl", 0xea } },
{ "ffc", {"rlrbvbwl", 0xeb } },
{ "cmpv", {"rlrbvbrl", 0xec } },
{ "cmpzv", {"rlrbvbrl", 0xed } },
{ "extv", {"rlrbvbwl", 0xee } },
{ "extzv", {"rlrbvbwl", 0xef } },
{ "insv", {"rlrlrbvb", 0xf0 } },
{ "acbl", {"rlrlmlbw", 0xf1 } },
{ "aoblss", {"rlmlbb", 0xf2 } },
{ "aobleq", {"rlmlbb", 0xf3 } },
{ "sobgeq", {"mlbb", 0xf4 } },
{ "sobgtr", {"mlbb", 0xf5 } },
{ "cvtlb", {"rlwb", 0xf6 } },
{ "cvtlw", {"rlww", 0xf7 } },
{ "ashp", {"rbrwabrbrwab", 0xf8 } },
{ "cvtlp", {"rlrwab", 0xf9 } },
{ "callg", {"abab", 0xfa } },
{ "calls", {"rlab", 0xfb } },
{ "xfc", {"", 0xfc } },
/* undefined opcodes here */
{ "cvtdh", {"rdwh", 0x32fd } },
{ "cvtgf", {"rgwh", 0x33fd } },
{ "addg2", {"rgmg", 0x40fd } },
{ "addg3", {"rgrgwg", 0x41fd } },
{ "subg2", {"rgmg", 0x42fd } },
{ "subg3", {"rgrgwg", 0x43fd } },
{ "mulg2", {"rgmg", 0x44fd } },
{ "mulg3", {"rgrgwg", 0x45fd } },
{ "divg2", {"rgmg", 0x46fd } },
{ "divg3", {"rgrgwg", 0x47fd } },
{ "cvtgb", {"rgwb", 0x48fd } },
{ "cvtgw", {"rgww", 0x49fd } },
{ "cvtgl", {"rgwl", 0x4afd } },
{ "cvtrgl", {"rgwl", 0x4bfd } },
{ "cvtbg", {"rbwg", 0x4cfd } },
{ "cvtwg", {"rwwg", 0x4dfd } },
{ "cvtlg", {"rlwg", 0x4efd } },
{ "acbg", {"rgrgmgbw", 0x4ffd } },
{ "movg", {"rgwg", 0x50fd } },
{ "cmpg", {"rgrg", 0x51fd } },
{ "mnegg", {"rgwg", 0x52fd } },
{ "tstg", {"rg", 0x53fd } },
{ "emodg", {"rgrwrgwlwg", 0x54fd } },
{ "polyg", {"rgrwab", 0x55fd } },
{ "cvtgh", {"rgwh", 0x56fd } },
/* undefined opcodes here */
{ "addh2", {"rhmh", 0x60fd } },
{ "addh3", {"rhrhwh", 0x61fd } },
{ "subh2", {"rhmh", 0x62fd } },
{ "subh3", {"rhrhwh", 0x63fd } },
{ "mulh2", {"rhmh", 0x64fd } },
{ "mulh3", {"rhrhwh", 0x65fd } },
{ "divh2", {"rhmh", 0x66fd } },
{ "divh3", {"rhrhwh", 0x67fd } },
{ "cvthb", {"rhwb", 0x68fd } },
{ "cvthw", {"rhww", 0x69fd } },
{ "cvthl", {"rhwl", 0x6afd } },
{ "cvtrhl", {"rhwl", 0x6bfd } },
{ "cvtbh", {"rbwh", 0x6cfd } },
{ "cvtwh", {"rwwh", 0x6dfd } },
{ "cvtlh", {"rlwh", 0x6efd } },
{ "acbh", {"rhrhmhbw", 0x6ffd } },
{ "movh", {"rhwh", 0x70fd } },
{ "cmph", {"rhrh", 0x71fd } },
{ "mnegh", {"rhwh", 0x72fd } },
{ "tsth", {"rh", 0x73fd } },
{ "emodh", {"rhrwrhwlwh", 0x74fd } },
{ "polyh", {"rhrwab", 0x75fd } },
{ "cvthg", {"rhwg", 0x76fd } },
/* undefined opcodes here */
{ "clrh", {"wh", 0x7cfd } },
{ "clro", {"wo", 0x7cfd } },
{ "movo", {"rowo", 0x7dfd } },
{ "movah", {"ahwl", 0x7efd } },
{ "movao", {"aowl", 0x7efd } },
{ "pushah", {"ah", 0x7ffd } },
{ "pushao", {"ao", 0x7ffd } },
/* undefined opcodes here */
{ "cvtfh", {"rfwh", 0x98fd } },
{ "cvtfg", {"rfwg", 0x99fd } },
/* undefined opcodes here */
{ "cvthf", {"rhwf", 0xf6fd } },
{ "cvthd", {"rhwd", 0xf7fd } },
/* undefined opcodes here */
{ "bugl", {"rl", 0xfdff } },
{ "bugw", {"rw", 0xfeff } },
/* undefined opcodes here */
{ "", {"", 0} } /* empty is end sentinel */
}; /* votstrs */
/* end: vax.opcode.h */

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contrib/toolchain/binutils/include/opcode/xgate.h Normal file
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/* xgate.h -- Freescale XGATE opcode list
Copyright 2010, 2011, 2012 Free Software Foundation, Inc.
Written by Sean Keys (skeys@ipdatasys.com)
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
#ifndef _OPCODE_XGATE_H
#define _OPCODE_XGATE_H
/* XGATE CCR flag definitions. */
#define XGATE_N_BIT 0x08 /* XGN - Sign Flag */
#define XGATE_Z_BIT 0x04 /* XGZ - Zero Flag */
#define XGATE_V_BIT 0x02 /* XGV - Overflow Flag */
#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */
/* Access Detail Notation
V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
r — 8-bit data read: lasts for at least one RISC core cycle
R — 16-bit data read: lasts for at least one RISC core cycle
w — 8-bit data write: lasts for at least one RISC core cycle
W — 16-bit data write: lasts for at least one RISC core cycle
A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
f — Free cycle: no read or write, lasts for one RISC core cycles. */
#define XGATE_CYCLE_V 0x01
#define XGATE_CYCLE_P 0x02
#define XGATE_CYCLE_r 0x04
#define XGATE_CYCLE_R 0x08
#define XGATE_CYCLE_w 0x10
#define XGATE_CYCLE_W 0x20
#define XGATE_CYCLE_A 0x40
#define XGATE_CYCLE_f 0x80
/* Opcode format abbreviations. */
#define XG_INH 0x0001 /* Inherent. */
#define XG_I 0x0002 /* 3-bit immediate address. */
#define XG_R_I 0x0004 /* Register followed by 4/8-bit immediate value. */
#define XG_R_R 0x0008 /* Register followed by a register. */
#define XG_R_R_R 0x0010 /* Register followed by two registers. */
#define XG_R 0x0020 /* Single register. */
#define XG_PC 0x0040 /* PC relative 10 or 11 bit. */
#define XG_R_C 0x0080 /* General register followed by ccr register. */
#define XG_C_R 0x0100 /* CCR register followed by a general register. */
#define XG_R_P 0x0200 /* General register followed by pc register. */
#define XG_R_R_I 0x0400 /* Two general registers followed by an immediate value. */
#define XG_PCREL 0x0800 /* Immediate value that is relative to the current pc. */
/* XGATE operand formats as stored in the XGATE_opcode table.
They are only used by GAS to recognize operands. */
#define XGATE_OP_INH ""
#define XGATE_OP_TRI "r,r,r"
#define XGATE_OP_DYA "r,r"
#define XGATE_OP_IMM16 "r,if"
#define XGATE_OP_IMM8 "r,i8"
#define XGATE_OP_IMM4 "r,i4"
#define XGATE_OP_IMM3 "i3"
#define XGATE_OP_MON "r"
#define XGATE_OP_MON_R_C "r,c"
#define XGATE_OP_MON_C_R "c,r"
#define XGATE_OP_MON_R_P "r,p"
#define XGATE_OP_IDR "r,r,+"
#define XGATE_OP_IDO5 "r,r,i5"
#define XGATE_OP_REL9 "b9"
#define XGATE_OP_REL10 "ba"
#define XGATE_OP_DYA_MON "=r"
/* Macro definitions. */
#define XGATE_OP_IMM16mADD "r,if; addl addh"
#define XGATE_OP_IMM16mAND "r,if; andl andh"
#define XGATE_OP_IMM16mCPC "r,if; cmpl cpch"
#define XGATE_OP_IMM16mSUB "r,if; subl subh"
#define XGATE_OP_IMM16mLDW "r,if; ldl ldh"
/* CPU variant identification. */
#define XGATE_V1 0x1
#define XGATE_V2 0x2
#define XGATE_V3 0x4
/* Max opcodes per opcode handle. */
#define MAX_OPCODES 0x05
#define MAX_DETECT_CHARS 0x10
/* The opcode table definitions. */
struct xgate_opcode
{
char * name; /* Op-code name. */
char * constraints; /* Constraint chars. */
char * format; /* Bit definitions. */
unsigned int sh_format; /* Shorthand format mask. */
unsigned int size; /* Opcode size in bytes. */
unsigned int bin_opcode; /* Binary opcode with operands masked off. */
unsigned char cycles_min; /* Minimum cpu cycles needed. */
unsigned char cycles_max; /* Maximum cpu cycles needed. */
unsigned char set_flags_mask; /* CCR flags set. */
unsigned char clr_flags_mask; /* CCR flags cleared. */
unsigned char chg_flags_mask; /* CCR flags changed. */
unsigned char arch; /* CPU variant. */
};
/* The opcode table. The table contains all the opcodes (all pages).
You can't rely on the order. */
extern const struct xgate_opcode xgate_opcodes[];
extern const int xgate_num_opcodes;
#endif /* _OPCODE_XGATE_H */