forked from KolibriOS/kolibrios
196 lines
6.2 KiB
C
196 lines
6.2 KiB
C
#ifndef _INTEL_DRIVER_H_
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#define _INTEL_DRIVER_H_
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#include <stddef.h>
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//#include <pthread.h>
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//#include <signal.h>
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#include <stdbool.h>
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#include <drm.h>
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#include <i915_drm.h>
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#include <intel_bufmgr.h>
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#include <va/va_backend.h>
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#include "va_backend_compat.h"
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#include "intel_compiler.h"
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#define BATCH_SIZE 0x80000
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#define BATCH_RESERVED 0x10
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#define CMD_MI (0x0 << 29)
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#define CMD_2D (0x2 << 29)
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#define CMD_3D (0x3 << 29)
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#define MI_NOOP (CMD_MI | 0)
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#define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
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#define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
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#define MI_FLUSH (CMD_MI | (0x4 << 23))
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#define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
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#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
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#define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
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#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
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#define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
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#define XY_COLOR_BLT_WRITE_RGB (1 << 20)
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#define XY_COLOR_BLT_DST_TILED (1 << 11)
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#define GEN8_XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x05)
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/* BR13 */
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#define BR13_8 (0x0 << 24)
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#define BR13_565 (0x1 << 24)
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#define BR13_1555 (0x2 << 24)
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#define BR13_8888 (0x3 << 24)
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#define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
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#define CMD_PIPE_CONTROL_CS_STALL (1 << 20)
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#define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
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#define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
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#define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
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#define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
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#define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
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#define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
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#define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
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#define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
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#define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
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#define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
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#define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
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#define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
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#define CMD_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1)
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#define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
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struct intel_batchbuffer;
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#define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
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#define IS_ALIGNED(i, n) (((i) & ((n)-1)) == 0)
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
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#define Bool int
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#define True 1
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#define False 0
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extern uint32_t g_intel_debug_option_flags;
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#define VA_INTEL_DEBUG_OPTION_ASSERT (1 << 0)
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#define VA_INTEL_DEBUG_OPTION_BENCH (1 << 1)
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#define ASSERT_RET(value, fail_ret) do { \
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if (!(value)) { \
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if (g_intel_debug_option_flags & VA_INTEL_DEBUG_OPTION_ASSERT) \
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assert(value); \
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return fail_ret; \
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} \
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} while (0)
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#define SET_BLOCKED_SIGSET() do { \
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sigset_t bl_mask; \
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sigfillset(&bl_mask); \
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sigdelset(&bl_mask, SIGFPE); \
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sigdelset(&bl_mask, SIGILL); \
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sigdelset(&bl_mask, SIGSEGV); \
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sigdelset(&bl_mask, SIGBUS); \
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sigdelset(&bl_mask, SIGKILL); \
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pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
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} while (0)
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#define RESTORE_BLOCKED_SIGSET() do { \
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pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
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} while (0)
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#define PPTHREAD_MUTEX_LOCK() do { \
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SET_BLOCKED_SIGSET(); \
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pthread_mutex_lock(&intel->ctxmutex); \
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} while (0)
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#define PPTHREAD_MUTEX_UNLOCK() do { \
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pthread_mutex_unlock(&intel->ctxmutex); \
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RESTORE_BLOCKED_SIGSET(); \
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} while (0)
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#define WARN_ONCE(...) do { \
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static int g_once = 1; \
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if (g_once) { \
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g_once = 0; \
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printf("WARNING: " __VA_ARGS__); \
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} \
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} while (0)
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struct intel_device_info
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{
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int gen;
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int gt;
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unsigned int urb_size;
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unsigned int max_wm_threads;
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unsigned int is_g4x : 1; /* gen4 */
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unsigned int is_ivybridge : 1; /* gen7 */
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unsigned int is_baytrail : 1; /* gen7 */
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unsigned int is_haswell : 1; /* gen7 */
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unsigned int is_cherryview : 1; /* gen8 */
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};
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struct intel_driver_data
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{
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int fd;
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int device_id;
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int revision;
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int dri2Enabled;
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// sigset_t sa_mask;
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// pthread_mutex_t ctxmutex;
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int locked;
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dri_bufmgr *bufmgr;
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unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
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unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
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unsigned int has_blt : 1; /* Flag: has BLT unit? */
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unsigned int has_vebox : 1; /* Flag: has VEBOX unit */
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const struct intel_device_info *device_info;
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};
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bool intel_driver_init(VADriverContextP ctx);
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void intel_driver_terminate(VADriverContextP ctx);
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static INLINE struct intel_driver_data *
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intel_driver_data(VADriverContextP ctx)
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{
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return (struct intel_driver_data *)ctx->pDriverData;
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}
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struct intel_region
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{
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int x;
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int y;
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unsigned int width;
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unsigned int height;
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unsigned int cpp;
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unsigned int pitch;
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unsigned int tiling;
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unsigned int swizzle;
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dri_bo *bo;
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};
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#define IS_G4X(device_info) (device_info->is_g4x)
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#define IS_IRONLAKE(device_info) (device_info->gen == 5)
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#define IS_GEN6(device_info) (device_info->gen == 6)
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#define IS_HASWELL(device_info) (device_info->is_haswell)
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#define IS_GEN7(device_info) (device_info->gen == 7)
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#define IS_CHERRYVIEW(device_info) (device_info->is_cherryview)
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#define IS_GEN8(device_info) (device_info->gen == 8)
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#endif /* _INTEL_DRIVER_H_ */
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