forked from KolibriOS/kolibrios
543 lines
19 KiB
PHP
543 lines
19 KiB
PHP
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2005-01-11 10:31 ******* Source: ATtiny26.xml ************
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn26def.inc"
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;* Title : Register/Bit Definitions for the ATtiny26
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;* Date : 2005-01-11
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;* Version : 2.14
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny26
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN26DEF_INC_
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#define _TN26DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny26
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#pragma AVRPART ADMIN PART_NAME ATtiny26
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x91
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.equ SIGNATURE_002 = 0x09
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#pragma AVRPART CORE CORE_VERSION V1
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#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SP = 0x3d
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.equ GIMSK = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK = 0x39
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.equ TIFR = 0x38
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0 = 0x33
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.equ TCNT0 = 0x32
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.equ OSCCAL = 0x31
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.equ TCCR1A = 0x30
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.equ TCCR1B = 0x2f
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.equ TCNT1 = 0x2e
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.equ OCR1A = 0x2d
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.equ OCR1B = 0x2c
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.equ OCR1C = 0x2b
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.equ PLLCSR = 0x29
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.equ WDTCR = 0x21
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.equ EEAR = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTA = 0x1b
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.equ DDRA = 0x1a
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.equ PINA = 0x19
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ USIDR = 0x0f
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.equ USISR = 0x0e
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.equ USICR = 0x0d
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.equ ACSR = 0x08
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.equ ADMUX = 0x07
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.equ ADCSRA = 0x06
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.equ ADCH = 0x05
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.equ ADCL = 0x04
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; ***** BIT DEFINITIONS **************************************************
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; ***** AD_CONVERTER *****************
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; ADMUX - The ADC multiplexer Selection Register
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.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
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.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
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.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
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.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
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.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
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.equ ADLAR = 5 ; Left Adjust Result
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.equ REFS0 = 6 ; Reference Selection Bit 0
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.equ REFS1 = 7 ; Reference Selection Bit 1
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; ADCSRA - The ADC Control and Status register
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.equ ADCSR = ADCSRA ; For compatibility
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.equ ADPS0 = 0 ; ADC Prescaler Select Bits
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.equ ADPS1 = 1 ; ADC Prescaler Select Bits
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.equ ADPS2 = 2 ; ADC Prescaler Select Bits
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.equ ADIE = 3 ; ADC Interrupt Enable
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.equ ADIF = 4 ; ADC Interrupt Flag
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.equ ADFR = 5 ; ADC Free Running Select
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.equ ADSC = 6 ; ADC Start Conversion
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.equ ADEN = 7 ; ADC Enable
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; ADCH - ADC Data Register High Byte
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.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
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.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
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.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
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.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
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.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
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.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
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.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
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.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
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; ADCL - ADC Data Register Low Byte
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.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
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.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
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.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
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.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
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.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
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.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
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.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
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.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACME = 2 ; Analog Comparator Multiplexer Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ ACD = 7 ; Analog Comparator Disable
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; ***** USI **************************
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; USIDR - USI Data Register
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.equ USIDR0 = 0 ; USI Data Register bit 0
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.equ USIDR1 = 1 ; USI Data Register bit 1
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.equ USIDR2 = 2 ; USI Data Register bit 2
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.equ USIDR3 = 3 ; USI Data Register bit 3
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.equ USIDR4 = 4 ; USI Data Register bit 4
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.equ USIDR5 = 5 ; USI Data Register bit 5
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.equ USIDR6 = 6 ; USI Data Register bit 6
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.equ USIDR7 = 7 ; USI Data Register bit 7
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; USISR - USI Status Register
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.equ USICNT0 = 0 ; USI Counter Value Bit 0
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.equ USICNT1 = 1 ; USI Counter Value Bit 1
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.equ USICNT2 = 2 ; USI Counter Value Bit 2
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.equ USICNT3 = 3 ; USI Counter Value Bit 3
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.equ USIDC = 4 ; Data Output Collision
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.equ USIPF = 5 ; Stop Condition Flag
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.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
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.equ USISIF = 7 ; Start Condition Interrupt Flag
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; USICR - USI Control Register
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.equ USITC = 0 ; Toggle Clock Port Pin
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.equ USICLK = 1 ; Clock Strobe
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.equ USICS0 = 2 ; USI Clock Source Select Bit 0
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.equ USICS1 = 3 ; USI Clock Source Select Bit 1
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.equ USIWM0 = 4 ; USI Wire Mode Bit 0
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.equ USIWM1 = 5 ; USI Wire Mode Bit 1
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.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
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.equ USISIE = 7 ; Start Condition Interrupt Enable
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; ***** PORTA ************************
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ; Port A Data Register bit 0
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ; Port A Data Register bit 1
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ; Port A Data Register bit 2
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.equ PA2 = 2 ; For compatibility
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.equ PORTA3 = 3 ; Port A Data Register bit 3
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.equ PA3 = 3 ; For compatibility
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.equ PORTA4 = 4 ; Port A Data Register bit 4
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.equ PA4 = 4 ; For compatibility
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.equ PORTA5 = 5 ; Port A Data Register bit 5
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.equ PA5 = 5 ; For compatibility
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.equ PORTA6 = 6 ; Port A Data Register bit 6
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.equ PA6 = 6 ; For compatibility
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.equ PORTA7 = 7 ; Port A Data Register bit 7
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.equ PA7 = 7 ; For compatibility
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; DDRA - Port A Data Direction Register
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.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
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.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
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.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
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.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
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.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
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.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
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.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
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.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ; Input Pins, Port A bit 0
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.equ PINA1 = 1 ; Input Pins, Port A bit 1
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.equ PINA2 = 2 ; Input Pins, Port A bit 2
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.equ PINA3 = 3 ; Input Pins, Port A bit 3
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.equ PINA4 = 4 ; Input Pins, Port A bit 4
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.equ PINA5 = 5 ; Input Pins, Port A bit 5
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.equ PINA6 = 6 ; Input Pins, Port A bit 6
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.equ PINA7 = 7 ; Input Pins, Port A bit 7
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; ***** PORTB ************************
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; PORTB - Port B Data Register
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.equ PORTB0 = 0 ; Port B Data Register bit 0
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ; Port B Data Register bit 1
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ; Port B Data Register bit 2
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ; Port B Data Register bit 3
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ; Port B Data Register bit 4
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ; Port B Data Register bit 5
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.equ PB5 = 5 ; For compatibility
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.equ PORTB6 = 6 ; Port B Data Register bit 6
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.equ PB6 = 6 ; For compatibility
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.equ PORTB7 = 7 ; Port B Data Register bit 7
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.equ PB7 = 7 ; For compatibility
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; DDRB - Port B Data Direction Register
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.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; ***** EEPROM ***********************
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; EEAR - EEPROM Read/Write Access
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.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEWE = 1 ; EEPROM Write Enable
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.equ EEMWE = 2 ; EEPROM Master Write Enable
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.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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; ***** WATCHDOG *********************
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; WDTCR - Watchdog Timer Control Register
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.equ WDTCSR = WDTCR ; For compatibility
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDCE = 4 ; Watchdog Change Enable
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.equ WDTOE = WDCE ; For compatibility
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; SP - Stack Pointer
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.equ SP0 = 0 ; Stack Pointer Bit 0
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.equ SP1 = 1 ; Stack Pointer Bit 1
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.equ SP2 = 2 ; Stack Pointer Bit 2
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.equ SP3 = 3 ; Stack Pointer Bit 3
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.equ SP4 = 4
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.equ SP5 = 5 ; Stack Pointer Bit 5
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.equ SP6 = 6 ; Stack Pointer Bit 6
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.equ SP7 = 7 ; Stack Pointer Bit 7
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; MCUCR - MCU Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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.equ SM0 = 3 ; Sleep Mode Select Bit 0
|
||
|
|
.equ SM1 = 4 ; Sleep Mode Select Bit 1
|
||
|
|
.equ SE = 5 ; Sleep Enable
|
||
|
|
.equ PUD = 6 ; Pull-up Disable
|
||
|
|
|
||
|
|
; MCUSR - MCU Status register
|
||
|
|
.equ PORF = 0 ; Power-On Reset Flag
|
||
|
|
.equ EXTRF = 1 ; External Reset Flag
|
||
|
|
.equ BORF = 2 ; Brown-out Reset Flag
|
||
|
|
.equ WDRF = 3 ; Watchdog Reset Flag
|
||
|
|
|
||
|
|
; OSCCAL - Status Register
|
||
|
|
.equ CAL0 = 0 ; Oscillator Calibration Value Bit 0
|
||
|
|
.equ OSCCAL0 = CAL0 ; For compatibility
|
||
|
|
.equ CAL1 = 1 ; Oscillator Calibration Value Bit 1
|
||
|
|
.equ OSCCAL1 = CAL1 ; For compatibility
|
||
|
|
.equ CAL2 = 2 ; Oscillator Calibration Value Bit 2
|
||
|
|
.equ OSCCAL2 = CAL2 ; For compatibility
|
||
|
|
.equ CAL3 = 3 ; Oscillator Calibration Value Bit 3
|
||
|
|
.equ OSCCAL3 = CAL3 ; For compatibility
|
||
|
|
.equ CAL4 = 4
|
||
|
|
.equ OSCCAL4 = CAL4 ; For compatibility
|
||
|
|
.equ CAL5 = 5 ; Oscillator Calibration Value Bit 5
|
||
|
|
.equ CAL6 = 6 ; Oscillator Calibration Value Bit 6
|
||
|
|
.equ CAL7 = 7 ; Oscillator Calibration Value Bit 7
|
||
|
|
|
||
|
|
|
||
|
|
; ***** TIMER_COUNTER_0 **************
|
||
|
|
; TIMSK - Timer/Counter Interrupt Mask Register
|
||
|
|
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
||
|
|
|
||
|
|
; TIFR - Timer/Counter Interrupt Flag register
|
||
|
|
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
||
|
|
|
||
|
|
; TCCR0 - Timer/Counter0 Control Register
|
||
|
|
.equ CS00 = 0 ; Clock Select0 bit 0
|
||
|
|
.equ CS01 = 1 ; Clock Select0 bit 1
|
||
|
|
.equ CS02 = 2 ; Clock Select0 bit 2
|
||
|
|
.equ PSR0 = 3 ; Prescaler Reset Timer/Counter0
|
||
|
|
|
||
|
|
; TCNT0 - Timer Counter 0
|
||
|
|
.equ TCNT00 = 0 ; Timer Counter 0 bit 0
|
||
|
|
.equ TCNT01 = 1 ; Timer Counter 0 bit 1
|
||
|
|
.equ TCNT02 = 2 ; Timer Counter 0 bit 2
|
||
|
|
.equ TCNT03 = 3 ; Timer Counter 0 bit 3
|
||
|
|
.equ TCNT04 = 4 ; Timer Counter 0 bit 4
|
||
|
|
.equ TCNT05 = 5 ; Timer Counter 0 bit 5
|
||
|
|
.equ TCNT06 = 6 ; Timer Counter 0 bit 6
|
||
|
|
.equ TCNT07 = 7 ; Timer Counter 0 bit 7
|
||
|
|
|
||
|
|
|
||
|
|
; ***** TIMER_COUNTER_1 **************
|
||
|
|
; TCCR1A - Timer/Counter Control Register A
|
||
|
|
.equ PWM1B = 0 ; Pulse Width Modulator B Enable
|
||
|
|
.equ PWM1A = 1 ; Pulse Width Modulator A Enable
|
||
|
|
.equ FOC1B = 2 ; Force Output Compare Match 1B
|
||
|
|
.equ FOC1A = 3 ; Force Output Compare Match 1A
|
||
|
|
.equ COM1B0 = 4 ; Comparator B Output Mode Bit 0
|
||
|
|
.equ COM1B1 = 5 ; Comparator B Output Mode Bit 1
|
||
|
|
.equ COM1A0 = 6 ; Comparator A Output Mode Bit 0
|
||
|
|
.equ COM1A1 = 7 ; Comparator A Output Mode Bit 1
|
||
|
|
|
||
|
|
; TCCR1B - Timer/Counter Control Register B
|
||
|
|
.equ CS10 = 0 ; Clock Select Bits
|
||
|
|
.equ CS11 = 1 ; Clock Select Bits
|
||
|
|
.equ CS12 = 2 ; Clock Select Bits
|
||
|
|
.equ CS13 = 3 ; Clock Select Bits
|
||
|
|
.equ PSR1 = 6 ; Prescaler Reset Timer/Counter1
|
||
|
|
.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match
|
||
|
|
|
||
|
|
; TCNT1 - Timer/Counter Register
|
||
|
|
.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0
|
||
|
|
.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1
|
||
|
|
.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2
|
||
|
|
.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3
|
||
|
|
.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4
|
||
|
|
.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5
|
||
|
|
.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6
|
||
|
|
.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7
|
||
|
|
|
||
|
|
; OCR1A - Output Compare Register
|
||
|
|
.equ OCR1A0 = 0 ; Output Compare Register A Bit 0
|
||
|
|
.equ OCR1A1 = 1 ; Output Compare Register A Bit 1
|
||
|
|
.equ OCR1A2 = 2 ; Output Compare Register A Bit 2
|
||
|
|
.equ OCR1A3 = 3 ; Output Compare Register A Bit 3
|
||
|
|
.equ OCR1A4 = 4 ; Output Compare Register A Bit 4
|
||
|
|
.equ OCR1A5 = 5 ; Output Compare Register A Bit 5
|
||
|
|
.equ OCR1A6 = 6 ; Output Compare Register A Bit 6
|
||
|
|
.equ OCR1A7 = 7 ; Output Compare Register A Bit 7
|
||
|
|
|
||
|
|
; OCR1B - Output Compare Register
|
||
|
|
.equ OCR1B0 = 0 ; Output Compare Register B Bit 0
|
||
|
|
.equ OCR1B1 = 1 ; Output Compare Register B Bit 1
|
||
|
|
.equ OCR1B2 = 2 ; Output Compare Register B Bit 2
|
||
|
|
.equ OCR1B3 = 3 ; Output Compare Register B Bit 3
|
||
|
|
.equ OCR1B4 = 4 ; Output Compare Register B Bit 4
|
||
|
|
.equ OCR1B5 = 5 ; Output Compare Register B Bit 5
|
||
|
|
.equ OCR1B6 = 6 ; Output Compare Register B Bit 6
|
||
|
|
.equ OCR1B7 = 7 ; Output Compare Register B Bit 7
|
||
|
|
|
||
|
|
; OCR1C - Output Compare Register
|
||
|
|
.equ OCR1C0 = 0 ; Output Compare Register C Bit 0
|
||
|
|
.equ OCR1C1 = 1 ; Output Compare Register C Bit 1
|
||
|
|
.equ OCR1C2 = 2 ; Output Compare Register C Bit 2
|
||
|
|
.equ OCR1C3 = 3 ; Output Compare Register C Bit 3
|
||
|
|
.equ OCR1C4 = 4 ; Output Compare Register C Bit 4
|
||
|
|
.equ OCR1C5 = 5 ; Output Compare Register C Bit 5
|
||
|
|
.equ OCR1C6 = 6 ; Output Compare Register C Bit 6
|
||
|
|
.equ OCR1C7 = 7 ; Output Compare Register C Bit 7
|
||
|
|
|
||
|
|
; TIMSK - Timer/Counter Interrupt Mask Register
|
||
|
|
;.equ TOIE0 = 1 ; Timer/Counter1 Overflow Interrupt Enable
|
||
|
|
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
|
||
|
|
.equ OCIE1B = 5 ; Timer/Counter1 Output Compare Interrupt Enable
|
||
|
|
.equ OCIE1A = 6 ; Timer/Counter1 Output Compare Interrupt Enable
|
||
|
|
|
||
|
|
; TIFR - Timer/Counter Interrupt Flag Register
|
||
|
|
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
|
||
|
|
.equ OCF1B = 5 ; Timer/Counter1 Output Compare Flag 1B
|
||
|
|
.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A
|
||
|
|
|
||
|
|
; PLLCSR - PLL Control and Status Register
|
||
|
|
.equ PLOCK = 0 ; PLL Lock Detector
|
||
|
|
.equ PLLE = 1 ; PLL Enable
|
||
|
|
.equ PCKE = 2 ; PCK Enable
|
||
|
|
|
||
|
|
|
||
|
|
; ***** EXTERNAL_INTERRUPT ***********
|
||
|
|
; GIMSK - General Interrupt Mask Register
|
||
|
|
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0
|
||
|
|
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1
|
||
|
|
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
||
|
|
|
||
|
|
; GIFR - General Interrupt Flag register
|
||
|
|
.equ PCIF = 5 ; Pin Change Interrupt Flag
|
||
|
|
.equ INTF0 = 6 ; External Interrupt Flag 0
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** LOCKSBITS ********************************************************
|
||
|
|
.equ LB1 = 0 ; Lockbit
|
||
|
|
.equ LB2 = 1 ; Lockbit
|
||
|
|
|
||
|
|
|
||
|
|
; ***** FUSES ************************************************************
|
||
|
|
; LOW fuse bits
|
||
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
||
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
||
|
|
.equ CKSEL2 = 2 ; Select Clock Source
|
||
|
|
.equ CKSEL3 = 3 ; Select Clock Source
|
||
|
|
.equ SUT0 = 4 ; Select start-up time
|
||
|
|
.equ SUT1 = 5 ; Select start-up time
|
||
|
|
.equ CKOPT = 6 ; Oscillator options
|
||
|
|
.equ PLLCK = 7 ; Use PLL for internal clock
|
||
|
|
|
||
|
|
; HIGH fuse bits
|
||
|
|
.equ BODEN = 0 ; Brown out detector enable
|
||
|
|
.equ BODLEVEL = 1 ; Brown out detector trigger level
|
||
|
|
.equ EESAVE = 2 ; EEPROM memory is preserved through the Chip Erase
|
||
|
|
.equ SPIEN = 3 ; Enable Serial Program and Data Downloading
|
||
|
|
.equ RSTDISBL = 4 ; Select if PB/ is I/O pin or RESET pin
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||
|
|
.def XH = r27
|
||
|
|
.def XL = r26
|
||
|
|
.def YH = r29
|
||
|
|
.def YL = r28
|
||
|
|
.def ZH = r31
|
||
|
|
.def ZL = r30
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||
|
|
.equ FLASHEND = 0x03ff ; Note: Word address
|
||
|
|
.equ IOEND = 0x003f
|
||
|
|
.equ SRAM_START = 0x0060
|
||
|
|
.equ SRAM_SIZE = 128
|
||
|
|
.equ RAMEND = 0x00df
|
||
|
|
.equ XRAMEND = 0x0000
|
||
|
|
.equ E2END = 0x007f
|
||
|
|
.equ EEPROMEND = 0x007f
|
||
|
|
.equ EEADRBITS = 7
|
||
|
|
#pragma AVRPART MEMORY PROG_FLASH 2048
|
||
|
|
#pragma AVRPART MEMORY EEPROM 128
|
||
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
||
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** INTERRUPT VECTORS ************************************************
|
||
|
|
.equ INT0addr = 0x0001 ; External Interrupt 0
|
||
|
|
.equ PCI0addr = 0x0002 ; External Interrupt Request 0
|
||
|
|
.equ OC1Aaddr = 0x0003 ; Timer/Counter1 Compare Match 1A
|
||
|
|
.equ OC1Baddr = 0x0004 ; Timer/Counter1 Compare Match 1B
|
||
|
|
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
||
|
|
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
||
|
|
.equ USI_STARTaddr = 0x0007 ; USI Start
|
||
|
|
.equ USI_OVFaddr = 0x0008 ; USI Overflow
|
||
|
|
.equ ERDYaddr = 0x0009 ; EEPROM Ready
|
||
|
|
.equ ACIaddr = 0x000a ; Analog Comparator
|
||
|
|
.equ ADCCaddr = 0x000b ; ADC Conversion Complete
|
||
|
|
|
||
|
|
.equ INT_VECTORS_SIZE = 12 ; size in words
|
||
|
|
|
||
|
|
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
||
|
|
|
||
|
|
#endif /* _TN26DEF_INC_ */
|
||
|
|
|
||
|
|
; ***** END OF FILE ******************************************************
|