forked from KolibriOS/kolibrios
408 lines
11 KiB
C
408 lines
11 KiB
C
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/**************************************************************************
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Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
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Copyright <EFBFBD> 2002 David Dawes
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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* David Dawes <dawes@xfree86.org>
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#if 0
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#define I830DEBUG
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#endif
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#include <stdint.h>
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#ifndef REMAP_RESERVED
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#define REMAP_RESERVED 0
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#endif
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#include "picture.h"
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#include <pciaccess.h>
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#include "intel_bufmgr.h"
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#include "i915_drm.h"
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#include "intel_driver.h"
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#include "intel_list.h"
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# define ENTER() printf("ENTER %s\n", __FUNCTION__)
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# define LEAVE() printf("LEAVE %s\n", __FUNCTION__)
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# define FAIL() printf("FAIL %s\n", __FUNCTION__)
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typedef int ScrnInfoPtr;
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typedef int ScreenPtr;
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typedef int Bool;
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#define TRUE (Bool)(1)
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#define FALSE (Bool)(0)
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typedef struct pixman_transform PictTransform, *PictTransformPtr;
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typedef struct _Pixmap *PixmapPtr;
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typedef struct _Picture *PicturePtr;
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/* remain compatible to xorg-server 1.6 */
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#ifndef MONITOR_EDID_COMPLETE_RAWDATA
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#define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA
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#endif
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#if XF86_CRTC_VERSION >= 5
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#define INTEL_PIXMAP_SHARING 1
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#endif
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struct intel_pixmap {
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dri_bo *bo;
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struct list batch;
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uint16_t stride;
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uint8_t tiling;
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int8_t busy :2;
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uint8_t dirty :1;
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uint8_t offscreen :1;
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uint8_t pinned :3;
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#define PIN_SCANOUT 0x1
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#define PIN_DRI 0x2
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#define PIN_GLAMOR 0x4
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};
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#if HAS_DEVPRIVATEKEYREC
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extern DevPrivateKeyRec uxa_pixmap_index;
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#else
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extern int uxa_pixmap_index;
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#endif
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/*
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static inline struct intel_pixmap *intel_get_pixmap_private(PixmapPtr pixmap)
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{
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#if HAS_DEVPRIVATEKEYREC
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return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index);
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#else
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return dixLookupPrivate(&pixmap->devPrivates, &uxa_pixmap_index);
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#endif
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}
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*/
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static inline Bool intel_pixmap_is_busy(struct intel_pixmap *priv)
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{
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if (priv->busy == -1)
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priv->busy = drm_intel_bo_busy(priv->bo);
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return priv->busy;
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}
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static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixmap *intel)
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{
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dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel);
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}
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static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap)
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{
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return pixmap && pixmap->private->dirty;
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}
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static inline Bool intel_pixmap_tiled(PixmapPtr pixmap)
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{
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return pixmap->private->tiling != I915_TILING_NONE;
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}
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dri_bo *intel_get_pixmap_bo(PixmapPtr pixmap);
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void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo);
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#include "common.h"
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#define PITCH_NONE 0
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/** enumeration of 3d consumers so some can maintain invariant state. */
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enum last_3d {
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LAST_3D_OTHER,
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LAST_3D_VIDEO,
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LAST_3D_RENDER,
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LAST_3D_ROTATION
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};
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enum dri_type {
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DRI_DISABLED,
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DRI_NONE,
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DRI_DRI2
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};
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typedef struct intel_screen_private {
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int scrn;
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int cpp;
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#define RENDER_BATCH I915_EXEC_RENDER
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#define BLT_BATCH I915_EXEC_BLT
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unsigned int current_batch;
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void *modes;
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drm_intel_bo *front_buffer, *back_buffer;
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PixmapPtr back_pixmap;
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unsigned int back_name;
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long front_pitch, front_tiling;
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dri_bufmgr *bufmgr;
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uint32_t batch_ptr[4096];
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/** Byte offset in batch_ptr for the next dword to be emitted. */
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unsigned int batch_used;
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/** Position in batch_ptr at the start of the current BEGIN_BATCH */
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unsigned int batch_emit_start;
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/** Number of bytes to be emitted in the current BEGIN_BATCH. */
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uint32_t batch_emitting;
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dri_bo *batch_bo, *last_batch_bo[2];
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/** Whether we're in a section of code that can't tolerate flushing */
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Bool in_batch_atomic;
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/** Ending batch_used that was verified by intel_start_batch_atomic() */
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int batch_atomic_limit;
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struct list batch_pixmaps;
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drm_intel_bo *wa_scratch_bo;
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unsigned int tiling;
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#define INTEL_TILING_FB 0x1
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#define INTEL_TILING_2D 0x2
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#define INTEL_TILING_3D 0x4
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#define INTEL_TILING_ALL (~0)
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Bool swapbuffers_wait;
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Bool has_relaxed_fencing;
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int Chipset;
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struct pci_device *PciInfo;
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const struct intel_device_info *info;
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unsigned int BR[20];
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void (*context_switch) (struct intel_screen_private *intel,
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int new_mode);
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void (*vertex_flush) (struct intel_screen_private *intel);
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void (*batch_flush) (struct intel_screen_private *intel);
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void (*batch_commit_notify) (struct intel_screen_private *intel);
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Bool need_sync;
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int accel_pixmap_offset_alignment;
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int accel_max_x;
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int accel_max_y;
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int max_bo_size;
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int max_gtt_map_size;
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int max_tiling_size;
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struct {
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drm_intel_bo *gen4_vs_bo;
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drm_intel_bo *gen4_sf_bo;
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drm_intel_bo *gen4_wm_packed_bo;
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drm_intel_bo *gen4_wm_planar_bo;
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drm_intel_bo *gen4_cc_bo;
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drm_intel_bo *gen4_cc_vp_bo;
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drm_intel_bo *gen4_sampler_bo;
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drm_intel_bo *gen4_sip_kernel_bo;
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drm_intel_bo *wm_prog_packed_bo;
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drm_intel_bo *wm_prog_planar_bo;
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drm_intel_bo *gen6_blend_bo;
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drm_intel_bo *gen6_depth_stencil_bo;
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} video;
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/* Render accel state */
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float scale_units[2][2];
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/** Transform pointers for src/mask, or NULL if identity */
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PictTransform *transform[2];
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PixmapPtr render_source, render_mask, render_dest;
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PicturePtr render_source_picture, render_mask_picture, render_dest_picture;
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Bool needs_3d_invariant;
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Bool needs_render_state_emit;
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Bool needs_render_vertex_emit;
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/* i830 render accel state */
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uint32_t render_dest_format;
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uint32_t cblend, ablend, s8_blendctl;
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/* i915 render accel state */
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PixmapPtr texture[2];
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uint32_t mapstate[6];
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uint32_t samplerstate[6];
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struct {
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int op;
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uint32_t dst_format;
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} i915_render_state;
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struct {
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int num_sf_outputs;
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int drawrect;
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uint32_t blend;
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dri_bo *samplers;
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dri_bo *kernel;
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} gen6_render_state;
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uint32_t prim_offset;
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void (*prim_emit)(struct intel_screen_private *intel,
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int srcX, int srcY,
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int maskX, int maskY,
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int dstX, int dstY,
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int w, int h);
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int floats_per_vertex;
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int last_floats_per_vertex;
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uint16_t vertex_offset;
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uint16_t vertex_count;
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uint16_t vertex_index;
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uint16_t vertex_used;
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uint32_t vertex_id;
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float vertex_ptr[4*1024];
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dri_bo *vertex_bo;
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uint8_t surface_data[16*1024];
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uint16_t surface_used;
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uint16_t surface_table;
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uint32_t surface_reloc;
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dri_bo *surface_bo;
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/* 965 render acceleration state */
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struct gen4_render_state *gen4_render_state;
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Bool use_pageflipping;
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Bool use_triple_buffer;
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Bool force_fallback;
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Bool has_kernel_flush;
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Bool needs_flush;
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enum last_3d last_3d;
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/**
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* User option to print acceleration fallback info to the server log.
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*/
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Bool fallback_debug;
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unsigned debug_flush;
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Bool has_prime_vmap_flush;
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} intel_screen_private;
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#define INTEL_INFO(intel) ((intel)->info)
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#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1))
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#define IS_GEN1(intel) IS_GENx(intel, 1)
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#define IS_GEN2(intel) IS_GENx(intel, 2)
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#define IS_GEN3(intel) IS_GENx(intel, 3)
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#define IS_GEN4(intel) IS_GENx(intel, 4)
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#define IS_GEN5(intel) IS_GENx(intel, 5)
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#define IS_GEN6(intel) IS_GENx(intel, 6)
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#define IS_GEN7(intel) IS_GENx(intel, 7)
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#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075)
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/* Some chips have specific errata (or limits) that we need to workaround. */
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#define IS_I830(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I830_M)
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#define IS_845G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_845_G)
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#define IS_I865G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I865_G)
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#define IS_I915G(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_G || (intel)->PciInfo->device_id == PCI_CHIP_E7221_G)
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#define IS_I915GM(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_GM)
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#define IS_965_Q(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I965_Q)
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/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
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#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040)
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#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060)
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#ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH
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#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
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#endif
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enum {
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DEBUG_FLUSH_BATCHES = 0x1,
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DEBUG_FLUSH_CACHES = 0x2,
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DEBUG_FLUSH_WAIT = 0x4,
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};
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extern intel_screen_private *driverPrivate;
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static inline intel_screen_private *
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intel_get_screen_private()
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{
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return driverPrivate;
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}
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#ifndef ARRAY_SIZE
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
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#endif
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|||
|
|
#ifndef ALIGN
|
|||
|
|
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#ifndef MIN
|
|||
|
|
#define MIN(a,b) ((a) < (b) ? (a) : (b))
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
static inline unsigned long intel_pixmap_pitch(PixmapPtr pixmap)
|
|||
|
|
{
|
|||
|
|
return (unsigned long)pixmap->devKind;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Batchbuffer support macros and functions */
|
|||
|
|
#include "intel_batchbuffer.h"
|
|||
|
|
void i965_vertex_flush(intel_screen_private *intel);
|
|||
|
|
void i965_batch_flush(intel_screen_private *intel);
|
|||
|
|
void i965_batch_commit_notify(intel_screen_private *intel);
|
|||
|
|
/**
|
|||
|
|
* Little wrapper around drm_intel_bo_reloc to return the initial value you
|
|||
|
|
* should stuff into the relocation entry.
|
|||
|
|
*
|
|||
|
|
* If only we'd done this before settling on the library API.
|
|||
|
|
*/
|
|||
|
|
static inline uint32_t
|
|||
|
|
intel_emit_reloc(drm_intel_bo * bo, uint32_t offset,
|
|||
|
|
drm_intel_bo * target_bo, uint32_t target_offset,
|
|||
|
|
uint32_t read_domains, uint32_t write_domain)
|
|||
|
|
{
|
|||
|
|
drm_intel_bo_emit_reloc(bo, offset, target_bo, target_offset,
|
|||
|
|
read_domains, write_domain);
|
|||
|
|
|
|||
|
|
return target_bo->offset + target_offset;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
static inline drm_intel_bo *intel_bo_alloc_for_data(intel_screen_private *intel,
|
|||
|
|
const void *data,
|
|||
|
|
unsigned int size,
|
|||
|
|
const char *name)
|
|||
|
|
{
|
|||
|
|
drm_intel_bo *bo;
|
|||
|
|
int ret;
|
|||
|
|
|
|||
|
|
bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096);
|
|||
|
|
assert(bo);
|
|||
|
|
|
|||
|
|
ret = drm_intel_bo_subdata(bo, 0, size, data);
|
|||
|
|
assert(ret == 0);
|
|||
|
|
|
|||
|
|
return bo;
|
|||
|
|
(void)ret;
|
|||
|
|
}
|