1) gfx reverted to stable version 1710

2) Phenom and Fusion CPUs supported
3) RDMSR syscall added

git-svn-id: svn://kolibrios.org@1928 a494cfbc-eb01-0410-851d-a64ba20cac60

kernel/branches/Kolibri-A/trunk/bus/HT.inc

@@ -136,12 +136,16 @@ rs7xx_pcie_init:
 	call	rs7xx_nbconfig_flush_pci
 	mov	eax, ebx
 	and	eax, 0xFFE00000 		; valid bits [31..21]
-	jz	$				; NB BAR3 may be invisible!
+	jz	$				; invalid map!
 .addr_found:
 	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; physical address (lower 32 bits)
 	add	dword[mmio_pcie_cfg_lim-OS_BASE],  eax
 
-	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  by the way, UW is unsafe!
+; ---- common mapping procedure ----
+; (eax = phys. address of PCIe conf.space)
+;
+map_pcie_pages:
+	or	eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW)  ;  UW is unsafe, fix it!
 	mov	ecx, PCIe_CONFIG_SPACE			; linear address
 	mov	ebx, ecx
 	shr	ebx, 20
@@ -167,6 +171,32 @@ rs7xx_pcie_init:
 .pcie_cfg_mapped:
 	ret	; <<< OK >>>
 
+; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
+align 4
+fusion_pcie_init:
+        mov     ecx, 0xC0010058
+        rdmsr
+        or      edx, edx
+        jnz     $                               ; PCIe is in the upper memory. Stop.
+        xchg    dl, al
+	mov	dword[mmio_pcie_cfg_addr-OS_BASE], eax	; store the physical address
+        mov     ecx, edx
+        and     dl, 1
+        jz      $                               ; bit[0] = 1 means no PCIe mapping allowed. Stop.
+        shr     cl, 2                           ; ecx = log2(number of buses)
+	mov	word[PCIe_bus_range-OS_BASE], cx	
+        sub     cl, 2
+        jae     @f
+        xor     cl, cl
+@@:
+        shl     edx, cl                         ; edx = number of 4M pages to map
+	mov	word[mmio_pcie_cfg_pdes-OS_BASE], dx	
+        shl     edx, 22
+        dec     edx
+        add     edx, eax                        ; the upper configspace limit
+	mov	dword[mmio_pcie_cfg_lim-OS_BASE], edx
+
+        jmp     map_pcie_pages  
 
 ; ================================================================================
 
@@ -278,6 +308,19 @@ rs780_write_htiu:
 	pop	edx
 	ret
 
+;------------------------------------------------
+align 4
+sys_rdmsr:
+;  in: [esp+8] = MSR#
+; out: [esp+8] = MSR[63:32]
+;        [eax] = MSR[31: 0]
+;------------------------------------------------
+        push    ecx edx
+        mov     ecx, [esp+16]
+        rdmsr
+        mov     [esp+16], edx
+        pop     edx ecx
+        ret
 
 
 

kernel/branches/Kolibri-A/trunk/core/syscall.inc

@@ -44,28 +44,10 @@ i40:
 
 align 32
 syscall_entry:
-	push  ecx
 ;        sti
-;        and   eax, 3
+	push ecx
-;        call    dword [servetable3 + eax * 4]
+	and   eax, 3
-
+	call	dword [servetable3 + eax * 4]
-	mov edi, [esp+4]
-	mov ecx, [esp+8]
-	mov edx, [esp+12]
-	mov ebx, [esp+16]
-	and al, 1
-	jz .hline
-	mov eax, [esp+20]
-	sti
-	call vline
-	jmp .done
-.hline:
-	mov eax, [esp+20]
-	sti
-	call hline
-.done:
-
-
 	pop	ecx
 	sysret
 
@@ -173,8 +155,8 @@ iglobal
 align 4
 servetable3:	; Kolibri-A special service
 
-	dd	hline	    ; 0
+	dd	sys_rdmsr	 ; 0
-	dd	vline	    ; 1
+	dd	paleholder	 ; 1
 	dd	paleholder	 ; 2
 	dd	sys_end ; last
 

kernel/branches/Kolibri-A/trunk/hid/mousedrv.inc

@@ -8,6 +8,7 @@
 $Revision$
 
  
+
 ;   check mouse
 ;
 ;

kernel/branches/Kolibri-A/trunk/kernel.asm

@@ -219,7 +219,8 @@ diff16 "32-bit code start ",0,$
 	   call init_BIOS32	; (init.inc - to be removed later)
 
 ; PCIe extended config space access
-	   call rs7xx_pcie_init	; (bus/HT.inc)
+;	   call rs7xx_pcie_init	; (bus/HT.inc)
+	   call fusion_pcie_init	; (bus/HT.inc)
 
 ; MEMORY MODEL
 	   call init_mem	; (init.inc)