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Removed old netdrv.inc and pci.inc, replaced with newer, better versions.

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git-svn-id: svn://kolibrios.org@5074 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
hidnplayr 2014-08-31 14:09:14 +00:00
parent 48b7151d43
commit bb295aca38
20 changed files with 316 additions and 598 deletions
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2
drivers/ethernet/3c59x.asm
View File

@ -105,7 +105,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
; Registers
REG_POWER_MGMT_CTRL = 0x7c

2
drivers/ethernet/R6040.asm
View File

@ -52,7 +52,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
; Operational parameters that usually are not changed.

2
drivers/ethernet/RTL8029.asm
View File

@ -35,7 +35,7 @@ include '../struct.inc'
include '../macros.inc'
include '../proc32.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
struct device ETH_DEVICE

2
drivers/ethernet/RTL8139.asm
View File

@ -41,7 +41,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
REG_IDR0 = 0x00
REG_MAR0 = 0x08 ; multicast filter register 0

2
drivers/ethernet/RTL8169.asm
View File

@ -39,7 +39,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
REG_MAC0 = 0x0 ; Ethernet hardware address
REG_MAR0 = 0x8 ; Multicast filter

2
drivers/ethernet/dec21x4x.asm
View File

@ -40,7 +40,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
;-------------------------------------------
; configuration registers

2
drivers/ethernet/forcedeth.asm
View File

@ -50,7 +50,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
;**************************************************************************
; forcedeth Register Definitions

2
drivers/ethernet/i8254x.asm
View File

@ -37,7 +37,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
; Register list
REG_CTRL = 0x0000 ; Control Register

2
drivers/ethernet/i8255x.asm
View File

@ -40,7 +40,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
; Serial EEPROM

2
drivers/ethernet/mtd80x.asm
View File

@ -35,7 +35,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
; for different PHY

2
drivers/ethernet/pcnet32.asm
View File

@ -35,7 +35,7 @@ include '../struct.inc'
include '../macros.inc'
include '../proc32.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
PORT_AUI = 0x00

2
drivers/ethernet/rhine.asm
View File

@ -58,7 +58,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
;**************************************************************************

2
drivers/ethernet/sis900.asm
View File

@ -202,7 +202,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
struct device ETH_DEVICE

110
drivers/netdrv.inc
View File

@ -26,48 +26,57 @@ include 'mii.inc'
PAGESIZE = 4096
; network driver types
; Network driver types
NET_TYPE_ETH = 1
NET_TYPE_SLIP = 2
; link state
; Link state
ETH_LINK_DOWN = 0 ; Link is down
ETH_LINK_UNKOWN = 1b ; There could be an active link
ETH_LINK_UNKNOWN= 1b ; There could be an active link
ETH_LINK_FD = 10b ; full duplex flag
ETH_LINK_10M = 100b ; 10 mbit
ETH_LINK_100M = 1000b ; 100 mbit
ETH_LINK_1G = 10000b ; gigabit
ETH_LINK_1G = 1100b ; gigabit
; Macro to easily set i/o addresses to access device.
; In the beginning of a procedure (or ofter edx may have been destroyed),
; always use set_io with offset 0 to reset the variables.
LAST_IO = 0
macro set_io addr {
if addr = 0
mov edx, [device.io_addr]
else if addr = LAST_IO
macro set_io baseaddr, offset {
if offset = 0
mov edx, baseaddr
else if offset = LAST_IO
else
add edx, addr - LAST_IO
add edx, offset - LAST_IO
end if
LAST_IO = addr
LAST_IO = offset
}
; Macro to allocate a contiguous buffer in memory
; And initialise it to all zeros
; This macro will destroy eax, ecx and edi !
macro allocate_and_clear dest, size, err {
; We need to allocate at least 8 pages, if we want a continuous memory in ram
; We need to allocate at least 8 pages, if we want a contiguous area in ram
push edx
if (size < 8*4096) & (size > 4096)
stdcall KernelAlloc, 8*4096
invoke KernelAlloc, 8*4096
else
stdcall KernelAlloc, size
invoke KernelAlloc, size
end if
pop edx
test eax, eax
jz err
mov dest, eax ; Save the address to it into the device struct
mov dest, eax
mov edi, eax ; look at last part of code!
; Release the unused pages (if any)
@ -75,7 +84,7 @@ macro allocate_and_clear dest, size, err {
add eax, (size/4096+1)*4096
mov ecx, 8-(size/4096+1)
push edx
call ReleasePages
invoke ReleasePages
pop edx
end if
@ -92,59 +101,30 @@ macro allocate_and_clear dest, size, err {
}
if used null_op
align 4
null_op:
or eax, -1
ret
struct NET_DEVICE
end if
type dd ? ; Type field
mtu dd ? ; Maximal Transmission Unit
name dd ? ; Ptr to 0 terminated string
unload dd ? ; Ptrs to driver functions
reset dd ? ;
transmit dd ? ;
bytes_tx dq ? ; Statistics, updated by the driver
bytes_rx dq ? ;
packets_tx dd ? ;
packets_rx dd ? ;
state dd ? ; link state (0 = no link)
hwacc dd ? ; bitmask stating enabled HW accelerations
ends
macro GetRealAddr { ; input and output is eax
struct ETH_DEVICE NET_DEVICE
push ax
call GetPgAddr
and word[esp], PAGESIZE - 1
or ax, word[esp]
inc esp
inc esp
}
macro NET_DEVICE {
.type dd ? ; Type field
.mtu dd ? ; Maximal Transmission Unit
.name dd ? ; Ptr to 0 terminated string
.unload dd ? ; Ptrs to driver functions
.reset dd ? ;
.transmit dd ? ;
.bytes_tx dq ? ; Statistics, updated by the driver
.bytes_rx dq ? ;
.packets_tx dd ? ;
.packets_rx dd ? ;
.state dd ? ; link state (0 = no link)
.hwacc dd ? ; bitmask stating enabled HW accelerations
.end:
}
macro ETH_DEVICE {
NET_DEVICE
.mac dp ?
mac dp ?
dw ? ; qword alignment
}
macro SLIP_DEVICE {
NET_DEVICE
}
ends

130
drivers/netdrv_pe.inc
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@ -1,130 +0,0 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; GNU GENERAL PUBLIC LICENSE ;;
;; Version 2, June 1991 ;;
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This macro will prepend driver name to all debug output through DEBUGF macro
; The driver name is taken from my_service label
if defined my_service
macro DEBUGF _level,_format, [args] {
common DEBUGF _level, "%s: " # _format, my_service, args
}
end if
include 'pci_pe.inc'
include 'mii.inc'
; Kernel variables
PAGESIZE = 4096
; Network driver types
NET_TYPE_ETH = 1
NET_TYPE_SLIP = 2
; Link state
ETH_LINK_DOWN = 0 ; Link is down
ETH_LINK_UNKNOWN= 1b ; There could be an active link
ETH_LINK_FD = 10b ; full duplex flag
ETH_LINK_10M = 100b ; 10 mbit
ETH_LINK_100M = 1000b ; 100 mbit
ETH_LINK_1G = 1100b ; gigabit
; Macro to easily set i/o addresses to access device.
; In the beginning of a procedure (or ofter edx may have been destroyed),
; always use set_io with offset 0 to reset the variables.
LAST_IO = 0
macro set_io baseaddr, offset {
if offset = 0
mov edx, baseaddr
else if offset = LAST_IO
else
add edx, offset - LAST_IO
end if
LAST_IO = offset
}
; Macro to allocate a contiguous buffer in memory
; And initialise it to all zeros
; This macro will destroy eax, ecx and edi !
macro allocate_and_clear dest, size, err {
; We need to allocate at least 8 pages, if we want a contiguous area in ram
push edx
if (size < 8*4096) & (size > 4096)
invoke KernelAlloc, 8*4096
else
invoke KernelAlloc, size
end if
pop edx
test eax, eax
jz err
mov dest, eax
mov edi, eax ; look at last part of code!
; Release the unused pages (if any)
if (size < 8*4096) & (size > 4096)
add eax, (size/4096+1)*4096
mov ecx, 8-(size/4096+1)
push edx
invoke ReleasePages
pop edx
end if
; Clear the allocated buffer
mov ecx, size/4 ; divide by 4 because of DWORD
xor eax, eax
rep stosd
if (size - size/4*4)
mov ecx, size - size/4*4
rep stosb
end if
}
struct NET_DEVICE
type dd ? ; Type field
mtu dd ? ; Maximal Transmission Unit
name dd ? ; Ptr to 0 terminated string
unload dd ? ; Ptrs to driver functions
reset dd ? ;
transmit dd ? ;
bytes_tx dq ? ; Statistics, updated by the driver
bytes_rx dq ? ;
packets_tx dd ? ;
packets_rx dd ? ;
state dd ? ; link state (0 = no link)
hwacc dd ? ; bitmask stating enabled HW accelerations
ends
struct ETH_DEVICE NET_DEVICE
mac dp ?
dw ? ; qword alignment
ends

208
drivers/pci.inc
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@ -1,6 +1,6 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; GNU GENERAL PUBLIC LICENSE ;;
@ -8,125 +8,163 @@
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
struct PCI_header
; PCI Bus defines
vendor_id dw ? ; 0x00
device_id dw ? ; 0x02
command dw ? ; 0x04
status dw ? ; 0x06
revision_id db ? ; 0x08
prog_if db ? ; 0x09
subclass db ? ; 0x0A
class_code db ? ; 0x0B
cache_line_size db ? ; 0x0C
latency_timer db ? ; 0x0D
header_type db ? ; 0x0E
bist db ? ; 0x0F
PCI_HEADER_TYPE = 0x0e ; 8 bit
PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit
PCI_BASE_ADDRESS_1 = 0x14 ; 32 bits
PCI_BASE_ADDRESS_2 = 0x18 ; 32 bits
PCI_BASE_ADDRESS_3 = 0x1c ; 32 bits
PCI_BASE_ADDRESS_4 = 0x20 ; 32 bits
PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits
ends
struct PCI_header00 PCI_header
base_addr_0 dd ? ; 0x10
base_addr_1 dd ? ; 0x14
base_addr_2 dd ? ; 0x18
base_addr_3 dd ? ; 0x1C
base_addr_4 dd ? ; 0x20
base_addr_5 dd ? ; 0x24
cardbus_cis_ptr dd ? ; 0x28
subsys_vendor dw ? ; 0x2C
subsys_id dw ? ; 0x2E
exp_rom_addr dd ? ; 0x30
cap_ptr db ? ; 0x34
rb 7 ; reserved
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3D
min_grant db ? ; 0x3E
max_latency db ? ; 0x3F
ends
struct PCI_header01 PCI_header
base_addr_0 dd ? ; 0x10
base_addr_1 dd ? ; 0x14
prim_bus_nr db ? ; 0x18
sec_bus_nr db ? ; 0x19
sub_bus_nr db ? ; 0x1A
sec_lat_tmr db ? ; 0x1B
io_base db ? ; 0x1C
io_limit db ? ; 0x1D
sec_status dw ? ; 0x1E
mem_base dw ? ; 0x20
mem_limit dw ? ; 0x22
pref_mem_base dw ? ; 0x24
pref_mem_limit dw ? ; 0x26
pref_base_up dd ? ; 0x28
pref_limit_up dd ? ; 0x2C
io_base_up dw ? ; 0x30
io_limit_up dw ? ; 0x32
cap_ptr db ? ; 0x34
rb 3 ; reserved
exp_rom_addr dd ? ; 0x38
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3E
bridge_ctrl dw ? ; 0x3F
ends
struct PCI_header02 PCI_header
base_addr dd ? ; 0x10
cap_list_offs db ? ; 0x14
rb 1 ; reserved
sec_stat dw ? ; 0x16
pci_bus_nr db ? ; 0x18
cardbus_bus_nr db ? ; 0x19
sub_bus_nr db ? ; 0x1A
cardbus_lat_tmr db ? ; 0x1B
mbar_0 dd ? ; 0x1C
mlimit_0 dd ? ; 0x20
mbar_1 dd ? ; 0x24
mlimit_1 dd ? ; 0x28
iobar_0 dd ? ; 0x2C
iolimit_0 dd ? ; 0x30
iobar_1 dd ? ; 0x34
iolimit_1 dd ? ; 0x38
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3D
bridge_ctrl dw ? ; 0x3E
subs_did dw ? ; 0x40
subs_vid dw ? ; 0x42
legacy_bar dd ? ; 0x44
ends
; Base address bits
PCI_BASE_ADDRESS_SPACE_IO = 0x01
PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0
; PCI programming
; command bits
PCI_CMD_PIO = 0x01 ; bit0: io space control
PCI_CMD_MMIO = 0x02 ; bit1: memory space control
PCI_CMD_MASTER = 0x04 ; bit2: device acts as a PCI master
PCI_VENDOR_ID = 0x00 ; 16 bit
PCI_DEVICE_ID = 0x02 ; 16 bits
PCI_REG_COMMAND = 0x4 ; command register
PCI_REG_STATUS = 0x6 ; status register
PCI_REVISION_ID = 0x08 ; 8 bits
PCI_REG_LATENCY = 0xd ; latency timer register
PCI_REG_CAP_PTR = 0x34 ; capabilities pointer
PCI_REG_IRQ = 0x3c
PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block
PCI_REG_PM_STATUS = 0x4 ; power management status register
PCI_REG_PM_CTRL = 0x4 ; power management control register
PCI_BIT_PIO = 1 ; bit0: io space control
PCI_BIT_MMIO = 2 ; bit1: memory space control
PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master
; status bits
PCI_STATUS_CAPA = 0x10 ; bit4: new capabilities available
macro PCI_find_io {
local .check, .inc, .got
if used PCI_find_io
proc PCI_find_io stdcall bus, dev
push esi
xor eax, eax
mov esi, PCI_BASE_ADDRESS_0
mov esi, PCI_header00.base_addr_0
.check:
stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi
invoke PciRead32, [bus], [dev], esi
test eax, PCI_BASE_ADDRESS_IO_MASK
jz .inc
test eax, PCI_BASE_ADDRESS_SPACE_IO
jz .inc
and eax, PCI_BASE_ADDRESS_IO_MASK
jmp .got
pop esi
ret
.inc:
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
cmp esi, PCI_header00.base_addr_5
jbe .check
pop esi
xor eax, eax
ret
.got:
mov [device.io_addr], eax
}
endp
end if
macro PCI_find_mmio32 {
if used PCI_find_mmio32
proc PCI_find_mmio32 stdcall bus, dev
local .check, .inc, .got
mov esi, PCI_BASE_ADDRESS_0
push esi
mov esi, PCI_header00.base_addr_0
.check:
stdcall PciRead32, [device.pci_bus], [device.pci_dev], esi
invoke PciRead32, [bus], [dev], esi
test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address?
jnz .inc
test eax, 100b ; 64 bit?
jnz .inc
and eax, not 1111b
jmp .got
pop esi
ret
.inc:
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
cmp esi, PCI_header00.base_addr_5
jbe .check
xor eax, eax
pop esi
ret
.got:
mov [device.mmio_addr], eax
}
macro PCI_find_irq {
stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_IRQ
mov [device.irq_line], al
}
macro PCI_find_rev {
stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REVISION_ID
mov [device.revision], al
}
macro PCI_make_bus_master bus, dev {
stdcall PciRead32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND
or al, PCI_BIT_MASTER
stdcall PciWrite32, [device.pci_bus], [device.pci_dev], PCI_REG_COMMAND, eax
}
macro PCI_adjust_latency min {
local .not
stdcall PciRead8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY
cmp al, min
ja .not
mov al, min
stdcall PciWrite8, [device.pci_bus], [device.pci_dev], PCI_REG_LATENCY, eax
.not:
}
endp
end if

170
drivers/pci_pe.inc
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@ -1,170 +0,0 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; GNU GENERAL PUBLIC LICENSE ;;
;; Version 2, June 1991 ;;
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
struct PCI_header
vendor_id dw ? ; 0x00
device_id dw ? ; 0x02
command dw ? ; 0x04
status dw ? ; 0x06
revision_id db ? ; 0x08
prog_if db ? ; 0x09
subclass db ? ; 0x0A
class_code db ? ; 0x0B
cache_line_size db ? ; 0x0C
latency_timer db ? ; 0x0D
header_type db ? ; 0x0E
bist db ? ; 0x0F
ends
struct PCI_header00 PCI_header
base_addr_0 dd ? ; 0x10
base_addr_1 dd ? ; 0x14
base_addr_2 dd ? ; 0x18
base_addr_3 dd ? ; 0x1C
base_addr_4 dd ? ; 0x20
base_addr_5 dd ? ; 0x24
cardbus_cis_ptr dd ? ; 0x28
subsys_vendor dw ? ; 0x2C
subsys_id dw ? ; 0x2E
exp_rom_addr dd ? ; 0x30
cap_ptr db ? ; 0x34
rb 7 ; reserved
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3D
min_grant db ? ; 0x3E
max_latency db ? ; 0x3F
ends
struct PCI_header01 PCI_header
base_addr_0 dd ? ; 0x10
base_addr_1 dd ? ; 0x14
prim_bus_nr db ? ; 0x18
sec_bus_nr db ? ; 0x19
sub_bus_nr db ? ; 0x1A
sec_lat_tmr db ? ; 0x1B
io_base db ? ; 0x1C
io_limit db ? ; 0x1D
sec_status dw ? ; 0x1E
mem_base dw ? ; 0x20
mem_limit dw ? ; 0x22
pref_mem_base dw ? ; 0x24
pref_mem_limit dw ? ; 0x26
pref_base_up dd ? ; 0x28
pref_limit_up dd ? ; 0x2C
io_base_up dw ? ; 0x30
io_limit_up dw ? ; 0x32
cap_ptr db ? ; 0x34
rb 3 ; reserved
exp_rom_addr dd ? ; 0x38
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3E
bridge_ctrl dw ? ; 0x3F
ends
struct PCI_header02 PCI_header
base_addr dd ? ; 0x10
cap_list_offs db ? ; 0x14
rb 1 ; reserved
sec_stat dw ? ; 0x16
pci_bus_nr db ? ; 0x18
cardbus_bus_nr db ? ; 0x19
sub_bus_nr db ? ; 0x1A
cardbus_lat_tmr db ? ; 0x1B
mbar_0 dd ? ; 0x1C
mlimit_0 dd ? ; 0x20
mbar_1 dd ? ; 0x24
mlimit_1 dd ? ; 0x28
iobar_0 dd ? ; 0x2C
iolimit_0 dd ? ; 0x30
iobar_1 dd ? ; 0x34
iolimit_1 dd ? ; 0x38
interrupt_line db ? ; 0x3C
interrupt_pin db ? ; 0x3D
bridge_ctrl dw ? ; 0x3E
subs_did dw ? ; 0x40
subs_vid dw ? ; 0x42
legacy_bar dd ? ; 0x44
ends
; Base address bits
PCI_BASE_ADDRESS_SPACE_IO = 0x01
PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
PCI_BASE_ADDRESS_MEM_MASK = 0xFFFFFFF0
; command bits
PCI_CMD_PIO = 0x01 ; bit0: io space control
PCI_CMD_MMIO = 0x02 ; bit1: memory space control
PCI_CMD_MASTER = 0x04 ; bit2: device acts as a PCI master
; status bits
PCI_STATUS_CAPA = 0x10 ; bit4: new capabilities available
if used PCI_find_io
proc PCI_find_io stdcall bus, dev
push esi
xor eax, eax
mov esi, PCI_header00.base_addr_0
.check:
invoke PciRead32, [bus], [dev], esi
test eax, PCI_BASE_ADDRESS_IO_MASK
jz .inc
test eax, PCI_BASE_ADDRESS_SPACE_IO
jz .inc
and eax, PCI_BASE_ADDRESS_IO_MASK
pop esi
ret
.inc:
add esi, 4
cmp esi, PCI_header00.base_addr_5
jbe .check
pop esi
xor eax, eax
ret
endp
end if
if used PCI_find_mmio32
proc PCI_find_mmio32 stdcall bus, dev
push esi
mov esi, PCI_header00.base_addr_0
.check:
invoke PciRead32, [bus], [dev], esi
test eax, PCI_BASE_ADDRESS_SPACE_IO ; mmio address?
jnz .inc
test eax, 100b ; 64 bit?
jnz .inc
and eax, not 1111b
pop esi
ret
.inc:
add esi, 4
cmp esi, PCI_header00.base_addr_5
jbe .check
xor eax, eax
pop esi
ret
endp
end if

2
drivers/unfinished/agp.asm
View File

@ -27,7 +27,7 @@ section '.flat' readable writable executable
include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../pci_pe.inc'
include '../pci.inc'
;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;

2
drivers/unfinished/bcm57xx.asm
View File

@ -32,7 +32,7 @@ include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../fdo.inc'
include '../netdrv_pe.inc'
include '../netdrv.inc'
struct device ETH_DEVICE

2
drivers/unfinished/cardbus.asm
View File

@ -34,7 +34,7 @@ section '.flat' readable writable executable
include '../proc32.inc'
include '../struct.inc'
include '../macros.inc'
include '../pci_pe.inc'
include '../pci.inc'
include '../fdo.inc'
;;;;;;;;;;;;;;;;;;;;;;;;;;;;