forked from KolibriOS/kolibrios
ARM Emulator: emulate instruction ARM processor v0.01
git-svn-id: svn://kolibrios.org@7405 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
pavelyakov
parent
fa3e0cb007
commit
d8e4b3ebb5
8
programs/cmm/ARM/compile.bat
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8
programs/cmm/ARM/compile.bat
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@del emul.kex
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@c-- emul.c
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@rename emul.com emul.kex
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@del warning.txt
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@del lang.h--
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@pause
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218
programs/cmm/ARM/emul.c
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218
programs/cmm/ARM/emul.c
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// version 0.01
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// Author: Pavel Iakovlev
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#pragma option OST
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#pragma option ON
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#pragma option cri-
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#pragma option -CPA
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#initallvar 0
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#jumptomain FALSE
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#startaddress 0x10000
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#code32 TRUE
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char os_name[8] = {'M','E','N','U','E','T','0','1'};
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dword os_version = 0x00000001;
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dword start_addr = #main;
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dword final_addr = #______STOP______+32;
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dword alloc_mem = 20000;
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dword x86esp_reg = 20000;
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dword I_Param = #param;
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dword I_Path = #program_path;
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char param[4096] ={0};
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char program_path[4096] = {0};
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dword test_bytecode = "\x05\x10\x82\xe2\x07\x30\x82\xe2\x03\x20\x81\xe0"; // test opcode arm
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struct _reg // registers arm
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{
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dword r0;
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dword r1;
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dword r2;
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dword r3;
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dword r4;
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dword r5;
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dword r6;
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dword r7;
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dword r8;
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dword r9;
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dword r10;
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dword r11;
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dword r12; // (Intra-Procedure-call scratch register)
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dword r13; // (Stack Pointer)
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dword r14; // (Link Register)
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dword r15; // PC (Program Counter)
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};
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_reg reg = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; // clear and init registers
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dword REG = #reg;
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struct _flags
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{
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byte negative;
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byte zero;
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byte carry;
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byte overflow;
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};
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_flags flags = {0,0,0,0}; // clear and init flags
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struct _mode
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{
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byte User;
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byte FastInterrupt;
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byte Interrupt;
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byte Supervisor;
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};
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_mode mode = {0,0,0,0}; // processor mode
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struct _mask
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{
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byte IRQ;
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byte FIRQ;
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};
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_mask mask = {0,0}; // processor mask
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void main()
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{
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callOpcode(#test_bytecode,3);
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EAX = -1;
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$int 0x40;
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}
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dword callOpcode(dword binary, lengthInstruction)
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{
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dword command = 0;
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dword PC = 0;
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byte flag = 0;
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byte pMask = 0;
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byte pMode = 0;
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while(lengthInstruction)
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{
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PC = reg.r15 >> 2 & 0xFFFFFF;
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flag = reg.r15 >> 28;
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pMask = reg.r15 >> 26;
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flags.negative = flag & 0x8;
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flags.zero = flag & 0x4;
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flags.carry = flag & 0x2;
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flags.overflow = flag & 0x1;
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mask.IRQ = pMask & 0x2;
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mask.FIRQ = pMask & 0x1;
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switch(reg.r15 & 3)
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{
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case 0:
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DSDWORD[#mode] = 0x000000FF;
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break;
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case 1:
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DSDWORD[#mode] = 0x0000FF00;
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break;
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case 2:
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DSDWORD[#mode] = 0x00FF0000;
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break;
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case 3:
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DSDWORD[#mode] = 0xFF000000;
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break;
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}
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command = DSDWORD[binary + PC]; // generation PC instruction
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//EAX = DSDWORD[command >> 28 << 2 + #opcodeExec]; // get opcodeExecition call instruction
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//EAX(command); // call opcodeExecition
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//IF (command & 0xC000000 == 0) opcodeExec0(command);
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IF (command & 0x0FFFFFF0 == 0x12FFF10) BranchExchange(command);
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ELSE IF (command & 0x0FF00FF0 == 0x1000090) SingleDataSwap(command);
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ELSE IF (command & 0x0FC000F0 == 0x0000090) Multiply(command);
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ELSE IF (command & 0x0FC000F0 == 0x0800090) MultiplyLong(command);
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ELSE IF (command & 0x0C000000 == 0x0000000) DataProcessing(command);
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PC += 4; // addition 4 for reg15 or PC instruction
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PC <<= 2;
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flag = 0;
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IF (flags.negative) flag |= 0x8;
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IF (flags.zero) flag |= 0x4;
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IF (flags.carry) flag |= 0x2;
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IF (flags.overflow) flag |= 0x1;
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pMask = 0;
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IF (mask.IRQ) pMask |= 0x2;
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IF (mask.FIRQ) pMask |= 0x1;
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IF (mode.User) pMode = 0;
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ELSE IF (mode.FastInterrupt) pMode = 1;
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ELSE IF (mode.Interrupt) pMode = 2;
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ELSE IF (mode.Supervisor) pMode = 3;
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reg.r15 = flag << 28 | PC | pMode;
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lengthInstruction--;
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}
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}
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dword Multiply(dword command)
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{
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}
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dword MultiplyLong(dword command)
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{
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}
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dword SingleDataSwap(dword command)
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{
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}
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dword BranchExchange(dword command)
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{
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}
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dword DataProcessing(dword command) // Data Processing / PSR Transfer
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{
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dword opcode = 0;
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dword Rd = #reg;
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dword Rn = #reg;
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dword operand = 0;
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opcode = command >> 21 & 0xF;
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Rd += command >> 12 & 0xF << 2;
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Rn += command >> 16 & 0xF << 2;
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operand = command & 0xFFF;
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IF (command & 0x2000000 == 0)
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{
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operand = DSDWORD[operand << 2 + #reg];
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}
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switch (opcode)
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{
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case 0: // and
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DSDWORD[Rd] = DSDWORD[Rn] & operand;
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break;
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case 1: // eor
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DSDWORD[Rd] = DSDWORD[Rn] | operand;
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break;
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case 2: // sub
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DSDWORD[Rd] = DSDWORD[Rn] - operand;
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break;
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case 3: // rsb
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DSDWORD[Rd] = operand - DSDWORD[Rn];
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break;
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case 4: // add
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DSDWORD[Rd] = DSDWORD[Rn] + operand;
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break;
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}
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IF(reg.r2 == 12) while(1);
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}
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______STOP______:
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