forked from KolibriOS/kolibrios
1100 lines
30 KiB
C
1100 lines
30 KiB
C
/*
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* Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com>
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* Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com>
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* Copyright 2007, 2008 Egbert Eich <eich@novell.com>
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* Copyright 2007, 2008 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "xf86.h"
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/* for usleep */
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#if HAVE_XF86_ANSIC_H
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# include "xf86_ansic.h"
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#else
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# include <unistd.h>
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# include <string.h>
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# include <stdio.h>
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#endif
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#include "rhd.h"
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#include "rhd_connector.h"
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#include "rhd_output.h"
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#include "rhd_crtc.h"
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#include "rhd_regs.h"
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#ifdef ATOM_BIOS
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# include "rhd_atombios.h"
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#endif
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#define REG_DACA_OFFSET 0
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#define RV620_REG_DACA_OFFSET 0
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#define REG_DACB_OFFSET 0x200
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#define RV620_REG_DACB_OFFSET 0x100
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struct rhdDACPrivate {
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Bool Stored;
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CARD32 Store_Powerdown;
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CARD32 Store_Force_Output_Control;
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CARD32 Store_Force_Data;
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CARD32 Store_Source_Select;
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CARD32 Store_Sync_Select;
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CARD32 Store_Enable;
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CARD32 Store_Control1;
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CARD32 Store_Control2;
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CARD32 Store_Tristate_Control;
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CARD32 Store_Auto_Calib_Control;
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CARD32 Store_Dac_Bgadj_Src;
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};
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/* ----------------------------------------------------------- */
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/*
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*
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*/
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static unsigned char
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DACSense(struct rhdOutput *Output, CARD32 offset, Bool TV)
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{
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CARD32 CompEnable, Control1, Control2, DetectControl, Enable;
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CARD8 ret;
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CompEnable = RHDRegRead(Output, offset + DACA_COMPARATOR_ENABLE);
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Control1 = RHDRegRead(Output, offset + DACA_CONTROL1);
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Control2 = RHDRegRead(Output, offset + DACA_CONTROL2);
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DetectControl = RHDRegRead(Output, offset + DACA_AUTODETECT_CONTROL);
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Enable = RHDRegRead(Output, offset + DACA_ENABLE);
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RHDRegWrite(Output, offset + DACA_ENABLE, 1);
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/* ack autodetect */
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RHDRegMask(Output, offset + DACA_AUTODETECT_INT_CONTROL, 0x01, 0x01);
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RHDRegMask(Output, offset + DACA_AUTODETECT_CONTROL, 0, 0x00000003);
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RHDRegMask(Output, offset + DACA_CONTROL2, 0, 0x00000001);
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RHDRegMask(Output, offset + DACA_CONTROL2, 0, 0x00ff0000);
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if (offset) { /* We can do TV on DACA but only DACB has mux for separate connector */
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if (TV)
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RHDRegMask(Output, offset + DACA_CONTROL2, 0x00000100, 0x00000100);
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else
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RHDRegMask(Output, offset + DACA_CONTROL2, 0, 0x00000100);
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}
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RHDRegWrite(Output, offset + DACA_FORCE_DATA, 0);
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RHDRegMask(Output, offset + DACA_CONTROL2, 0x00000001, 0x0000001);
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RHDRegMask(Output, offset + DACA_COMPARATOR_ENABLE, 0x00070000, 0x00070101);
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RHDRegWrite(Output, offset + DACA_CONTROL1, 0x00050802);
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RHDRegMask(Output, offset + DACA_POWERDOWN, 0, 0x00000001); /* Shut down Bandgap Voltage Reference Power */
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usleep(5);
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RHDRegMask(Output, offset + DACA_POWERDOWN, 0, 0x01010100); /* Shut down RGB */
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RHDRegWrite(Output, offset + DACA_FORCE_DATA, 0x1e6); /* 486 out of 1024 */
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usleep(200);
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RHDRegMask(Output, offset + DACA_POWERDOWN, 0x01010100, 0x01010100); /* Enable RGB */
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usleep(88);
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RHDRegMask(Output, offset + DACA_POWERDOWN, 0, 0x01010100); /* Shut down RGB */
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RHDRegMask(Output, offset + DACA_COMPARATOR_ENABLE, 0x00000100, 0x00000100);
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usleep(100);
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/* Get RGB detect values
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* If only G is detected, we could have a monochrome monitor,
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* but we don't bother with this at the moment.
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*/
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ret = (RHDRegRead(Output, offset + DACA_COMPARATOR_OUTPUT) & 0x0E) >> 1;
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RHDRegMask(Output, offset + DACA_COMPARATOR_ENABLE, CompEnable, 0x00FFFFFF);
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RHDRegWrite(Output, offset + DACA_CONTROL1, Control1);
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RHDRegMask(Output, offset + DACA_CONTROL2, Control2, 0x000001FF);
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RHDRegMask(Output, offset + DACA_AUTODETECT_CONTROL, DetectControl, 0x000000FF);
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RHDRegMask(Output, offset + DACA_ENABLE, Enable, 0x000000FF);
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RHDDebug(Output->scrnIndex, "%s: DAC: 0x0%1X\n", __func__, ret);
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return ret;
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}
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/*
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*
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*/
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static enum rhdSensedOutput
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DACASense(struct rhdOutput *Output, struct rhdConnector *Connector)
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{
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enum rhdConnectorType Type = Connector->Type;
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RHDFUNC(Output);
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switch (Type) {
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case RHD_CONNECTOR_DVI:
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case RHD_CONNECTOR_DVI_SINGLE:
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case RHD_CONNECTOR_VGA:
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return (DACSense(Output, REG_DACA_OFFSET, FALSE) == 0x7)
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? RHD_SENSED_VGA
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: RHD_SENSED_NONE;
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default:
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xf86DrvMsg(Output->scrnIndex, X_WARNING,
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"%s: connector type %d is not supported on DACA.\n",
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__func__, Type);
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return RHD_SENSED_NONE;
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}
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}
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/*
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*
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*/
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static enum rhdSensedOutput
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DACBSense(struct rhdOutput *Output, struct rhdConnector *Connector)
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{
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enum rhdConnectorType Type = Connector->Type;
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RHDFUNC(Output);
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switch (Type) {
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case RHD_CONNECTOR_DVI:
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case RHD_CONNECTOR_DVI_SINGLE:
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case RHD_CONNECTOR_VGA:
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return (DACSense(Output, REG_DACB_OFFSET, FALSE) == 0x7)
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? RHD_SENSED_VGA
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: RHD_SENSED_NONE;
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case RHD_CONNECTOR_TV:
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switch (DACSense(Output, REG_DACB_OFFSET, TRUE) & 0x7) {
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case 0x7:
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return RHD_SENSED_TV_COMPONENT;
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case 0x6:
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return RHD_SENSED_TV_SVIDEO;
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case 0x1:
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return RHD_SENSED_TV_COMPOSITE;
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default:
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return RHD_SENSED_NONE;
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}
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default:
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xf86DrvMsg(Output->scrnIndex, X_WARNING,
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"%s: connector type %d is not supported on DACB.\n",
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__func__, Type);
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return RHD_SENSED_NONE;
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}
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}
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enum outputType {
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TvPAL = 0,
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TvNTSC,
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VGA,
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TvCV,
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typeLast = VGA
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};
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/*
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*
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*/
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static void
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DACGetElectrical(RHDPtr rhdPtr, enum outputType type, int dac, CARD8 *bandgap, CARD8 *whitefine)
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{
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#ifdef ATOM_BIOS
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enum _AtomBiosRequestID bg = 0, wf = 0;
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AtomBiosArgRec atomBiosArg;
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#endif
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struct
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{
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CARD16 pciIdMin;
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CARD16 pciIdMax;
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CARD8 bandgap[2][4];
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CARD8 whitefine[2][4];
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} list[] = {
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{ 0x791E, 0x791F,
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{ { 0x07, 0x07, 0x07, 0x07 },
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{ 0x07, 0x07, 0x07, 0x07 } },
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{ { 0x09, 0x09, 0x04, 0x09 },
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{ 0x09, 0x09, 0x04, 0x09 } },
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},
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{ 0x793F, 0x7942,
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{ { 0x09, 0x09, 0x09, 0x09 },
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{ 0x09, 0x09, 0x09, 0x09 } },
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{ { 0x0a, 0x0a, 0x08, 0x0a },
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{ 0x0a, 0x0a, 0x08, 0x0a } },
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},
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{ 0x9500, 0x9519,
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{ { 0x00, 0x00, 0x00, 0x00 },
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{ 0x00, 0x00, 0x00, 0x00 } },
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{ { 0x00, 0x00, 0x20, 0x00 },
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{ 0x25, 0x25, 0x26, 0x26 } },
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},
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{ 0, 0,
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{ { 0, 0, 0, 0 },
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{ 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0 },
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{ 0, 0, 0, 0 } }
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}
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};
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*bandgap = *whitefine = 0;
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#ifdef ATOM_BIOS
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switch (type) {
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case TvPAL:
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bg = ATOM_DAC2_PAL_BG_ADJ;
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wf = ATOM_DAC2_PAL_DAC_ADJ;
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break;
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case TvNTSC:
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bg = ATOM_DAC2_NTSC_BG_ADJ;
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wf = ATOM_DAC2_NTSC_DAC_ADJ;
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break;
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case TvCV:
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bg = ATOM_DAC2_CV_BG_ADJ;
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wf = ATOM_DAC2_CV_DAC_ADJ;
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break;
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case VGA:
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switch (dac) {
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case 0:
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bg = ATOM_DAC1_BG_ADJ;
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wf = ATOM_DAC1_DAC_ADJ;
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break;
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default:
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bg = ATOM_DAC2_CRTC2_BG_ADJ;
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wf = ATOM_DAC2_CRTC2_DAC_ADJ;
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break;
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}
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break;
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}
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if (RHDAtomBiosFunc(rhdPtr->scrnIndex, rhdPtr->atomBIOS, bg, &atomBiosArg)
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== ATOM_SUCCESS) {
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*bandgap = atomBiosArg.val;
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RHDDebug(rhdPtr->scrnIndex, "%s: BandGap found in CompassionateData.\n",__func__);
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}
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if (RHDAtomBiosFunc(rhdPtr->scrnIndex, rhdPtr->atomBIOS, wf, &atomBiosArg)
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== ATOM_SUCCESS) {
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*whitefine = atomBiosArg.val;
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RHDDebug(rhdPtr->scrnIndex, "%s: WhiteFine found in CompassionateData.\n",__func__);
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}
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if (*whitefine == 0) {
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CARD8 w_f = 0, b_g = 0;
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if (atomBiosArg.val = 0x18,
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RHDAtomBiosFunc(rhdPtr->scrnIndex, rhdPtr->atomBIOS,
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ATOMBIOS_GET_CODE_DATA_TABLE,
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&atomBiosArg) == ATOM_SUCCESS) {
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struct AtomDacCodeTableData *data
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= (struct AtomDacCodeTableData *)atomBiosArg.CommandDataTable.loc;
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if (atomBiosArg.CommandDataTable.size
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< (sizeof (struct AtomDacCodeTableData) >> (dac ? 0 : 1))) { /* IGPs only have 1 DAC -> table_size / 2 */
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xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR,
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"Code table data size: %i doesn't match expected size: %u\n",
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atomBiosArg.CommandDataTable.size,
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(unsigned int) sizeof (struct AtomDacCodeTableData));
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return;
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}
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RHDDebug(rhdPtr->scrnIndex, "%s: WhiteFine found in Code Table.\n",__func__);
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switch (type) {
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case TvPAL:
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w_f = dac ? data->DAC2PALWhiteFine : data->DAC1PALWhiteFine;
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b_g = dac ? data->DAC2PALBandGap : data->DAC1PALBandGap;
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break;
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case TvNTSC:
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w_f = dac ? data->DAC2NTSCWhiteFine : data->DAC1NTSCWhiteFine;
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b_g = dac ? data->DAC2NTSCBandGap : data->DAC1NTSCBandGap;
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break;
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case TvCV:
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w_f = dac ? data->DAC2CVWhiteFine : data->DAC1CVWhiteFine;
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b_g = dac ? data->DAC2CVBandGap : data->DAC1CVBandGap;
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break;
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case VGA:
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w_f = dac ? data->DAC2VGAWhiteFine : data->DAC1VGAWhiteFine;
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b_g = dac ? data->DAC2VGABandGap : data->DAC1VGABandGap;
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break;
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}
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*whitefine = w_f;
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if (rhdPtr->ChipSet >= RHD_RV770) /* Dunno why this is broken on older ASICs */
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*bandgap = b_g;
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}
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}
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#endif
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if (*bandgap == 0 || *whitefine == 0) {
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int i = 0;
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while (list[i].pciIdMin != 0) {
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if (list[i].pciIdMin <= rhdPtr->PciDeviceID
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&& list[i].pciIdMax >= rhdPtr->PciDeviceID) {
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#if 0
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ErrorF(">> %x %x %x -- %x %x\n",list[i].pciIdMin,
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rhdPtr->PciDeviceID,list[i].pciIdMax,
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list[i].bandgap[dac][type],list[i].whitefine[dac][type]);
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ErrorF(">> %i %i\n",dac,type);
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#endif
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if (*bandgap == 0) *bandgap = list[i].bandgap[dac][type];
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if (*whitefine == 0) *whitefine = list[i].whitefine[dac][type];
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break;
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}
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i++;
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}
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if (list[i].pciIdMin != 0)
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RHDDebug(rhdPtr->scrnIndex, "%s: BandGap and WhiteFine found in Table.\n",__func__);
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}
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RHDDebug(rhdPtr->scrnIndex, "%s: DAC[%i] BandGap: 0x%2.2x WhiteFine: 0x%2.2x\n",
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__func__, dac, *bandgap, *whitefine);
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}
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/*
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*
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*/
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static inline void
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DACSet(struct rhdOutput *Output, CARD16 offset)
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{
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RHDPtr rhdPtr = RHDPTRI(Output);
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CARD8 Standard, WhiteFine, Bandgap;
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Bool TV;
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CARD32 Mask = 0;
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switch (Output->SensedType) {
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case RHD_SENSED_TV_SVIDEO:
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case RHD_SENSED_TV_COMPOSITE:
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/* might want to selectively enable lines based on type */
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TV = TRUE;
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switch (rhdPtr->tvMode) {
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case RHD_TV_NTSC:
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case RHD_TV_NTSCJ:
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DACGetElectrical(rhdPtr, TvNTSC, offset ? 1 : 0, &Bandgap, &WhiteFine);
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Standard = 1; /* NTSC */
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break;
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case RHD_TV_PAL:
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case RHD_TV_PALN:
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case RHD_TV_PALCN:
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case RHD_TV_PAL60:
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default:
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DACGetElectrical(rhdPtr, TvPAL, offset ? 1 : 0, &Bandgap, &WhiteFine);
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Standard = 0; /* PAL */
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break;
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}
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break;
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case RHD_SENSED_TV_COMPONENT:
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TV = TRUE;
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DACGetElectrical(rhdPtr, TvCV, offset ? 1 : 0, &Bandgap, &WhiteFine);
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Standard = 3; /* HDTV */
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break;
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case RHD_SENSED_VGA:
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default:
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TV = FALSE;
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DACGetElectrical(rhdPtr, VGA, offset ? 1 : 0, &Bandgap, &WhiteFine);
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Standard = 2; /* VGA */
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break;
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}
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if (Bandgap) Mask |= 0xFF << 16;
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if (WhiteFine) Mask |= 0xFF << 8;
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RHDRegMask(Output, offset + DACA_CONTROL1, Standard, 0x000000FF);
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/* white level fine adjust */
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RHDRegMask(Output, offset + DACA_CONTROL1, (Bandgap << 16) | (WhiteFine << 8), Mask);
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if (TV) {
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/* tv enable */
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if (offset) /* TV mux only available on DACB */
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RHDRegMask(Output, offset + DACA_CONTROL2, 0x00000100, 0x0000FF00);
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/* select tv encoder */
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RHDRegMask(Output, offset + DACA_SOURCE_SELECT, 0x00000002, 0x00000003);
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} else {
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if (offset) /* TV mux only available on DACB */
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RHDRegMask(Output, offset + DACA_CONTROL2, 0, 0x0000FF00);
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/* select a crtc */
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RHDRegMask(Output, offset + DACA_SOURCE_SELECT, Output->Crtc->Id & 0x01, 0x00000003);
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}
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RHDRegMask(Output, offset + DACA_FORCE_OUTPUT_CNTL, 0x00000701, 0x00000701);
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RHDRegMask(Output, offset + DACA_FORCE_DATA, 0, 0x0000FFFF);
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}
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/*
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*
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*/
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static void
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DACASet(struct rhdOutput *Output, DisplayModePtr unused)
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{
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RHDFUNC(Output);
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DACSet(Output, REG_DACA_OFFSET);
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}
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/*
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*
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*/
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static void
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DACBSet(struct rhdOutput *Output, DisplayModePtr unused)
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{
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RHDFUNC(Output);
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DACSet(Output, REG_DACB_OFFSET);
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}
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/*
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*
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*/
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static inline void
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DACPower(struct rhdOutput *Output, CARD16 offset, int Power)
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{
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CARD32 powerdown;
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RHDDebug(Output->scrnIndex, "%s(%s,%s)\n",__func__,Output->Name,
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rhdPowerString[Power]);
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switch (Power) {
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case RHD_POWER_ON:
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switch (Output->SensedType) {
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case RHD_SENSED_TV_SVIDEO:
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powerdown = 0 /* 0x100 */;
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break;
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case RHD_SENSED_TV_COMPOSITE:
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powerdown = 0 /* 0x1010000 */;
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break;
|
|
case RHD_SENSED_TV_COMPONENT:
|
|
powerdown = 0;
|
|
break;
|
|
case RHD_SENSED_VGA:
|
|
default:
|
|
powerdown = 0;
|
|
break;
|
|
}
|
|
RHDRegWrite(Output, offset + DACA_ENABLE, 1);
|
|
RHDRegWrite(Output, offset + DACA_POWERDOWN, 0);
|
|
usleep (14);
|
|
RHDRegMask(Output, offset + DACA_POWERDOWN, powerdown, 0xFFFFFF00);
|
|
usleep(2);
|
|
RHDRegWrite(Output, offset + DACA_FORCE_OUTPUT_CNTL, 0);
|
|
RHDRegMask(Output, offset + DACA_SYNC_SELECT, 0, 0x00000101);
|
|
RHDRegWrite(Output, offset + DACA_SYNC_TRISTATE_CONTROL, 0);
|
|
return;
|
|
case RHD_POWER_RESET: /* don't bother */
|
|
return;
|
|
case RHD_POWER_SHUTDOWN:
|
|
default:
|
|
RHDRegMask(Output, offset + DACA_FORCE_DATA, 0, 0x0000FFFF);
|
|
RHDRegMask(Output, offset + DACA_FORCE_OUTPUT_CNTL, 0x0000701, 0x0000701);
|
|
RHDRegWrite(Output, offset + DACA_POWERDOWN, 0x01010100);
|
|
RHDRegWrite(Output, offset + DACA_POWERDOWN, 0x01010101);
|
|
RHDRegWrite(Output, offset + DACA_ENABLE, 0);
|
|
RHDRegWrite(Output, offset + DACA_ENABLE, 0);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACAPower(struct rhdOutput *Output, int Power)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACPower(Output, REG_DACA_OFFSET, Power);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBPower(struct rhdOutput *Output, int Power)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACPower(Output, REG_DACB_OFFSET, Power);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static inline void
|
|
DACSave(struct rhdOutput *Output, CARD16 offset)
|
|
{
|
|
struct rhdDACPrivate *Private = (struct rhdDACPrivate *) Output->Private;
|
|
|
|
Private->Store_Powerdown = RHDRegRead(Output, offset + DACA_POWERDOWN);
|
|
Private->Store_Force_Output_Control = RHDRegRead(Output, offset + DACA_FORCE_OUTPUT_CNTL);
|
|
Private->Store_Force_Data = RHDRegRead(Output, offset + DACA_FORCE_DATA);
|
|
Private->Store_Source_Select = RHDRegRead(Output, offset + DACA_SOURCE_SELECT);
|
|
Private->Store_Sync_Select = RHDRegRead(Output, offset + DACA_SYNC_SELECT);
|
|
Private->Store_Enable = RHDRegRead(Output, offset + DACA_ENABLE);
|
|
Private->Store_Control1 = RHDRegRead(Output, offset + DACA_CONTROL1);
|
|
Private->Store_Control2 = RHDRegRead(Output, offset + DACA_CONTROL2);
|
|
Private->Store_Tristate_Control = RHDRegRead(Output, offset + DACA_SYNC_TRISTATE_CONTROL);
|
|
|
|
Private->Stored = TRUE;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACASave(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACSave(Output, REG_DACA_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBSave(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACSave(Output, REG_DACB_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static inline void
|
|
DACRestore(struct rhdOutput *Output, CARD16 offset)
|
|
{
|
|
struct rhdDACPrivate *Private = (struct rhdDACPrivate *) Output->Private;
|
|
|
|
RHDRegWrite(Output, offset + DACA_POWERDOWN, Private->Store_Powerdown);
|
|
RHDRegWrite(Output, offset + DACA_FORCE_OUTPUT_CNTL, Private->Store_Force_Output_Control);
|
|
RHDRegWrite(Output, offset + DACA_FORCE_DATA, Private->Store_Force_Data);
|
|
RHDRegWrite(Output, offset + DACA_SOURCE_SELECT, Private->Store_Source_Select);
|
|
RHDRegWrite(Output, offset + DACA_SYNC_SELECT, Private->Store_Sync_Select);
|
|
RHDRegWrite(Output, offset + DACA_ENABLE, Private->Store_Enable);
|
|
RHDRegWrite(Output, offset + DACA_CONTROL1, Private->Store_Control1);
|
|
RHDRegWrite(Output, offset + DACA_CONTROL2, Private->Store_Control2);
|
|
RHDRegWrite(Output, offset + DACA_SYNC_TRISTATE_CONTROL, Private->Store_Tristate_Control);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACARestore(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
if (!((struct rhdDACPrivate *) Output->Private)->Stored) {
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR,
|
|
"%s: No registers stored.\n", __func__);
|
|
return;
|
|
}
|
|
|
|
DACRestore(Output, REG_DACA_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBRestore(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
if (!((struct rhdDACPrivate *) Output->Private)->Stored) {
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR,
|
|
"%s: No registers stored.\n", __func__);
|
|
return;
|
|
}
|
|
|
|
DACRestore(Output, REG_DACB_OFFSET);
|
|
}
|
|
|
|
/* ----------------------------------------------------------- */
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static CARD32
|
|
DACSenseRV620(struct rhdOutput *Output, CARD32 offset, Bool TV)
|
|
{
|
|
CARD32 ret;
|
|
CARD32 DetectControl, AutodetectIntCtl, ForceData,
|
|
Control1, Control2, CompEnable;
|
|
|
|
RHDFUNC(Output);
|
|
|
|
Control1 = RHDRegRead(Output, offset + RV620_DACA_MACRO_CNTL); /* 7ef4 */
|
|
Control2 = RHDRegRead(Output, offset + RV620_DACA_CONTROL2); /* 7058 */
|
|
ForceData = RHDRegRead(Output, offset + RV620_DACA_FORCE_DATA);
|
|
AutodetectIntCtl = RHDRegRead(Output, offset + RV620_DACA_AUTODETECT_INT_CONTROL);
|
|
DetectControl = RHDRegRead(Output, offset + RV620_DACA_AUTODETECT_CONTROL);
|
|
CompEnable = RHDRegRead(Output, offset + RV620_DACA_COMPARATOR_ENABLE);
|
|
|
|
if (offset) { /* We can do TV on DACA but only DACB has mux for separate connector */
|
|
if (TV)
|
|
RHDRegMask(Output, offset + RV620_DACA_CONTROL2, 0x100, 0xff00);
|
|
else
|
|
RHDRegMask(Output, offset + RV620_DACA_CONTROL2, 0x00, 0xff00);
|
|
}
|
|
RHDRegMask(Output, offset + RV620_DACA_FORCE_DATA, 0x18, 0xffff);
|
|
RHDRegMask(Output, offset + RV620_DACA_AUTODETECT_INT_CONTROL, 0x01, 0x01);
|
|
RHDRegMask(Output, offset + RV620_DACA_AUTODETECT_CONTROL, 0x00, 0xff);
|
|
RHDRegMask(Output, offset + RV620_DACA_MACRO_CNTL,
|
|
(offset > 0) ? 0x2502 : 0x2002, 0xffff);
|
|
/* enable comparators for R/G/B, disable DDET and SDET reference */
|
|
RHDRegMask(Output, offset + RV620_DACA_COMPARATOR_ENABLE, 0x70000, 0x070101);
|
|
RHDRegMask(Output, offset + RV620_DACA_AUTODETECT_CONTROL, 0x01, 0xff);
|
|
usleep(32);
|
|
ret = RHDRegRead(Output, offset + RV620_DACA_AUTODETECT_STATUS);
|
|
RHDRegWrite(Output, offset + RV620_DACA_AUTODETECT_CONTROL, DetectControl);
|
|
RHDRegWrite(Output, offset + RV620_DACA_MACRO_CNTL, Control1);
|
|
RHDRegWrite(Output, offset + RV620_DACA_CONTROL2, Control2);
|
|
RHDRegWrite(Output, offset + RV620_DACA_FORCE_DATA, ForceData);
|
|
RHDRegWrite(Output, offset + RV620_DACA_AUTODETECT_INT_CONTROL, AutodetectIntCtl);
|
|
#ifdef DEBUG
|
|
RHDDebug(Output->scrnIndex, "DAC%i: ret = 0x%x %s\n",offset ? "A" : "B",
|
|
ret,TV ? "TV" : "");
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static enum rhdSensedOutput
|
|
DACASenseRV620(struct rhdOutput *Output, struct rhdConnector *Connector)
|
|
{
|
|
enum rhdConnectorType Type = Connector->Type;
|
|
RHDFUNC(Output);
|
|
|
|
switch (Type) {
|
|
case RHD_CONNECTOR_DVI:
|
|
case RHD_CONNECTOR_DVI_SINGLE:
|
|
case RHD_CONNECTOR_VGA:
|
|
return (DACSenseRV620(Output, RV620_REG_DACA_OFFSET, FALSE)
|
|
& 0x1010100) ? RHD_SENSED_VGA : RHD_SENSED_NONE;
|
|
case RHD_CONNECTOR_TV:
|
|
switch (DACSenseRV620(Output, RV620_REG_DACA_OFFSET, TRUE)
|
|
& 0x1010100) {
|
|
case 0x1010100:
|
|
return RHD_SENSED_NONE; /* on DAC A we cannot distinguish VGA and CV */
|
|
case 0x10100:
|
|
return RHD_SENSED_TV_SVIDEO;
|
|
case 0x1000000:
|
|
return RHD_SENSED_TV_COMPOSITE;
|
|
default:
|
|
return RHD_SENSED_NONE;
|
|
}
|
|
default:
|
|
xf86DrvMsg(Output->scrnIndex, X_WARNING,
|
|
"%s: connector type %d is not supported.\n",
|
|
__func__, Type);
|
|
return RHD_SENSED_NONE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static enum rhdSensedOutput
|
|
DACBSenseRV620(struct rhdOutput *Output, struct rhdConnector *Connector)
|
|
{
|
|
enum rhdConnectorType Type = Connector->Type;
|
|
RHDFUNC(Output);
|
|
|
|
switch (Type) {
|
|
case RHD_CONNECTOR_DVI:
|
|
case RHD_CONNECTOR_DVI_SINGLE:
|
|
case RHD_CONNECTOR_VGA:
|
|
return (DACSenseRV620(Output, RV620_REG_DACB_OFFSET, FALSE)
|
|
& 0x1010100) ? RHD_SENSED_VGA : RHD_SENSED_NONE;
|
|
case RHD_CONNECTOR_TV:
|
|
switch (DACSenseRV620(Output, RV620_REG_DACB_OFFSET, TRUE)
|
|
& 0x1010100) {
|
|
case 0x1000000:
|
|
return RHD_SENSED_TV_COMPONENT;
|
|
case 0x1010100:
|
|
return RHD_SENSED_TV_SVIDEO;
|
|
case 0x10100:
|
|
return RHD_SENSED_TV_COMPOSITE;
|
|
default:
|
|
return RHD_SENSED_NONE;
|
|
}
|
|
default:
|
|
xf86DrvMsg(Output->scrnIndex, X_WARNING,
|
|
"%s: connector type %d is not supported.\n",
|
|
__func__, Type);
|
|
return RHD_SENSED_NONE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static inline void
|
|
DACSetRV620(struct rhdOutput *Output, CARD16 offset)
|
|
{
|
|
RHDPtr rhdPtr = RHDPTRI(Output);
|
|
CARD32 Source;
|
|
CARD32 Mode;
|
|
CARD32 TV;
|
|
CARD8 WhiteFine, Bandgap;
|
|
CARD32 Mask = 0;
|
|
|
|
switch (Output->SensedType) {
|
|
case RHD_SENSED_TV_SVIDEO:
|
|
case RHD_SENSED_TV_COMPOSITE:
|
|
TV = 0x1;
|
|
Source = 0x2; /* tv encoder */
|
|
switch (rhdPtr->tvMode) {
|
|
case RHD_TV_NTSC:
|
|
case RHD_TV_NTSCJ:
|
|
DACGetElectrical(rhdPtr, TvNTSC, offset ? 1 : 0, &Bandgap, &WhiteFine);
|
|
Mode = 1;
|
|
break;
|
|
case RHD_TV_PAL:
|
|
case RHD_TV_PALN:
|
|
case RHD_TV_PALCN:
|
|
case RHD_TV_PAL60:
|
|
default:
|
|
DACGetElectrical(rhdPtr, TvPAL, offset ? 1 : 0, &Bandgap, &WhiteFine);
|
|
Mode = 0;
|
|
break;
|
|
}
|
|
break;
|
|
case RHD_SENSED_TV_COMPONENT:
|
|
DACGetElectrical(rhdPtr, TvCV, offset ? 1 : 0, &Bandgap, &WhiteFine);
|
|
Mode = 3; /* HDTV */
|
|
TV = 0x1; /* tv on?? */
|
|
Source = 0x2; /* tv encoder ?? */
|
|
break;
|
|
case RHD_SENSED_VGA:
|
|
default:
|
|
DACGetElectrical(rhdPtr, VGA, offset ? 1 : 0, &Bandgap, &WhiteFine);
|
|
Mode = 2;
|
|
TV = 0;
|
|
Source = Output->Crtc->Id;
|
|
break;
|
|
}
|
|
if (Bandgap) Mask |= 0xFF << 16;
|
|
if (WhiteFine) Mask |= 0xFF << 8;
|
|
|
|
RHDRegMask(Output, offset + RV620_DACA_MACRO_CNTL, Mode, 0xFF); /* no fine control yet */
|
|
RHDRegMask(Output, offset + RV620_DACA_SOURCE_SELECT, Source, 0x00000003);
|
|
if (offset) /* TV mux only present on DACB */
|
|
RHDRegMask(Output, offset + RV620_DACA_CONTROL2, TV << 8, 0x0100); /* tv enable/disable */
|
|
/* use fine control from white_fine control register */
|
|
RHDRegMask(Output, offset + RV620_DACA_AUTO_CALIB_CONTROL, 0x0, 0x4);
|
|
RHDRegMask(Output, offset + RV620_DACA_BGADJ_SRC, 0x0, 0x30);
|
|
RHDRegMask(Output, offset + RV620_DACA_MACRO_CNTL, (Bandgap << 16) | (WhiteFine << 8), Mask);
|
|
/* Reset the FMT register on CRTC leading to this output */
|
|
Output->Crtc->FMTModeSet(Output->Crtc, NULL);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACASetRV620(struct rhdOutput *Output, DisplayModePtr unused)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACSetRV620(Output, RV620_REG_DACA_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBSetRV620(struct rhdOutput *Output, DisplayModePtr unused)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACSetRV620(Output, RV620_REG_DACB_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static inline void
|
|
DACPowerRV620(struct rhdOutput *Output, CARD16 offset, int Power)
|
|
{
|
|
CARD32 powerdown;
|
|
|
|
switch (Power) {
|
|
case RHD_POWER_ON:
|
|
switch (Output->SensedType) {
|
|
case RHD_SENSED_TV_SVIDEO:
|
|
powerdown = 0 /* 0x100 */;
|
|
break;
|
|
case RHD_SENSED_TV_COMPOSITE:
|
|
powerdown = 0 /* 0x1010000 */;
|
|
break;
|
|
case RHD_SENSED_TV_COMPONENT:
|
|
powerdown = 0;
|
|
break;
|
|
case RHD_SENSED_VGA:
|
|
default:
|
|
powerdown = 0;
|
|
break;
|
|
}
|
|
|
|
if (!(RHDRegRead(Output, offset + RV620_DACA_ENABLE) & 0x01))
|
|
RHDRegMask(Output, offset + RV620_DACA_ENABLE, 0x1, 0xff);
|
|
RHDRegMask(Output, offset + RV620_DACA_FORCE_OUTPUT_CNTL, 0x01, 0x01);
|
|
RHDRegMask(Output, offset + RV620_DACA_POWERDOWN, 0x0, 0xff);
|
|
usleep (0x14);
|
|
RHDRegMask(Output, offset + RV620_DACA_POWERDOWN, powerdown, 0xffffff00);
|
|
usleep(2);
|
|
RHDRegMask(Output, offset + RV620_DACA_FORCE_DATA, 0, 0x0000ffff);
|
|
RHDRegWrite(Output, offset + RV620_DACA_FORCE_OUTPUT_CNTL, 0x0);
|
|
RHDRegWrite(Output, offset + RV620_DACA_SYNC_TRISTATE_CONTROL, 0);
|
|
return;
|
|
case RHD_POWER_RESET: /* don't bother */
|
|
return;
|
|
case RHD_POWER_SHUTDOWN:
|
|
default:
|
|
RHDRegWrite(Output, offset + RV620_DACA_POWERDOWN, 0x01010100);
|
|
RHDRegWrite(Output, offset + RV620_DACA_POWERDOWN, 0x01010101);
|
|
RHDRegWrite(Output, offset + RV620_DACA_ENABLE, 0);
|
|
RHDRegMask(Output, offset + RV620_DACA_FORCE_DATA, 0, 0xffff);
|
|
RHDRegMask(Output, offset + RV620_DACA_FORCE_OUTPUT_CNTL, 0x701, 0x701);
|
|
return;
|
|
}
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACAPowerRV620(struct rhdOutput *Output, int Power)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACPowerRV620(Output, RV620_REG_DACA_OFFSET, Power);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBPowerRV620(struct rhdOutput *Output, int Power)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACPowerRV620(Output, RV620_REG_DACB_OFFSET, Power);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static inline void
|
|
DACSaveRV620(struct rhdOutput *Output, CARD16 offset)
|
|
{
|
|
struct rhdDACPrivate *Private = (struct rhdDACPrivate *) Output->Private;
|
|
|
|
Private->Store_Powerdown = RHDRegRead(Output, offset + RV620_DACA_POWERDOWN);
|
|
Private->Store_Force_Output_Control = RHDRegRead(Output, offset + RV620_DACA_FORCE_OUTPUT_CNTL);
|
|
Private->Store_Force_Data = RHDRegRead(Output, offset + RV620_DACA_FORCE_DATA);
|
|
Private->Store_Source_Select = RHDRegRead(Output, offset + RV620_DACA_SOURCE_SELECT);
|
|
Private->Store_Enable = RHDRegRead(Output, offset + RV620_DACA_ENABLE);
|
|
Private->Store_Control1 = RHDRegRead(Output, offset + RV620_DACA_MACRO_CNTL);
|
|
Private->Store_Control2 = RHDRegRead(Output, offset + RV620_DACA_CONTROL2);
|
|
Private->Store_Tristate_Control = RHDRegRead(Output, offset + RV620_DACA_SYNC_TRISTATE_CONTROL);
|
|
Private->Store_Auto_Calib_Control = RHDRegRead(Output, offset + RV620_DACA_AUTO_CALIB_CONTROL);
|
|
Private->Store_Dac_Bgadj_Src = RHDRegRead(Output, offset + RV620_DACA_BGADJ_SRC);
|
|
|
|
Private->Stored = TRUE;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACASaveRV620(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACSaveRV620(Output, RV620_REG_DACA_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBSaveRV620(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
DACSaveRV620(Output, RV620_REG_DACB_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static inline void
|
|
DACRestoreRV620(struct rhdOutput *Output, CARD16 offset)
|
|
{
|
|
struct rhdDACPrivate *Private = (struct rhdDACPrivate *) Output->Private;
|
|
|
|
RHDRegWrite(Output, offset + RV620_DACA_BGADJ_SRC, Private->Store_Dac_Bgadj_Src);
|
|
RHDRegWrite(Output, offset + RV620_DACA_AUTO_CALIB_CONTROL, Private->Store_Auto_Calib_Control);
|
|
RHDRegWrite(Output, offset + RV620_DACA_POWERDOWN, Private->Store_Powerdown);
|
|
RHDRegWrite(Output, offset + RV620_DACA_FORCE_OUTPUT_CNTL, Private->Store_Force_Output_Control);
|
|
RHDRegWrite(Output, offset + RV620_DACA_FORCE_DATA, Private->Store_Force_Data);
|
|
RHDRegWrite(Output, offset + RV620_DACA_SOURCE_SELECT, Private->Store_Source_Select);
|
|
RHDRegWrite(Output, offset + RV620_DACA_ENABLE, Private->Store_Enable);
|
|
RHDRegWrite(Output, offset + RV620_DACA_MACRO_CNTL, Private->Store_Control1);
|
|
RHDRegWrite(Output, offset + RV620_DACA_CONTROL2, Private->Store_Control2);
|
|
RHDRegWrite(Output, offset + RV620_DACA_SYNC_TRISTATE_CONTROL, Private->Store_Tristate_Control);
|
|
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACARestoreRV620(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
if (!((struct rhdDACPrivate *) Output->Private)->Stored) {
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR,
|
|
"%s: No registers stored.\n", __func__);
|
|
return;
|
|
}
|
|
DACRestoreRV620(Output, RV620_REG_DACA_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACBRestoreRV620(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
if (!((struct rhdDACPrivate *) Output->Private)->Stored) {
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR,
|
|
"%s: No registers stored.\n", __func__);
|
|
return;
|
|
}
|
|
|
|
DACRestoreRV620(Output, RV620_REG_DACB_OFFSET);
|
|
}
|
|
|
|
/* ----------------------------------------------------------- */
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static ModeStatus
|
|
DACModeValid(struct rhdOutput *Output, DisplayModePtr Mode)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
if (Mode->Clock < 20000)
|
|
return MODE_CLOCK_LOW;
|
|
|
|
if (Mode->Clock > 400000)
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
static void
|
|
DACDestroy(struct rhdOutput *Output)
|
|
{
|
|
RHDFUNC(Output);
|
|
|
|
if (!Output->Private)
|
|
return;
|
|
|
|
xfree(Output->Private);
|
|
Output->Private = NULL;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
struct rhdOutput *
|
|
RHDDACAInit(RHDPtr rhdPtr)
|
|
{
|
|
struct rhdOutput *Output;
|
|
struct rhdDACPrivate *Private;
|
|
|
|
RHDFUNC(rhdPtr);
|
|
|
|
Output = xnfcalloc(sizeof(struct rhdOutput), 1);
|
|
|
|
Output->scrnIndex = rhdPtr->scrnIndex;
|
|
Output->Name = "DAC A";
|
|
Output->Id = RHD_OUTPUT_DACA;
|
|
|
|
if (rhdPtr->ChipSet < RHD_RV620) {
|
|
Output->Sense = DACASense;
|
|
Output->Mode = DACASet;
|
|
Output->Power = DACAPower;
|
|
Output->Save = DACASave;
|
|
Output->Restore = DACARestore;
|
|
} else {
|
|
Output->Sense = DACASenseRV620;
|
|
Output->Mode = DACASetRV620;
|
|
Output->Power = DACAPowerRV620;
|
|
Output->Save = DACASaveRV620;
|
|
Output->Restore = DACARestoreRV620;
|
|
}
|
|
Output->ModeValid = DACModeValid;
|
|
Output->Destroy = DACDestroy;
|
|
Private = xnfcalloc(sizeof(struct rhdDACPrivate), 1);
|
|
Output->Private = Private;
|
|
|
|
return Output;
|
|
}
|
|
|
|
/*
|
|
*
|
|
*/
|
|
struct rhdOutput *
|
|
RHDDACBInit(RHDPtr rhdPtr)
|
|
{
|
|
struct rhdOutput *Output;
|
|
struct rhdDACPrivate *Private;
|
|
|
|
RHDFUNC(rhdPtr);
|
|
|
|
Output = xnfcalloc(sizeof(struct rhdOutput), 1);
|
|
|
|
Output->scrnIndex = rhdPtr->scrnIndex;
|
|
Output->Name = "DAC B";
|
|
Output->Id = RHD_OUTPUT_DACB;
|
|
|
|
if (rhdPtr->ChipSet < RHD_RV620) {
|
|
Output->Sense = DACBSense;
|
|
Output->Mode = DACBSet;
|
|
Output->Power = DACBPower;
|
|
Output->Save = DACBSave;
|
|
Output->Restore = DACBRestore;
|
|
} else {
|
|
Output->Sense = DACBSenseRV620;
|
|
Output->Mode = DACBSetRV620;
|
|
Output->Power = DACBPowerRV620;
|
|
Output->Save = DACBSaveRV620;
|
|
Output->Restore = DACBRestoreRV620;
|
|
}
|
|
Output->ModeValid = DACModeValid;
|
|
Output->Destroy = DACDestroy;
|
|
|
|
Private = xnfcalloc(sizeof(struct rhdDACPrivate), 1);
|
|
Output->Private = Private;
|
|
|
|
return Output;
|
|
}
|