forked from KolibriOS/kolibrios
477 lines
13 KiB
C
477 lines
13 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <ttm/ttm_bo_api.h>
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#include <ttm/ttm_bo_driver.h>
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#include <ttm/ttm_placement.h>
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#include <ttm/ttm_module.h>
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#include <ttm/ttm_page_alloc.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
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static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
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static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
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{
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struct radeon_mman *mman;
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struct radeon_device *rdev;
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mman = container_of(bdev, struct radeon_mman, bdev);
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rdev = container_of(mman, struct radeon_device, mman);
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return rdev;
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}
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/*
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* Global memory.
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*/
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static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
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{
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return ttm_mem_global_init(ref->object);
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}
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static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
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{
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ttm_mem_global_release(ref->object);
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}
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static int radeon_ttm_global_init(struct radeon_device *rdev)
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{
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struct drm_global_reference *global_ref;
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int r;
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ENTER();
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rdev->mman.mem_global_referenced = false;
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global_ref = &rdev->mman.mem_global_ref;
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global_ref->global_type = DRM_GLOBAL_TTM_MEM;
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global_ref->size = sizeof(struct ttm_mem_global);
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global_ref->init = &radeon_ttm_mem_global_init;
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global_ref->release = &radeon_ttm_mem_global_release;
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r = drm_global_item_ref(global_ref);
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if (r != 0) {
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DRM_ERROR("Failed setting up TTM memory accounting "
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"subsystem.\n");
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return r;
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}
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rdev->mman.bo_global_ref.mem_glob =
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rdev->mman.mem_global_ref.object;
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global_ref = &rdev->mman.bo_global_ref.ref;
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global_ref->global_type = DRM_GLOBAL_TTM_BO;
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global_ref->size = sizeof(struct ttm_bo_global);
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global_ref->init = &ttm_bo_global_init;
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global_ref->release = &ttm_bo_global_release;
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r = drm_global_item_ref(global_ref);
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if (r != 0) {
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DRM_ERROR("Failed setting up TTM BO subsystem.\n");
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drm_global_item_unref(&rdev->mman.mem_global_ref);
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return r;
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}
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rdev->mman.mem_global_referenced = true;
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LEAVE();
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return 0;
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}
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static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
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{
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return 0;
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}
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static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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struct ttm_mem_type_manager *man)
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{
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struct radeon_device *rdev;
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ENTER();
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rdev = radeon_get_rdev(bdev);
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switch (type) {
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case TTM_PL_SYSTEM:
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/* System memory */
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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case TTM_PL_TT:
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man->func = &ttm_bo_manager_func;
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man->gpu_offset = rdev->mc.gtt_start;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
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#if __OS_HAS_AGP
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if (rdev->flags & RADEON_IS_AGP) {
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if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
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DRM_ERROR("AGP is not enabled for memory type %u\n",
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(unsigned)type);
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return -EINVAL;
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}
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if (!rdev->ddev->agp->cant_use_aperture)
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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}
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#endif
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break;
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case TTM_PL_VRAM:
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/* "On-card" video ram */
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man->func = &ttm_bo_manager_func;
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man->gpu_offset = rdev->mc.vram_start;
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man->flags = TTM_MEMTYPE_FLAG_FIXED |
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TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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LEAVE();
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return 0;
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}
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static void radeon_evict_flags(struct ttm_buffer_object *bo,
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struct ttm_placement *placement)
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{
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struct radeon_bo *rbo;
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static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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if (!radeon_ttm_bo_is_radeon_bo(bo)) {
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placement->fpfn = 0;
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placement->lpfn = 0;
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placement->placement = &placements;
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placement->busy_placement = &placements;
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placement->num_placement = 1;
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placement->num_busy_placement = 1;
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return;
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}
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rbo = container_of(bo, struct radeon_bo, tbo);
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
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else
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
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break;
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case TTM_PL_TT:
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default:
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
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}
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*placement = rbo->placement;
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}
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static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
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{
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return 0;
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}
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static void radeon_move_null(struct ttm_buffer_object *bo,
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struct ttm_mem_reg *new_mem)
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{
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struct ttm_mem_reg *old_mem = &bo->mem;
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BUG_ON(old_mem->mm_node != NULL);
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*old_mem = *new_mem;
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new_mem->mm_node = NULL;
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}
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static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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{
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}
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static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible)
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{
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return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
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}
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static int radeon_sync_obj_flush(void *sync_obj)
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{
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return 0;
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}
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static void radeon_sync_obj_unref(void **sync_obj)
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{
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radeon_fence_unref((struct radeon_fence **)sync_obj);
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}
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static void *radeon_sync_obj_ref(void *sync_obj)
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{
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return radeon_fence_ref((struct radeon_fence *)sync_obj);
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}
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static bool radeon_sync_obj_signaled(void *sync_obj)
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{
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return radeon_fence_signaled((struct radeon_fence *)sync_obj);
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}
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/*
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* TTM backend functions.
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*/
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struct radeon_ttm_tt {
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struct ttm_dma_tt ttm;
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struct radeon_device *rdev;
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u64 offset;
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};
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static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
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struct ttm_mem_reg *bo_mem)
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{
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struct radeon_ttm_tt *gtt = (void*)ttm;
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int r;
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gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
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if (!ttm->num_pages) {
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WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
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ttm->num_pages, bo_mem, ttm);
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}
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r = radeon_gart_bind(gtt->rdev, gtt->offset,
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ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
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if (r) {
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DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
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ttm->num_pages, (unsigned)gtt->offset);
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return r;
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}
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return 0;
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}
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static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
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{
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struct radeon_ttm_tt *gtt = (void *)ttm;
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radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
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return 0;
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}
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static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
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{
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struct radeon_ttm_tt *gtt = (void *)ttm;
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ttm_dma_tt_fini(>t->ttm);
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kfree(gtt);
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}
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static struct ttm_backend_func radeon_backend_func = {
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.bind = &radeon_ttm_backend_bind,
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.unbind = &radeon_ttm_backend_unbind,
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.destroy = &radeon_ttm_backend_destroy,
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};
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static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
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unsigned long size, uint32_t page_flags,
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struct page *dummy_read_page)
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{
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struct radeon_device *rdev;
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struct radeon_ttm_tt *gtt;
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rdev = radeon_get_rdev(bdev);
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#if __OS_HAS_AGP
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if (rdev->flags & RADEON_IS_AGP) {
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return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
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size, page_flags, dummy_read_page);
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}
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#endif
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gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
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if (gtt == NULL) {
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return NULL;
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}
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gtt->ttm.ttm.func = &radeon_backend_func;
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gtt->rdev = rdev;
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if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
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kfree(gtt);
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return NULL;
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}
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return >t->ttm.ttm;
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}
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static struct ttm_bo_driver radeon_bo_driver = {
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.ttm_tt_create = &radeon_ttm_tt_create,
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// .ttm_tt_populate = &radeon_ttm_tt_populate,
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// .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
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// .invalidate_caches = &radeon_invalidate_caches,
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.init_mem_type = &radeon_init_mem_type,
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// .evict_flags = &radeon_evict_flags,
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// .move = &radeon_bo_move,
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// .verify_access = &radeon_verify_access,
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// .sync_obj_signaled = &radeon_sync_obj_signaled,
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// .sync_obj_wait = &radeon_sync_obj_wait,
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// .sync_obj_flush = &radeon_sync_obj_flush,
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// .sync_obj_unref = &radeon_sync_obj_unref,
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// .sync_obj_ref = &radeon_sync_obj_ref,
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// .move_notify = &radeon_bo_move_notify,
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// .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
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// .io_mem_reserve = &radeon_ttm_io_mem_reserve,
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// .io_mem_free = &radeon_ttm_io_mem_free,
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};
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int radeon_ttm_init(struct radeon_device *rdev)
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{
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int r;
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ENTER();
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r = radeon_ttm_global_init(rdev);
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if (r) {
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return r;
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}
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/* No others user of address space so set it to 0 */
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r = ttm_bo_device_init(&rdev->mman.bdev,
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rdev->mman.bo_global_ref.ref.object,
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&radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
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rdev->need_dma32);
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if (r) {
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DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
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return r;
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}
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rdev->mman.initialized = true;
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r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
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rdev->mc.real_vram_size >> PAGE_SHIFT);
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if (r) {
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DRM_ERROR("Failed initializing VRAM heap.\n");
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return r;
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}
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// r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
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// RADEON_GEM_DOMAIN_VRAM,
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// NULL, &rdev->stollen_vga_memory);
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// if (r) {
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// return r;
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// }
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// r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
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// if (r)
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// return r;
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// r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
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// radeon_bo_unreserve(rdev->stollen_vga_memory);
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// if (r) {
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// radeon_bo_unref(&rdev->stollen_vga_memory);
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// return r;
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// }
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DRM_INFO("radeon: %uM of VRAM memory ready\n",
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(unsigned)rdev->mc.real_vram_size / (1024 * 1024));
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r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
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rdev->mc.gtt_size >> PAGE_SHIFT);
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if (r) {
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DRM_ERROR("Failed initializing GTT heap.\n");
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return r;
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}
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DRM_INFO("radeon: %uM of GTT memory ready.\n",
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(unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
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rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
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LEAVE();
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return 0;
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}
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/* this should only be called at bootup or when userspace
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* isn't running */
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void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
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{
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struct ttm_mem_type_manager *man;
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if (!rdev->mman.initialized)
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return;
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man = &rdev->mman.bdev.man[TTM_PL_VRAM];
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/* this just adjusts TTM size idea, which sets lpfn to the correct value */
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man->size = size >> PAGE_SHIFT;
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}
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static struct vm_operations_struct radeon_ttm_vm_ops;
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static const struct vm_operations_struct *ttm_vm_ops = NULL;
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#if 0
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radeon_bo_init
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{
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<6>[drm] Detected VRAM RAM=1024M, BAR=256M
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<6>[drm] RAM width 128bits DDR
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radeon_ttm_init
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{
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radeon_ttm_global_init
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{
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radeon_ttm_mem_global_init
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ttm_bo_global_init
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}
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ttm_bo_device_init
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{
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ttm_bo_init_mm
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{
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radeon_init_mem_type
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};
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}
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ttm_bo_init_mm
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{
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radeon_init_mem_type
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ttm_bo_man_init
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}
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<6>[drm] radeon: 1024M of VRAM memory ready
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ttm_bo_init_mm
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{
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radeon_init_mem_type
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ttm_bo_man_init
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}
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<6>[drm] radeon: 512M of GTT memory ready.
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}
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};
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#endif
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