forked from KolibriOS/kolibrios
780 lines
20 KiB
C
780 lines
20 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <list.h>
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#include <drmP.h>
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#include "radeon_drm.h"
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#include "radeon.h"
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#include <drm_mm.h>
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#include "radeon_object.h"
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int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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int pages, u32_t *pagelist);
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static struct drm_mm mm_gtt;
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static struct drm_mm mm_vram;
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int radeon_object_init(struct radeon_device *rdev)
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{
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int r = 0;
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dbgprintf("%s\n",__FUNCTION__);
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r = drm_mm_init(&mm_vram, 0x800000 >> PAGE_SHIFT,
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((rdev->mc.aper_size - 0x800000) >> PAGE_SHIFT));
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if (r) {
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DRM_ERROR("Failed initializing VRAM heap.\n");
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return r;
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};
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r = drm_mm_init(&mm_gtt, 0, ((rdev->mc.gtt_size) >> PAGE_SHIFT));
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if (r) {
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DRM_ERROR("Failed initializing GTT heap.\n");
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return r;
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}
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return r;
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// return radeon_ttm_init(rdev);
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}
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static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
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{
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uint32_t flags = 0;
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if (domain & RADEON_GEM_DOMAIN_VRAM) {
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flags |= TTM_PL_FLAG_VRAM;
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}
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if (domain & RADEON_GEM_DOMAIN_GTT) {
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flags |= TTM_PL_FLAG_TT;
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}
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if (domain & RADEON_GEM_DOMAIN_CPU) {
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flags |= TTM_PL_FLAG_SYSTEM;
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}
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if (!flags) {
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flags |= TTM_PL_FLAG_SYSTEM;
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}
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return flags;
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}
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int radeon_object_create(struct radeon_device *rdev,
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struct drm_gem_object *gobj,
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unsigned long size,
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bool kernel,
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uint32_t domain,
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bool interruptible,
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struct radeon_object **robj_ptr)
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{
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struct radeon_object *robj;
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enum ttm_bo_type type;
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uint32_t flags;
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int r;
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dbgprintf("%s\n",__FUNCTION__);
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else {
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type = ttm_bo_type_device;
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}
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*robj_ptr = NULL;
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robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
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if (robj == NULL) {
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return -ENOMEM;
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}
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robj->rdev = rdev;
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// robj->gobj = gobj;
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INIT_LIST_HEAD(&robj->list);
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flags = radeon_object_flags_from_domain(domain);
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robj->flags = flags;
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dbgprintf("robj flags %x\n", robj->flags);
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if( flags & TTM_PL_FLAG_VRAM)
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{
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size_t num_pages;
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struct drm_mm_node *vm_node;
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num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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if (num_pages == 0) {
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printk("Illegal buffer object size.\n");
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return -EINVAL;
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}
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retry_pre_get:
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r = drm_mm_pre_get(&mm_vram);
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if (unlikely(r != 0))
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return r;
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vm_node = drm_mm_search_free(&mm_vram, num_pages, 0, 0);
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if (unlikely(vm_node == NULL)) {
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r = -ENOMEM;
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return r;
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}
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robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0);
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if (unlikely(robj->mm_node == NULL)) {
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goto retry_pre_get;
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}
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robj->vm_addr = ((uint32_t)robj->mm_node->start);
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dbgprintf("alloc vram: base %x size %x\n",
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robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT);
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};
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if( flags & TTM_PL_FLAG_TT)
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{
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size_t num_pages;
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struct drm_mm_node *vm_node;
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num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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if (num_pages == 0) {
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printk("Illegal buffer object size.\n");
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return -EINVAL;
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}
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retry_pre_get1:
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r = drm_mm_pre_get(&mm_gtt);
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if (unlikely(r != 0))
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return r;
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vm_node = drm_mm_search_free(&mm_gtt, num_pages, 0, 0);
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if (unlikely(vm_node == NULL)) {
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r = -ENOMEM;
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return r;
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}
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robj->mm_node = drm_mm_get_block_atomic(vm_node, num_pages, 0);
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if (unlikely(robj->mm_node == NULL)) {
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goto retry_pre_get1;
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}
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robj->vm_addr = ((uint32_t)robj->mm_node->start) ;
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dbgprintf("alloc gtt: base %x size %x\n",
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robj->vm_addr << PAGE_SHIFT, num_pages << PAGE_SHIFT);
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};
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// r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
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// 0, 0, false, NULL, size,
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// &radeon_ttm_object_object_destroy);
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if (unlikely(r != 0)) {
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/* ttm call radeon_ttm_object_object_destroy if error happen */
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DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
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size, flags, 0);
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return r;
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}
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*robj_ptr = robj;
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// if (gobj) {
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// list_add_tail(&robj->list, &rdev->gem.objects);
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// }
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return 0;
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}
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#define page_tabs 0xFDC00000
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int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
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uint64_t *gpu_addr)
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{
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uint32_t flags;
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uint32_t tmp;
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int r = 0;
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dbgprintf("%s\n",__FUNCTION__);
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// flags = radeon_object_flags_from_domain(domain);
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// spin_lock(&robj->tobj.lock);
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if (robj->pin_count) {
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robj->pin_count++;
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if (gpu_addr != NULL) {
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*gpu_addr = robj->gpu_addr;
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}
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// spin_unlock(&robj->tobj.lock);
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return 0;
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}
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// spin_unlock(&robj->tobj.lock);
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// r = radeon_object_reserve(robj, false);
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// if (unlikely(r != 0)) {
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// DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
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// return r;
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// }
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// tmp = robj->tobj.mem.placement;
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// ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
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// robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
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// r = ttm_buffer_object_validate(&robj->tobj,
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// robj->tobj.proposed_placement,
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// false, false);
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robj->gpu_addr = ((u64)robj->vm_addr) << PAGE_SHIFT;
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if(robj->flags & TTM_PL_FLAG_VRAM)
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robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
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else if (robj->flags & TTM_PL_FLAG_TT)
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{
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u32_t *pagelist;
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robj->kptr = KernelAlloc( robj->mm_node->size << PAGE_SHIFT );
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dbgprintf("kernel alloc %x\n", robj->kptr );
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pagelist = &((u32_t*)page_tabs)[(u32_t)robj->kptr >> 12];
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dbgprintf("pagelist %x\n", pagelist);
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radeon_gart_bind(robj->rdev, robj->gpu_addr,
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robj->mm_node->size, pagelist);
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robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
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}
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else
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{
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DRM_ERROR("Unknown placement %d\n", robj->flags);
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robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
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r = -1;
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};
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// flags & TTM_PL_FLAG_VRAM
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if (gpu_addr != NULL) {
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*gpu_addr = robj->gpu_addr;
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}
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robj->pin_count = 1;
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to pin object.\n");
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}
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dbgprintf("done %s\n",__FUNCTION__);
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return r;
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}
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int radeon_object_kmap(struct radeon_object *robj, void **ptr)
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{
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int r = 0;
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dbgprintf("%s\n",__FUNCTION__);
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// spin_lock(&robj->tobj.lock);
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if (robj->kptr) {
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if (ptr) {
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*ptr = robj->kptr;
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}
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// spin_unlock(&robj->tobj.lock);
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return 0;
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}
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// spin_unlock(&robj->tobj.lock);
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if(robj->flags & TTM_PL_FLAG_VRAM)
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{
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robj->cpu_addr = robj->rdev->mc.aper_base +
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(robj->vm_addr << PAGE_SHIFT);
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robj->kptr = (void*)MapIoMem(robj->cpu_addr,
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robj->mm_node->size << 12, PG_SW);
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dbgprintf("map io mem %x at %x\n", robj->cpu_addr, robj->kptr);
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}
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else
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{
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return -1;
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}
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if (ptr) {
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*ptr = robj->kptr;
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}
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dbgprintf("done %s\n",__FUNCTION__);
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return 0;
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}
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#if 0
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void radeon_object_unpin(struct radeon_object *robj)
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{
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uint32_t flags;
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int r;
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// spin_lock(&robj->tobj.lock);
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if (!robj->pin_count) {
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// spin_unlock(&robj->tobj.lock);
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printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
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return;
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}
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robj->pin_count--;
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if (robj->pin_count) {
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// spin_unlock(&robj->tobj.lock);
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return;
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}
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// spin_unlock(&robj->tobj.lock);
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r = radeon_object_reserve(robj, false);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
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return;
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}
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flags = robj->tobj.mem.placement;
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robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
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r = ttm_buffer_object_validate(&robj->tobj,
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robj->tobj.proposed_placement,
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false, false);
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if (unlikely(r != 0)) {
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DRM_ERROR("radeon: failed to unpin buffer.\n");
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}
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radeon_object_unreserve(robj);
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}
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/*
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* To exclude mutual BO access we rely on bo_reserve exclusion, as all
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* function are calling it.
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*/
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static int radeon_object_reserve(struct radeon_object *robj, bool interruptible)
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{
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return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0);
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}
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static void radeon_object_unreserve(struct radeon_object *robj)
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{
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ttm_bo_unreserve(&robj->tobj);
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}
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static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj)
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{
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struct radeon_object *robj;
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robj = container_of(tobj, struct radeon_object, tobj);
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// list_del_init(&robj->list);
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kfree(robj);
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}
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static inline void radeon_object_gpu_addr(struct radeon_object *robj)
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{
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/* Default gpu address */
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robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
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if (robj->tobj.mem.mm_node == NULL) {
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return;
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}
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robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT;
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switch (robj->tobj.mem.mem_type) {
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case TTM_PL_VRAM:
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robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
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break;
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case TTM_PL_TT:
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robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
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break;
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default:
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DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type);
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robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
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return;
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}
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}
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int radeon_object_create(struct radeon_device *rdev,
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struct drm_gem_object *gobj,
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unsigned long size,
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bool kernel,
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uint32_t domain,
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bool interruptible,
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struct radeon_object **robj_ptr)
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{
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struct radeon_object *robj;
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enum ttm_bo_type type;
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uint32_t flags;
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int r;
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// if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
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// rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
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// }
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else {
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type = ttm_bo_type_device;
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}
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*robj_ptr = NULL;
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robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
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if (robj == NULL) {
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return -ENOMEM;
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}
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robj->rdev = rdev;
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robj->gobj = gobj;
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// INIT_LIST_HEAD(&robj->list);
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flags = radeon_object_flags_from_domain(domain);
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// r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
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// 0, 0, false, NULL, size,
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// &radeon_ttm_object_object_destroy);
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if (unlikely(r != 0)) {
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/* ttm call radeon_ttm_object_object_destroy if error happen */
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DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
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size, flags, 0);
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return r;
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}
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*robj_ptr = robj;
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// if (gobj) {
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// list_add_tail(&robj->list, &rdev->gem.objects);
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// }
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return 0;
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}
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int radeon_object_kmap(struct radeon_object *robj, void **ptr)
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{
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int r;
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// spin_lock(&robj->tobj.lock);
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if (robj->kptr) {
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if (ptr) {
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*ptr = robj->kptr;
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}
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// spin_unlock(&robj->tobj.lock);
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return 0;
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}
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// spin_unlock(&robj->tobj.lock);
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r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap);
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if (r) {
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return r;
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}
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// spin_lock(&robj->tobj.lock);
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robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem);
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// spin_unlock(&robj->tobj.lock);
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if (ptr) {
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*ptr = robj->kptr;
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}
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return 0;
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}
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void radeon_object_kunmap(struct radeon_object *robj)
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{
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// spin_lock(&robj->tobj.lock);
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if (robj->kptr == NULL) {
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// spin_unlock(&robj->tobj.lock);
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return;
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}
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robj->kptr = NULL;
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// spin_unlock(&robj->tobj.lock);
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ttm_bo_kunmap(&robj->kmap);
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}
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void radeon_object_unref(struct radeon_object **robj)
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{
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struct ttm_buffer_object *tobj;
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if ((*robj) == NULL) {
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return;
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}
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tobj = &((*robj)->tobj);
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ttm_bo_unref(&tobj);
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if (tobj == NULL) {
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*robj = NULL;
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}
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}
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int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset)
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{
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*offset = robj->tobj.addr_space_offset;
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return 0;
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}
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int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
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uint64_t *gpu_addr)
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{
|
|
uint32_t flags;
|
|
uint32_t tmp;
|
|
int r;
|
|
|
|
flags = radeon_object_flags_from_domain(domain);
|
|
// spin_lock(&robj->tobj.lock);
|
|
if (robj->pin_count) {
|
|
robj->pin_count++;
|
|
if (gpu_addr != NULL) {
|
|
*gpu_addr = robj->gpu_addr;
|
|
}
|
|
// spin_unlock(&robj->tobj.lock);
|
|
return 0;
|
|
}
|
|
// spin_unlock(&robj->tobj.lock);
|
|
r = radeon_object_reserve(robj, false);
|
|
if (unlikely(r != 0)) {
|
|
DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
|
|
return r;
|
|
}
|
|
tmp = robj->tobj.mem.placement;
|
|
ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
|
|
robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
|
|
r = ttm_buffer_object_validate(&robj->tobj,
|
|
robj->tobj.proposed_placement,
|
|
false, false);
|
|
radeon_object_gpu_addr(robj);
|
|
if (gpu_addr != NULL) {
|
|
*gpu_addr = robj->gpu_addr;
|
|
}
|
|
robj->pin_count = 1;
|
|
if (unlikely(r != 0)) {
|
|
DRM_ERROR("radeon: failed to pin object.\n");
|
|
}
|
|
radeon_object_unreserve(robj);
|
|
return r;
|
|
}
|
|
|
|
void radeon_object_unpin(struct radeon_object *robj)
|
|
{
|
|
uint32_t flags;
|
|
int r;
|
|
|
|
// spin_lock(&robj->tobj.lock);
|
|
if (!robj->pin_count) {
|
|
// spin_unlock(&robj->tobj.lock);
|
|
printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
|
|
return;
|
|
}
|
|
robj->pin_count--;
|
|
if (robj->pin_count) {
|
|
// spin_unlock(&robj->tobj.lock);
|
|
return;
|
|
}
|
|
// spin_unlock(&robj->tobj.lock);
|
|
r = radeon_object_reserve(robj, false);
|
|
if (unlikely(r != 0)) {
|
|
DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
|
|
return;
|
|
}
|
|
flags = robj->tobj.mem.placement;
|
|
robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
|
|
r = ttm_buffer_object_validate(&robj->tobj,
|
|
robj->tobj.proposed_placement,
|
|
false, false);
|
|
if (unlikely(r != 0)) {
|
|
DRM_ERROR("radeon: failed to unpin buffer.\n");
|
|
}
|
|
radeon_object_unreserve(robj);
|
|
}
|
|
|
|
int radeon_object_wait(struct radeon_object *robj)
|
|
{
|
|
int r = 0;
|
|
|
|
/* FIXME: should use block reservation instead */
|
|
r = radeon_object_reserve(robj, true);
|
|
if (unlikely(r != 0)) {
|
|
DRM_ERROR("radeon: failed to reserve object for waiting.\n");
|
|
return r;
|
|
}
|
|
// spin_lock(&robj->tobj.lock);
|
|
if (robj->tobj.sync_obj) {
|
|
r = ttm_bo_wait(&robj->tobj, true, false, false);
|
|
}
|
|
// spin_unlock(&robj->tobj.lock);
|
|
radeon_object_unreserve(robj);
|
|
return r;
|
|
}
|
|
|
|
int radeon_object_evict_vram(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
|
/* Useless to evict on IGP chips */
|
|
return 0;
|
|
}
|
|
return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
|
|
}
|
|
|
|
void radeon_object_force_delete(struct radeon_device *rdev)
|
|
{
|
|
struct radeon_object *robj, *n;
|
|
struct drm_gem_object *gobj;
|
|
|
|
if (list_empty(&rdev->gem.objects)) {
|
|
return;
|
|
}
|
|
DRM_ERROR("Userspace still has active objects !\n");
|
|
list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) {
|
|
mutex_lock(&rdev->ddev->struct_mutex);
|
|
gobj = robj->gobj;
|
|
DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n",
|
|
gobj, robj, (unsigned long)gobj->size,
|
|
*((unsigned long *)&gobj->refcount));
|
|
list_del_init(&robj->list);
|
|
radeon_object_unref(&robj);
|
|
gobj->driver_private = NULL;
|
|
drm_gem_object_unreference(gobj);
|
|
mutex_unlock(&rdev->ddev->struct_mutex);
|
|
}
|
|
}
|
|
|
|
void radeon_object_fini(struct radeon_device *rdev)
|
|
{
|
|
radeon_ttm_fini(rdev);
|
|
}
|
|
|
|
void radeon_object_list_add_object(struct radeon_object_list *lobj,
|
|
struct list_head *head)
|
|
{
|
|
if (lobj->wdomain) {
|
|
list_add(&lobj->list, head);
|
|
} else {
|
|
list_add_tail(&lobj->list, head);
|
|
}
|
|
}
|
|
|
|
int radeon_object_list_reserve(struct list_head *head)
|
|
{
|
|
struct radeon_object_list *lobj;
|
|
struct list_head *i;
|
|
int r;
|
|
|
|
list_for_each(i, head) {
|
|
lobj = list_entry(i, struct radeon_object_list, list);
|
|
if (!lobj->robj->pin_count) {
|
|
r = radeon_object_reserve(lobj->robj, true);
|
|
if (unlikely(r != 0)) {
|
|
DRM_ERROR("radeon: failed to reserve object.\n");
|
|
return r;
|
|
}
|
|
} else {
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void radeon_object_list_unreserve(struct list_head *head)
|
|
{
|
|
struct radeon_object_list *lobj;
|
|
struct list_head *i;
|
|
|
|
list_for_each(i, head) {
|
|
lobj = list_entry(i, struct radeon_object_list, list);
|
|
if (!lobj->robj->pin_count) {
|
|
radeon_object_unreserve(lobj->robj);
|
|
} else {
|
|
}
|
|
}
|
|
}
|
|
|
|
int radeon_object_list_validate(struct list_head *head, void *fence)
|
|
{
|
|
struct radeon_object_list *lobj;
|
|
struct radeon_object *robj;
|
|
struct radeon_fence *old_fence = NULL;
|
|
struct list_head *i;
|
|
uint32_t flags;
|
|
int r;
|
|
|
|
r = radeon_object_list_reserve(head);
|
|
if (unlikely(r != 0)) {
|
|
radeon_object_list_unreserve(head);
|
|
return r;
|
|
}
|
|
list_for_each(i, head) {
|
|
lobj = list_entry(i, struct radeon_object_list, list);
|
|
robj = lobj->robj;
|
|
if (lobj->wdomain) {
|
|
flags = radeon_object_flags_from_domain(lobj->wdomain);
|
|
flags |= TTM_PL_FLAG_TT;
|
|
} else {
|
|
flags = radeon_object_flags_from_domain(lobj->rdomain);
|
|
flags |= TTM_PL_FLAG_TT;
|
|
flags |= TTM_PL_FLAG_VRAM;
|
|
}
|
|
if (!robj->pin_count) {
|
|
robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING;
|
|
r = ttm_buffer_object_validate(&robj->tobj,
|
|
robj->tobj.proposed_placement,
|
|
true, false);
|
|
if (unlikely(r)) {
|
|
radeon_object_list_unreserve(head);
|
|
DRM_ERROR("radeon: failed to validate.\n");
|
|
return r;
|
|
}
|
|
radeon_object_gpu_addr(robj);
|
|
}
|
|
lobj->gpu_offset = robj->gpu_addr;
|
|
if (fence) {
|
|
old_fence = (struct radeon_fence *)robj->tobj.sync_obj;
|
|
robj->tobj.sync_obj = radeon_fence_ref(fence);
|
|
robj->tobj.sync_obj_arg = NULL;
|
|
}
|
|
if (old_fence) {
|
|
radeon_fence_unref(&old_fence);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void radeon_object_list_unvalidate(struct list_head *head)
|
|
{
|
|
struct radeon_object_list *lobj;
|
|
struct radeon_fence *old_fence = NULL;
|
|
struct list_head *i;
|
|
|
|
list_for_each(i, head) {
|
|
lobj = list_entry(i, struct radeon_object_list, list);
|
|
old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
|
|
lobj->robj->tobj.sync_obj = NULL;
|
|
if (old_fence) {
|
|
radeon_fence_unref(&old_fence);
|
|
}
|
|
}
|
|
radeon_object_list_unreserve(head);
|
|
}
|
|
|
|
void radeon_object_list_clean(struct list_head *head)
|
|
{
|
|
radeon_object_list_unreserve(head);
|
|
}
|
|
|
|
int radeon_object_fbdev_mmap(struct radeon_object *robj,
|
|
struct vm_area_struct *vma)
|
|
{
|
|
return ttm_fbdev_mmap(vma, &robj->tobj);
|
|
}
|
|
|
|
#endif
|
|
|
|
unsigned long radeon_object_size(struct radeon_object *robj)
|
|
{
|
|
return robj->tobj.num_pages << PAGE_SHIFT;
|
|
}
|
|
|
|
|