forked from KolibriOS/kolibrios
591 lines
11 KiB
PHP
591 lines
11 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2007-2008. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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IRQ_RESERVE = 24 ; 16 or 24
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iglobal
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IRQ_COUNT dd 24
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endg
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uglobal
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APIC: dd 0
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LAPIC_BASE: dd 0
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IOAPIC_base: dd 0
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endg
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APIC_ID equ 0x20
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APIC_TPR equ 0x80
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APIC_EOI equ 0xb0
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APIC_LDR equ 0xd0
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APIC_DFR equ 0xe0
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APIC_SVR equ 0xf0
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APIC_ISR equ 0x100
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APIC_ESR equ 0x280
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APIC_ICRL equ 0x300
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APIC_ICRH equ 0x310
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APIC_LVT_LINT0 equ 0x350
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APIC_LVT_LINT1 equ 0x360
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APIC_LVT_err equ 0x370
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; APIC timer
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APIC_LVT_timer equ 0x320
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APIC_timer_div equ 0x3e0
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APIC_timer_init equ 0x380
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APIC_timer_cur equ 0x390
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; IOAPIC
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IOAPIC_ID equ 0x0
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IOAPIC_VER equ 0x1
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IOAPIC_ARB equ 0x2
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IOAPIC_REDTBL equ 0x10
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APIC_init:
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mov dword[APIC], 0
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; jmp .no_apic ; NO APIC
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; bt [cpu_caps], CAPS_APIC
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; jnc .no_apic
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; Check for MP table
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;.....
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call IRQ_mask_all
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; IOAPIC init
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; 0xfec00000 - may be relocated, see chip reference... & MP table
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stdcall map_io_mem, 0xfec00000, 0x20, PG_SW
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mov [IOAPIC_base], eax
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mov eax, IOAPIC_VER
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call IOAPIC_read
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shr eax, 16
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inc al
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movzx eax, al
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cmp al, IRQ_RESERVE
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jbe @f
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mov al, IRQ_RESERVE
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@@: mov [IRQ_COUNT], eax
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; Reroute IOAPIC & mask all interrupts
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xor ecx, ecx
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mov eax, IOAPIC_REDTBL
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@@: mov ebx, eax
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call IOAPIC_read
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mov ah, 0x09 ; Delivery Mode: Lowest Priority, Destination Mode: Logical
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mov al, cl
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add al, 0x20 ; vector
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or eax, 0x10000 ; Mask Interrupt
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cmp ecx, 16
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jb .set
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or eax, 0xa000 ;<<< level-triggered active-low for IRQ16+
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.set:
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xchg eax, ebx
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call IOAPIC_write
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inc eax
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mov ebx, eax
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call IOAPIC_read
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or eax, 0xff000000 ; Destination Field
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xchg eax, ebx
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call IOAPIC_write
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inc eax
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inc ecx
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cmp ecx, [IRQ_COUNT]
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jb @b
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call LAPIC_init
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mov dword[APIC], 0xffffffff
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mov al, 0x70
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out 0x22, al
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mov al, 1
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out 0x23, al
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; mov dword[irq_type_to_set], IRQ_TYPE_APIC
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;init handlers table
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mov ecx, IRQ_RESERVE
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mov edi, irqh_tab
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@@:
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mov eax, edi
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stosd
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stosd
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loop @B
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mov ecx, 48
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mov eax, irqh_array+IRQH.sizeof
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mov [next_irqh], irqh_array
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@@:
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mov [eax-IRQH.sizeof], eax
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add eax, IRQH.sizeof
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loop @B
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mov [eax-IRQH.sizeof], dword 0
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.no_apic:
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ret
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;===========================================================
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align 4
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LAPIC_init:
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; Check MSR support
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;....
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; Get LAPIC base address
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mov ecx, 0x1b
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rdmsr ; it may be replaced to
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and ax, 0xf000 ; mov eax, 0xfee00000
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stdcall map_io_mem, eax, 0x1000, PG_SW
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mov [LAPIC_BASE], eax
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mov esi, eax
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; Program Destination Format Register for Flat mode.
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mov eax, [esi + APIC_DFR]
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or eax, 0xf0000000
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mov [esi + APIC_DFR], eax
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; Program Logical Destination Register.
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mov eax, [esi + APIC_LDR]
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;and eax, 0xff000000
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and eax, 0x00ffffff
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or eax, 0x01000000 ;!!!!!!!!!!!!
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mov [esi + APIC_LDR], eax
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; Task Priority Register initialization.
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mov eax, [esi + APIC_TPR]
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and eax, 0xffffff00
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mov [esi + APIC_TPR], eax
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; Flush the queue
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mov edx, 0
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.nxt2: mov ecx, 32
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mov eax, [esi + APIC_ISR + edx]
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.nxt: shr eax, 1
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jnc @f
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mov dword [esi + APIC_EOI], 0 ; EOI
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@@: loop .nxt
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add edx, 0x10
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cmp edx, 0x170
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jbe .nxt2
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; Spurious-Interrupt Vector Register initialization.
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mov eax, [esi + APIC_SVR]
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or eax, 0x1ff
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and eax, 0xfffffdff
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mov [esi + APIC_SVR], eax
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; Initialize LVT LINT0 register. (INTR)
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mov eax, 0x00700
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; mov eax, 0x10700
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mov [esi + APIC_LVT_LINT0], eax
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; Initialize LVT LINT1 register. (NMI)
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mov eax, 0x00400
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mov [esi + APIC_LVT_LINT1], eax
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; Initialize LVT Error register.
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mov eax, [esi + APIC_LVT_err]
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or eax, 0x10000 ; bit 16
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mov [esi + APIC_LVT_err], eax
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; LAPIC timer
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; pre init
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mov dword[esi + APIC_timer_div], 1011b ; 1
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mov dword[esi + APIC_timer_init], 0xffffffff ; max val
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push esi
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mov esi, 640 ; wait 0.64 sec
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call delay_ms
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pop esi
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mov eax, [esi + APIC_timer_cur] ; read current tick couner
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xor eax, 0xffffffff ; eax = 0xffffffff - eax
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shr eax, 6 ; eax /= 64; APIC ticks per 0.01 sec
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; Start (every 0.01 sec)
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mov dword[esi + APIC_LVT_timer], 0x30020 ; periodic int 0x20
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mov dword[esi + APIC_timer_init], eax
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ret
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;===========================================================
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; IOAPIC implementation
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align 4
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IOAPIC_read:
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; in : EAX - IOAPIC register
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; out: EAX - readed value
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push esi
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mov esi, [IOAPIC_base]
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mov [esi], eax
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mov eax, [esi + 0x10]
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pop esi
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ret
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align 4
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IOAPIC_write:
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; in : EAX - IOAPIC register
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; EBX - value
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; out: none
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push esi
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mov esi, [IOAPIC_base]
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mov [esi], eax
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mov [esi + 0x10], ebx
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pop esi
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ret
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;===========================================================
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; Remap all IRQ to 0x20+ Vectors
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; IRQ0 to vector 0x20, IRQ1 to vector 0x21....
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PIC_init:
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cli
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mov al,0x11 ; icw4, edge triggered
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out 0x20,al
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call pic_delay
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out 0xA0,al
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call pic_delay
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mov al,0x20 ; generate 0x20 +
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out 0x21,al
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call pic_delay
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mov al,0x28 ; generate 0x28 +
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out 0xA1,al
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call pic_delay
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mov al,0x04 ; slave at irq2
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out 0x21,al
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call pic_delay
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mov al,0x02 ; at irq9
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out 0xA1,al
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call pic_delay
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mov al,0x01 ; 8086 mode
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out 0x21,al
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call pic_delay
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out 0xA1,al
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call pic_delay
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call IRQ_mask_all
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cli
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; mov dword[irq_type_to_set], IRQ_TYPE_PIC
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ret
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; -----------------------------------------
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pic_delay:
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jmp pdl1
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pdl1: ret
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; -----------------------------------------
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; TIMER SET TO 1/100 S
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PIT_init:
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mov al,0x34 ; set to 100Hz
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out 0x43,al
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mov al,0x9b ; lsb 1193180 / 1193
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out 0x40,al
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mov al,0x2e ; msb
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out 0x40,al
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ret
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; -----------------------------------------
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unmask_timer:
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test dword[APIC], 0xffffffff
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jnz @f
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stdcall enable_irq, 0
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ret
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@@:
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; use PIT
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; in some systems PIT no connected to IOAPIC
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; mov eax, 0x14
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; call IOAPIC_read
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; mov ah, 0x09 ; Delivery Mode: Lowest Priority, Destination Mode: Logical
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; mov al, 0x20
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; or eax, 0x10000 ; Mask Interrupt
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; mov ebx, eax
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; mov eax, 0x14
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; call IOAPIC_write
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; stdcall enable_irq, 2
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; ret
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; use LAPIC timer
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mov esi, [LAPIC_BASE]
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mov eax, [esi + APIC_LVT_timer]
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and eax, 0xfffeffff
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mov [esi + APIC_LVT_timer], eax
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ret
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; -----------------------------------------
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; Disable all IRQ
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IRQ_mask_all:
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test dword[APIC], 0xffffffff
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jnz .APIC
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mov al, 0xFF
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out 0x21, al
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out 0xA1, al
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mov ecx,0x1000
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cld
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@@: call pic_delay
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loop @b
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ret
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.APIC:
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mov ecx, [IRQ_COUNT]
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mov eax, 0x10
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@@: mov ebx, eax
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call IOAPIC_read
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or eax, 0x10000 ; bit 16
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xchg eax, ebx
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call IOAPIC_write
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inc eax
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inc eax
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loop @b
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ret
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; -----------------------------------------
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; End Of Interrupt
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; al - IRQ number
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align 16
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IRQ_EOI:
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test dword[APIC], 0xffffffff
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jnz .APIC
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cmp al, 8
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mov al, 0x20
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jb @f
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out 0xa0, al
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@@: out 0x20, al
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ret
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.APIC:
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mov eax, [LAPIC_BASE]
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mov dword [eax + APIC_EOI], 0 ; EOI
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ret
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; -----------------------------------------
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; from dll.inc
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align 4
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proc enable_irq stdcall, irq_line:dword
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mov ebx, [irq_line]
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test dword[APIC], 0xffffffff
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jnz .APIC
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mov edx, 0x21
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cmp ebx, 8
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jb @F
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mov edx, 0xA1
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sub ebx,8
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@@:
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in al,dx
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btr eax, ebx
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out dx, al
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ret
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.APIC:
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shl ebx, 1
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add ebx, 0x10
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mov eax, ebx
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call IOAPIC_read
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and eax, 0xfffeffff ; bit 16
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xchg eax, ebx
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call IOAPIC_write
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ret
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endp
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; IRQ_TYPE_DISABLE equ 0
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; IRQ_TYPE_PIC equ 1
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; IRQ_TYPE_APIC equ 2
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; uglobal
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; irq_type_to_set rd 1
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; irq_types rd IRQ_RESERVE
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; endg
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; -----------------------------------------
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; End Of Interrupt
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; al - IRQ number
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; align 16
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; IRQ_EOI:
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; movzx eax, al
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; cmp dword[irq_types + eax * 4], IRQ_TYPE_APIC
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; jne @f
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; mov eax, [LAPIC_BASE]
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; mov dword [eax + APIC_EOI], 0 ; EOI
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; ret
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; @@:
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; cmp al, 8
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; mov al, 0x20
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; jb @f
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; out 0xa0, al
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; @@: out 0x20, al
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; ret
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; align 4
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; proc enable_irq stdcall, irq_line:dword
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; cmp dword[irq_type_to_set], IRQ_TYPE_APIC
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; jne @f
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; stdcall APIC_enable_irq, [irq_line]
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; ret
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; @@: stdcall PIC_enable_irq, [irq_line]
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; ret
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; endp
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; align 4
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; proc disable_irq stdcall, irq_line:dword
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; push eax
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; mov eax, [irq_line]
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; cmp dword[irq_types + eax * 4], IRQ_TYPE_APIC
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; jne @f
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; stdcall APIC_disable_irq, eax
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; pop eax
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; ret
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; @@: stdcall PIC_disable_irq, eax
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; pop eax
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; ret
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; endp
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; align 4
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; proc PIC_enable_irq stdcall, irq_line:dword
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; pusha
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; mov ebx, [irq_line]
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; mov eax, [irq_types + ebx * 4]
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; cmp eax, IRQ_TYPE_DISABLE
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; je @f
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; cmp eax, IRQ_TYPE_PIC
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; je @f
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; stdcall disable_irq, ebx
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; @@: mov dword[irq_types + ebx * 4], IRQ_TYPE_PIC
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; mov edx, 0x21
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; cmp ebx, 8
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; jb @F
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; mov edx, 0xA1
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; sub ebx,8
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; @@: in al,dx
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; btr eax, ebx
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; out dx, al
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; popa
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; ret
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; endp
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; align 4
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; proc PIC_disable_irq stdcall, irq_line:dword
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; pusha
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; mov ebx, [irq_line]
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; mov dword[irq_types + ebx * 4], IRQ_TYPE_DISABLE
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; mov edx, 0x21
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; cmp ebx, 8
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; jb @F
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; mov edx, 0xA1
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; sub ebx,8
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; @@: in al,dx
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; bts eax, ebx
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; out dx, al
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; popa
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; ret
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; endp
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; align 4
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; proc APIC_enable_irq stdcall, irq_line:dword
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; pusha
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; mov ebx, [irq_line]
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; mov eax, [irq_types + ebx * 4]
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; cmp eax, IRQ_TYPE_DISABLE
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; je @f
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; cmp eax, IRQ_TYPE_APIC
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; je @f
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; stdcall disable_irq, ebx
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; @@: mov dword[irq_types + ebx * 4], IRQ_TYPE_APIC
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; shl ebx, 1
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; add ebx, 0x10
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; mov eax, ebx
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; call IOAPIC_read
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; and eax, 0xfffeffff ; bit 16
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; xchg eax, ebx
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; call IOAPIC_write
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; popa
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; ret
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; endp
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; align 4
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; proc APIC_disable_irq stdcall, irq_line:dword
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; pusha
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; mov ebx, [irq_line]
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; mov dword[irq_types + ebx * 4], IRQ_TYPE_DISABLE
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; shl ebx, 1
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; add ebx, 0x10
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; mov eax, ebx
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; call IOAPIC_read
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; or eax, 0x10000
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; xchg eax, ebx
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; call IOAPIC_write
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; popa
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; ret
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; endp
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macro __list_add new, prev, next
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{
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mov [next+LHEAD.prev], new
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mov [new+LHEAD.next], next
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mov [new+LHEAD.prev], prev
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mov [prev+LHEAD.next], new
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}
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macro list_add new, head
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{
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mov eax, [head+LHEAD.next]
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__list_add new, head, eax
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}
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macro list_add_tail new, head
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{
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mov eax, [head+LHEAD.prev]
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__list_add new, eax, head
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}
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align 4
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proc attach_int_handler_ex stdcall, irq:dword, handler:dword, user_data:dword
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locals
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.irqh dd ?
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endl
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and [.irqh], 0
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push ebx
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mov ebx, [irq] ;irq num
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test ebx, ebx
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jz .err
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cmp ebx, IRQ_RESERVE
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jae .err
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mov edx, [handler]
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test edx, edx
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jz .err
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pushfd
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cli
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;allocate handler
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mov ecx, [next_irqh]
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test ecx, ecx
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jz .fail
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|
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mov eax, [ecx]
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mov [next_irqh], eax
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|
|
|
mov [.irqh], ecx
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|
|
|
mov eax, [user_data]
|
|
mov [ecx+IRQH.handler], edx
|
|
mov [ecx+IRQH.data], eax
|
|
|
|
lea edx, [irqh_tab+ebx*8]
|
|
list_add_tail ecx, edx ;clobber eax
|
|
|
|
stdcall enable_irq, [irq]
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|
|
|
.fail:
|
|
popfd
|
|
.err:
|
|
pop ebx
|
|
mov eax, [.irqh]
|
|
ret
|
|
|
|
endp
|