forked from KolibriOS/kolibrios
251 lines
4.0 KiB
PHP
251 lines
4.0 KiB
PHP
; PCI Bus defines
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PCI_HEADER_TYPE equ 0x0e ;8 bit
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PCI_BASE_ADDRESS_0 equ 0x10 ;32 bit
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PCI_BASE_ADDRESS_5 equ 0x24 ;32 bits
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PCI_BASE_ADDRESS_SPACE_IO equ 0x01
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PCI_VENDOR_ID equ 0x00 ;16 bit
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PCI_BASE_ADDRESS_IO_MASK equ 0xFFFFFFFC
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; PCI programming
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PCI_REG_COMMAND equ 0x4 ; command register
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PCI_REG_STATUS equ 0x6 ; status register
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PCI_REG_LATENCY equ 0xd ; latency timer register
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PCI_REG_CAP_PTR equ 0x34 ; capabilities pointer
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PCI_REG_CAPABILITY_ID equ 0x0 ; capapility ID in pm register block
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PCI_REG_PM_STATUS equ 0x4 ; power management status register
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PCI_REG_PM_CTRL equ 0x4 ; power management control register
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PCI_BIT_PIO equ 1 ; bit0: io space control
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PCI_BIT_MMIO equ 2 ; bit1: memory space control
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PCI_BIT_MASTER equ 4 ; bit2: device acts as a PCI master
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PAGESIZE equ 4096
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; network driver types
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NET_TYPE_ETH equ 1
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NET_TYPE_SLIP equ 2
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LAST_IO = 0
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macro set_io addr {
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if addr = 0
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mov edx, [device.io_addr]
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else if addr = LAST_IO
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else
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add edx, addr - LAST_IO
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end if
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LAST_IO = addr
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}
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macro allocate_and_clear dest, size, err {
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; We need to allocate at least 8 pages, if we want a continuous memory in ram
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push edx
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if (size < 8*4096) & (size > 4096)
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stdcall KernelAlloc, 8*4096
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else
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stdcall KernelAlloc, size
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end if
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pop edx
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test eax, eax
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jz err
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mov dest, eax ; Save the address to it into the device struct
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mov edi, eax ; look at last part of code!
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; Release the unused pages (if any)
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if (size < 8*4096) & (size > 4096)
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add eax, (size/4096+1)*4096
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mov ecx, 8-(size/4096+1)
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push edx
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call ReleasePages
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pop edx
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end if
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; Clear the allocated buffer
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mov ecx, size/4 ; divide by 4 because of DWORD
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xor eax, eax
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rep stosd
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}
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macro find_io bus, dev, io {
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local .check, .inc, .got
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xor eax, eax
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mov esi, PCI_BASE_ADDRESS_0
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movzx ecx, bus
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movzx edx, dev
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.check:
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stdcall PciRead32, ecx ,edx ,esi
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test eax, PCI_BASE_ADDRESS_IO_MASK
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jz .inc
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test eax, PCI_BASE_ADDRESS_SPACE_IO
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jz .inc
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and eax, PCI_BASE_ADDRESS_IO_MASK
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mov io , eax
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jmp .got
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.inc:
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add esi, 4
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cmp esi, PCI_BASE_ADDRESS_5
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jle .check
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.got:
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}
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macro find_irq bus, dev, irq {
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push eax edx ecx
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found
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mov irq, al
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pop ecx edx eax
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}
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macro find_rev bus, dev, rev {
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push eax edx ecx
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead8, ecx ,edx ,0x8
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mov rev, al
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pop ecx edx eax
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}
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macro make_bus_master bus, dev {
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND
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or al, PCI_BIT_MASTER ;or PCI_BIT_PIO
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; and al, not PCI_BIT_MMIO
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stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
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;; TODO: try to switch to PIO, and check if PIO works or not..
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}
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struc IOCTL {
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.handle dd ?
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.io_code dd ?
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.input dd ?
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.inp_size dd ?
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.output dd ?
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.out_size dd ?
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}
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virtual at edx
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IOCTL IOCTL
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end virtual
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if used null_op
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align 4
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null_op:
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or eax, -1
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ret
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end if
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macro virt_to_dma { ; input is eax
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push ax
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and word[esp], PAGESIZE - 1
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call GetPgAddr
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or ax, word[esp]
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inc esp
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inc esp
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}
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macro NET_DEVICE {
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.type dd ? ; Type field
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.mtu dd ? ; Maximal Transmission Unit
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.name dd ? ; Ptr to 0 terminated string
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.unload dd ? ; Ptrs to driver functions
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.reset dd ? ;
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.transmit dd ? ;
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.bytes_tx dq ? ; Statistics, updated by the driver
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.bytes_rx dq ? ;
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.packets_tx dd ? ;
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.packets_rx dd ? ;
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.end:
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}
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;struc ETH_DEVICE {
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macro ETH_DEVICE {
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NET_DEVICE
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.set_mode dd ?
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.get_mode dd ?
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.set_MAC dd ?
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.get_MAC dd ?
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.mode dd ?
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.mac dp ?
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dp ? ; qword alignment
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}
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macro SLIP_DEVICE {
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NET_DEVICE
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.set_mode dd ?
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.get_mode dd ?
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.mode dd ?
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}
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macro GetRealAddr {
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push eax
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call GetPgAddr
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and dword [esp], (PAGESIZE - 1)
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or eax, dword [esp]
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add esp, 4
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}
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