forked from KolibriOS/kolibrios
398 lines
10 KiB
PHP
398 lines
10 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) 2010-17 KolibriOS team. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; HT.inc ;; ;;
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;; ;;
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;; AMD HyperTransport bus control ;;
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;; ;;
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;; art_zh <kolibri@jerdev.co.uk> ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision: 1554 $
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NB_MISC_INDEX equ 0xF0000060 ; NB Misc indirect access
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NB_MISC_DATA equ 0xF0000064
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PCIEIND_INDEX equ 0xF00000E0 ; PCIe Core indirect config space access
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HTIU_NB_INDEX equ 0xF0000094 ; HyperTransport indirect config space access
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;=============================================================================
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;
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; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
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;
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;=============================================================================
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org $-OS_BASE ; physical addresses needed at initial stage
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align 4
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;------------------------------------------
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; params: al = nbconfig register#
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; returns: eax = register content
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;
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rs7xx_nbconfig_read_pci:
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and eax, 0x0FC ; leave register# only
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or eax, 0x80000000 ; bdf = 0:0.0
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mov dx, 0x0CF8 ; write to index reg
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out dx, eax
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add dl, 4
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in eax, dx
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ret
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align 4
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rs7xx_nbconfig_flush_pci:
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mov eax, 0x0B0 ; a scratch reg
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mov dx, 0xCF8
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out dx, eax
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ret
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align 4
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;------------------------------------------
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; params: al = nbconfig register#
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; ebx = register content
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;
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rs7xx_nbconfig_write_pci:
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and eax, 0x0FC ; leave register# only
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or eax, 0x80000000 ; bdf = 0:0.0
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mov dx, 0x0CF8 ; write to index reg
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out dx, eax
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add dl, 4
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mov eax, ebx
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out dx, eax
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ret
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;***************************************************************************
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; Function
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; rs7xx_unlock_bar3: unlocks the BAR3 register of nbconfig that
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; makes pcie config address space visible
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; -----------------------
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; in: nothing out: nothing destroys: eax ebx edx
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;
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;***************************************************************************
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align 4
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rs7xx_unlock_bar3:
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mov eax, NB_MISC_INDEX
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mov ebx, 0x080 ; NBMISCIND:0x0; write-enable
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call rs7xx_nbconfig_write_pci ; set index
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mov eax, NB_MISC_DATA
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call rs7xx_nbconfig_read_pci ; read data
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mov ebx, eax
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and ebx, 0xFFFFFFF7 ; clear bit3
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mov eax, NB_MISC_DATA
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call rs7xx_nbconfig_write_pci ; write it back
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mov eax, NB_MISC_INDEX
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xor ebx, ebx ; reg#0; write-locked
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call rs7xx_nbconfig_write_pci ; set index
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ret
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;***************************************************************************
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; Function
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; fusion_pcie_init:
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;
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; Description
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; PCIe extended config space detection and mapping
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;
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;***************************************************************************
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align 4
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; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
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align 4
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fusion_pcie_init:
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mov ecx, 0xC0010058
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rdmsr
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or edx, edx
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jnz $ ; PCIe is in the upper memory. Stop.
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xchg dl, al
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mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address
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mov ecx, edx
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shr cl, 2
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mov word[PCIe_bus_range-OS_BASE], cx
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sub cl, 2
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jae @f
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xor cl, cl
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@@:
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shl edx, cl ; edx = number of 4M pages to map
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mov word[mmio_pcie_cfg_pdes-OS_BASE], dx
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shl edx, 22
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dec edx
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add edx, eax ; the upper configspace limit
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mov dword[mmio_pcie_cfg_lim-OS_BASE], edx
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; ---- large pages mapping ----
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; (eax = phys. address of PCIe conf.space)
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;
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.map_pcie_pages:
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or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!
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mov ecx, PCIe_CONFIG_SPACE ; linear address
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mov ebx, ecx
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shr ebx, 20
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add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
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mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space
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cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
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jb @f
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mov dl, 0x33
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mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl
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@@:
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xor dx, dx ; PDEs counter
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.write_pde:
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mov dword[ebx], eax ; map 4 buses
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add bx, 4 ; new PDE
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add eax, 0x400000 ; +4M phys.
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add ecx, 0x400000 ; +4M lin.
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cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
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jae .pcie_cfg_mapped
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inc dl
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jmp .write_pde
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.pcie_cfg_mapped:
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create_mmio_pte:
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mov ecx, mmio_pte ; physical address
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or ecx, (PG_NOCACHE + PG_SHARED + PG_UW)
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mov ebx, FUSION_MMIO ; linear address
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shr ebx, 20
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add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
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mov dword[ebx], ecx ; Fusion MMIO tables
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; ---- map APIC regs ----
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.map_apic_mmio:
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mov ecx, 0x01B ; APIC BAR
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rdmsr
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and eax, 0xFFFFF000 ; physical address
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or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
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mov ebx, mmio_pte
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mov [ebx], eax
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; ---- map GPU MMRegs ----
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.map_gpu_mmr:
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mov eax, [mmio_pcie_cfg_addr-OS_BASE] ; PCIe space
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; add eax, 0x08018 ; b:0, d:1, f:0, reg=18 << fam.14h GPU BAR
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add eax, 0x08024 ; b:0, d:1, f:0, reg=24 << fam.16h GPU BAR
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mov eax, [eax]
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xor al, al ; physical address
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or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
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@@:
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add bl, 4
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mov [ebx], eax
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add eax, 0x01000
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cmp bl, 16*4 ; map 15 pages
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jb @b
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ret ; <<< OK >>>
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; ================================================================================
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org OS_BASE+$ ; back to the linear address space
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;--------------------------------------------------------------
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align 4
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rs780_read_misc:
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; in: eax(al) - reg# out: eax = NBMISCIND data
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push edx
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mov edx, NB_MISC_INDEX
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and eax, 0x07F
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mov [edx], eax
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add dl, 4
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mov eax, [edx]
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pop edx
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ret
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;-------------------------------------------
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align 4
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rs780_write_misc:
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; in: eax(al) - reg# ebx = NBMISCIND data
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push edx
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mov edx, NB_MISC_INDEX
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and eax, 0x07F
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or eax, 0x080 ; set WE
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mov [edx], eax
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add dl, 4
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mov [edx], ebx
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sub dl, 4
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xor eax, eax
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mov [edx], eax ; safety last
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pop edx
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ret
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;-------------------------------------------------------------
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align 4
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rs780_read_pcieind:
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; in: ah = bridge#, al = reg# out: eax = PCIEIND data
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push edx
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xor edx, edx
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mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB
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and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge
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shl edx, 15 ; device#
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add edx, PCIEIND_INDEX ; full bdf-address
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and eax, 0x30FF
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or al, al
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jnz @f
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shl eax, 4 ; set bits 17..16 for a Core bridge
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@@:
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mov [edx], eax
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add dl, 4
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mov eax, [edx]
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pop edx
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ret
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;-------------------------------------------
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align 4
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rs780_write_pcieind:
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; in: ah = bridge#, al = reg#, ebx = PCIEIND data
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push edx
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xor edx, edx
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mov ah, dl ; bridge# : 0 = Core+GFX; 0x10 = Core+SB
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and dl, 15 ; 0x20 = Core+GPP; 2..12 = a PortBridge
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shl edx, 15 ; device#
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add edx, PCIEIND_INDEX ; full bdf-address
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and eax, 0x30FF
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or al, al
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jnz @f
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shl eax, 4 ; set bits 17..16 for a Core bridge
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@@:
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mov [edx], eax
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add dl, 4
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mov [edx], ebx
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sub dl, 4
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xor eax, eax
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mov [edx], eax ; safety last
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pop edx
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ret
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;------------------------------------------------
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align 4
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rs780_read_htiu:
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; in: al = reg# | out: eax = HTIU data
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;------------------------------------------------
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push edx
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mov edx, HTIU_NB_INDEX
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and eax, 0x07F
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mov [edx], eax
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add dl, 4
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mov eax, [edx]
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pop edx
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ret
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;------------------------------------------------
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align 4
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rs780_write_htiu:
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; in: al = reg#; ebx = data
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;------------------------------------------------
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push edx
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mov edx, HTIU_NB_INDEX
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and eax, 0x07F
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or eax, 0x100
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mov [edx], eax
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add dl, 4
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mov [edx], ebx
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sub dl, 4
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xor eax, eax
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mov [edx], eax
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pop edx
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ret
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;------------------------------------------------
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align 4
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sys_rdmsr:
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; in: [esp+8] = MSR#
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; out: [esp+8] = MSR[63:32]
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; [eax] = MSR[31: 0]
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;------------------------------------------------
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push ecx edx
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mov ecx, [esp+16]
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rdmsr
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mov [esp+16], edx
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pop edx ecx
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ret
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;------------------------------------------------
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uglobal
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align 4
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diff16 "apic_data : ", 0, $
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apic_data:
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.counter dd ?
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.ticks dd ?
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.t_freq dd ?
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.gpu_r6998 dd ?
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endg
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apic_timer_reset:
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mov eax, [pll_frequency.osc]
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shr eax, 1 ; default prescaler - fix it !!
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mov [apic_data.t_freq], eax
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shr eax, 4 ; 16 per second
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mov [apic_data.ticks], eax
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mov ebx, LAPIC_BAR+ 0x320
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mov edx, [ebx]
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and edx, 0xFFFEFF00
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or edx, 0x0002003F ; int vector + restart
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;-- mov [ebx], edx
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mov dword [LAPIC_BAR + 0x380], eax ; load APICTIC
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; ret
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init_hw_cursor:
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call alloc_page ; eax = phys. addr
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push eax
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or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
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mov [mmio_pte + OS_BASE + 15*4], eax ; mapped to the end of GPU MMRegs
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mov edi, GPU_CURSOR ; lin. addr
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invlpg [edi]
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xor ecx, ecx
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.fill64pix:
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xor ebx, ebx
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mov eax, 0x80000000 ; black, non-transparent
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.check_pix:
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cmp ebx, ecx
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jbe @f
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xor eax, eax ; transparent
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@@:
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mov [edi + ebx*4], eax
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inc ebx
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cmp bl, 64
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jb .check_pix
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inc ecx
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cmp ecx, 16
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je @f
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; add edi, 64*4 ; evergreen cursor is 64x64pix
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add edi, 128*4 ; si cursor is 128x128pix
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jmp .fill64pix
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@@:
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pop eax
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mov dword[GPU_MMR + 0x0699C], eax ; cur_surface_addr
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mov dword[GPU_MMR + 0x069A0], 0x000F000F ; cur_size = 16x16
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mov dword[GPU_MMR + 0x069A4], 0 ; cur_adr_hi
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mov dword[GPU_MMR + 0x069A8], 0x02000100 ; cur_pos = 512,256
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mov dword[GPU_MMR + 0x069AC], 0 ; cur_hotspot = 0,0
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mov dword[GPU_MMR + 0x06998], 0x00000301 ; set it!
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ret
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apic_timer_int:
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push eax
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inc dword [apic_data.counter]
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; mov eax, [apic_data.ticks]
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; mov dword [LAPIC_BAR + 0x380], eax ; reload APICTIC
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mov dword [LAPIC_BAR + 0x0B0], 0 ; end of interrupt
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; mov dword [LAPIC_BAR + 0x420], 0x3F ; end of interrupt
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pop eax
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iretd
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