forked from KolibriOS/kolibrios
Rustem Gimadutdinov (rgimad)
774aee343f
- added more structures - added function ahci_find_cmdslot - small fixes git-svn-id: svn://kolibrios.org@9069 a494cfbc-eb01-0410-851d-a64ba20cac60
652 lines
24 KiB
PHP
652 lines
24 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision$
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PCI_REG_STATUS_COMMAND = 0x0004
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PCI_REG_BAR5 = 0x0024
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; bit_ prefix means that its index of bit
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; format: bit_AHCI_STR_REG_BIT
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bit_AHCI_HBA_CAP2_BOH = 0 ; Supports BIOS/OS Handoff
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bit_AHCI_HBA_BOHC_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller)
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bit_AHCI_HBA_BOHC_OOS = 1 ; OS-Owned Semaphore (OS owns controller)
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bit_AHCI_HBA_BOHC_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up
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bit_AHCI_HBA_GHC_AHCI_ENABLE = 31 ; Enable AHCI mode
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bit_AHCI_HBA_GHC_RESET = 0 ; Reset HBA
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bit_AHCI_HBA_GHC_INTERRUPT_ENABLE = 1 ; Enable interrupts from the HBA
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bit_AHCI_HBA_PxCMD_ST = 0
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bit_AHCI_HBA_PxCMD_FRE = 4
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bit_AHCI_HBA_PxCMD_FR = 14
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bit_AHCI_HBA_PxCMD_CR = 15
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AHCI_HBA_PxSSTS_DET = 0xF
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AHCI_HBA_PORT_IPM_ACTIVE = 1
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AHCI_HBA_PxSSTS_DET_PRESENT = 3
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AHCI_MAX_PORTS = 32 ;
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;HBA_MEMORY_SIZE = 0x1100
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; Frame Information Structure Types
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FIS_TYPE_REG_H2D = 0x27 ; Register FIS - host to device
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FIS_TYPE_REG_D2H = 0x34 ; Register FIS - device to host
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FIS_TYPE_DMA_ACT = 0x39 ; DMA activate FIS - device to host
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FIS_TYPE_DMA_SETUP = 0x41 ; DMA setup FIS - bidirectional
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FIS_TYPE_DATA = 0x46 ; Data FIS - bidirectional
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FIS_TYPE_BIST = 0x58 ; BIST activate FIS - bidirectional
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FIS_TYPE_PIO_SETUP = 0x5F ; PIO setup FIS - device to host
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FIS_TYPE_DEV_BITS = 0xA1 ; Set device bits FIS - device to host
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struct AHCI_DATA
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abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory
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pcidev dd ? ; pointer to corresponding PCIDEV structure
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ends
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; Generic Host Control registers
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struct HBA_MEM
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cap dd ? ; 0x00, Host capabilities
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ghc dd ? ; 0x04, Global host control
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is dd ? ; 0x08, Interrupt status
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pi dd ? ; 0x0C, Port implemented
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version dd ? ; 0x10, Version
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ccc_ctl dd ? ; 0x14, Command completion coalescing control
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ccc_pts dd ? ; 0x18, Command completion coalescing ports
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em_loc dd ? ; 0x1C, Enclosure management location
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em_ctl dd ? ; 0x20, Enclosure management control
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cap2 dd ? ; 0x24, Host capabilities extended
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bohc dd ? ; 0x28, BIOS/OS handoff control and status
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reserved rb (0xA0-0x2C) ; 0x2C - 0x9F, Reserved
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vendor rb (0x100-0xA0) ; 0xA0 - 0xFF, Vendor specific
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ports rb (sizeof.HBA_PORT*AHCI_MAX_PORTS) ; 0x100 - 0x10FF, Port control registers, max AHCI_MAX_PORTS
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ends
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; Port Control registers
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struct HBA_PORT
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command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned
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command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems
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fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned
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fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems
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interrupt_status dd ? ; 0x10
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interrupt_enable dd ? ; 0x14
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command dd ? ; 0x18, command and status
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reserved0 dd ? ; 0x1C
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task_file_data dd ? ; 0x20
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signature dd ? ; 0x24
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sata_status dd ? ; 0x28, SATA status (SCR0:SStatus)
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sata_control dd ? ; 0x2C, SATA control (SCR2:SControl)
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sata_error dd ? ; 0x30, SATA error (SCR1:SError)
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sata_active dd ? ; 0x34, SATA active (SCR3:SActive)
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command_issue dd ? ; 0x38
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sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification)
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fis_based_switch_control dd ? ; 0x40
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reserved1 rd 11 ; 0x44 - 0x6F
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vendor rd 4 ; 0x70 - 0x7F, vendor specific
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ends
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; Command header structure
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struct HBA_CMD_HDR
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_flags1 db ? ; 0bPWACCCCC, P - Prefetchable, W - Write (1: H2D, 0: D2H)
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; A - ATAPI, C - Command FIS length in DWORDS, 2 ~ 16
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_flags2 db ? ; 0bPPPPRCB(Re), P - Port multiplier port, R - Reserved,
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; C - Clear busy upon R_OK, B - BIST, Re - Reset
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prdtl dw ? ; Physical region descriptor table length in entries
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prdbc dd ? ; Physical region descriptor byte count transferred
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ctba dd ? ; Command table descriptor base address
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ctbau dd ? ; Command table descriptor base address upper 32 bits
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rsv1 rd 4 ; Reserved
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ends
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struct HBA_PRDT_ENTRY
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dba dd ? ; Data base address
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dbau dd ? ; Data base address upper 32 bits
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rsv0 dd ? ; Reserved
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_flags dd ? ; 0bIR..RD..D, I (1 bit) - Interrupt on completion,
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; R (9 bits) - Reserved, D (22 bits) - Byte count, 4M max
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ends
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struct HBA_CMD_TBL
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cfis rb 64 ; 0x00, Command FIS
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acmd rb 16 ; 0x40, ATAPI command, 12 or 16 bytes
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rsv rb 48 ; 0x50, Reserved
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prdt_entry HBA_PRDT_ENTRY ; 0x80, Physical region descriptor table entries, 0 ~ 65535
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; so, this structure is variable-length
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ends
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; Contains virtual mappings for port phys memory regions
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struct PORT_DATA
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clb dd ? ; Command list base
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fb dd ? ; FIS base
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ctba_arr rd 32 ; ctba_arr[0] = clb[0].ctba, ... and so on.
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port dd ? ; address of correspoding HBA_PORT structure
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ends
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; Register FIS – Host to Device
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struct FIS_REG_H2D
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fis_type db ? ; FIS_TYPE_REG_H2D
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_flags db ? ; 0bCRRRPPPP, C - 1: Command, 0: Control
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; R - Reserved, P - Port multiplier
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command db ? ; Command register
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featurel db ? ; Feature register, 7:0
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lba0 db ? ; LBA low register, 7:0
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lba1 db ? ; LBA mid register, 15:8
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lba2 db ? ; LBA high register, 23:16
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device db ? ; Device register
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lba3 db ? ; LBA register, 31:24
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lba4 db ? ; LBA register, 39:32
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lba5 db ? ; LBA register, 47:40
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featureh db ? ; Feature register, 15:8
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countl db ? ; Count register, 7:0
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counth db ? ; Count register, 15:8
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icc db ? ; Isochronous command completion
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control db ? ; Control register
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rsv1 rb 4 ; Reserved
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ends
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; Register FIS – Device to Host
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struct FIS_REG_D2H
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fis_type db ? ; FIS_TYPE_REG_D2H
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_flags db ? ; 0bRIRPPPP, P - Port multiplier, R - Reserved
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; I - Interrupt bit
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status db ? ; Status register
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error db ? ; Error register
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lba0 db ? ; LBA low register, 7:0
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lba1 db ? ; LBA mid register, 15:8
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lba2 db ? ; LBA high register, 23:16
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device db ? ; Device register
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lba3 db ? ; LBA register, 31:24
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lba4 db ? ; LBA register, 39:32
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lba5 db ? ; LBA register, 47:40
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rsv2 db ? ; Reserved
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countl db ? ; Count register, 7:0
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counth db ? ; Count register, 15:8
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rsv3 rb 2 ; Reserved
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rsv4 rb 4 ; Reserved
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ends
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; Data FIS – Bidirectional
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struct FIS_DATA
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fis_type db ? ; FIS_TYPE_DATA
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_flags db ? ; 0bRRRRPPPP, R - Reserved, P - Port multiplier
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rsv1 rb 2 ; Reserved
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; DWORD 1 ~ N (?)
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data rd 1 ; Payload
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ends
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; PIO Setup – Device to Host
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struct FIS_PIO_SETUP
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fis_type db ? ; FIS_TYPE_PIO_SETUP
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_flags db ? ; 0bRIDRPPPP, P - Port multiplier, R - Reserved
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; I - Interrupt bit, D - Data transfer direction, 1 - device to host
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status db ? ; Status register
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error db ? ; Error register
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lba0 db ? ; LBA low register, 7:0
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lba1 db ? ; LBA mid register, 15:8
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lba2 db ? ; LBA high register, 23:16
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device db ? ; Device register
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lba3 db ? ; LBA register, 31:24
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lba4 db ? ; LBA register, 39:32
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lba5 db ? ; LBA register, 47:40
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rsv2 db ? ; Reserved
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countl db ? ; Count register, 7:0
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counth db ? ; Count register, 15:8
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rsv3 db ? ; Reserved
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e_status db ? ; New value of status register
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tc dw ? ; Transfer count
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rsv4 rb 2 ; Reserved
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ends
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; DMA Setup – Device to Host
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struct FIS_DMA_SETUP
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fis_type db ? ; FIS_TYPE_DMA_SETUP
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_flags db ? ; 0bAIDRPPPP, A - Auto-activate. Specifies if DMA Activate FIS is needed,
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; I - Interrupt bit, D - Data transfer direction, 1 - device to host,
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; R - Reserved, P - Port multiplier
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rsved rb 2 ; Reserved
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DMAbufferID dq ? ; DMA Buffer Identifier.
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; Used to Identify DMA buffer in host memory.
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; SATA Spec says host specific and not in Spec.
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; Trying AHCI spec might work.
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TransferCount dd ? ; Number of bytes to transfer. Bit 0 must be 0
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resvd dd ? ; Reserved
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ends
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; Set device bits FIS - device to host
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struct FIS_DEV_BITS
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fis_type db ? ; FIS_TYPE_DEV_BITS
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_flags db ? ; 0bNIRRPPPP, N - Notification, I - Interrupt,
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; R - Reserved, P - Port multiplier
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status db ? ; Status register
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error db ? ; Error register
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protocol dd ? ; Protocol
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ends
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struct HBA_FIS
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dsfis FIS_DMA_SETUP ; 0x00, DMA Setup FIS
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pad0 rb 4 ;
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psfis FIS_PIO_SETUP ; 0x20, PIO Setup FIS
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pad1 rb 12 ;
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rfis FIS_REG_D2H ; 0x40, Register - Device to Host FIS
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pad2 rb 4 ;
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sdbfis FIS_DEV_BITS ; 0x58, Set Device Bit FIS
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ufis rb 64 ; 0x60
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rsv rb (0x100 - 0xA0) ; 0xA0
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ends
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; --------------------------------------------------
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uglobal
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align 4
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ahci_controller AHCI_DATA
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port_data_arr rb (sizeof.PORT_DATA*AHCI_MAX_PORTS)
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endg
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; -----------------------------------------------------------------------
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; detect ahci controller and initialize
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align 4
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ahci_init:
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mov ecx, ahci_controller
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mov esi, pcidev_list
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.find_ahci_ctr:
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mov esi, [esi + PCIDEV.fd]
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cmp esi, pcidev_list
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jz .ahci_ctr_not_found
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mov eax, [esi + PCIDEV.class]
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;DEBUGF 1, "K: device class = %x\n", eax
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shr eax, 8 ; shift right because lowest 8 bits if ProgIf field
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cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass
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jz .ahci_ctr_found
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jmp .find_ahci_ctr
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.ahci_ctr_not_found:
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DEBUGF 1, "K: AHCI controller not found\n"
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ret
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.ahci_ctr_found:
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mov [ahci_controller + AHCI_DATA.pcidev], esi
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mov eax, [esi+PCIDEV.class]
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movzx ebx, byte [esi+PCIDEV.bus]
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movzx ecx, byte [esi+PCIDEV.devfn]
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shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code
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movzx edx, byte [esi+PCIDEV.devfn]
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and edx, 00000111b ; get only 3 lowest bits (function code)
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DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx
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; get BAR5 value, it is physical address
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movzx ebx, [esi + PCIDEV.bus]
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movzx ebp, [esi + PCIDEV.devfn]
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stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
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DEBUGF 1, "K: AHCI controller MMIO = %x\n", eax
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mov edi, eax
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; get the size of MMIO region
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stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, 0xFFFFFFFF
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stdcall pci_read32, ebx, ebp, PCI_REG_BAR5
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not eax
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inc eax
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DEBUGF 1, "K: AHCI: MMIO region size = 0x%x bytes\n", eax
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; Map MMIO region to virtual memory
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stdcall map_io_mem, edi, eax, PG_SWR + PG_NOCACHE
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mov [ahci_controller + AHCI_DATA.abar], eax
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DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax
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; Restore the original BAR5 value
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stdcall pci_write32, ebx, ebp, PCI_REG_BAR5, edi
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; Enable dma bus mastering, memory space access, clear the "disable interrupts" bit
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; Usually, it is already done before us
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movzx ebx, [esi + PCIDEV.bus]
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movzx ebp, [esi + PCIDEV.devfn]
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stdcall pci_read32, ebx, ebp, PCI_REG_STATUS_COMMAND
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DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax
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or eax, 0x06 ; pci.command |= 0x06 (dma bus mastering + memory space access)
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btr eax, 10 ; clear the "disable interrupts" bit
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DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax
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stdcall pci_write32, ebx, ebp, PCI_REG_STATUS_COMMAND, eax
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; ; Print some register values to debug board
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; mov esi, [ahci_controller + AHCI_DATA.abar]
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; DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.ghc], [esi + HBA_MEM.version]
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;-------------------------------------------------------
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; Request BIOS/OS ownership handoff, if supported. (TODO check correctness)
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mov esi, [ahci_controller + AHCI_DATA.abar]
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;mov ebx, [esi + HBA_MEM.cap2]
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;DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx
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bt [esi + HBA_MEM.cap2], bit_AHCI_HBA_CAP2_BOH
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jnc .end_handoff
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DEBUGF 1, "K: AHCI: requesting AHCI ownership change...\n"
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bts [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_OOS
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.wait_not_bos:
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bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BOS
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jc .wait_not_bos
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mov ebx, 3
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call delay_hs
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; if Bios Busy is still set after 30 mS, wait 2 seconds.
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bt [esi + HBA_MEM.bohc], bit_AHCI_HBA_BOHC_BB
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jnc @f
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mov ebx, 200
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call delay_hs
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@@:
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DEBUGF 1, "K: AHCI: ownership change completed.\n"
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.end_handoff:
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;-------------------------------------------------------
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; enable the AHCI and reset it
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bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
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bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
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; wait for reset to complete
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.wait_reset:
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bt [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_RESET
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jc .wait_reset
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; enable the AHCI and interrupts
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bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_AHCI_ENABLE
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bts [esi + HBA_MEM.ghc], bit_AHCI_HBA_GHC_INTERRUPT_ENABLE
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mov ebx, 2
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call delay_hs
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DEBUGF 1, "K: AHCI: caps: %x %x, ver: %x, ghc: %x, pi: %x\n", [esi + HBA_MEM.cap], [esi + HBA_MEM.cap2], [esi + HBA_MEM.version], [esi + HBA_MEM.ghc], [esi + HBA_MEM.pi]
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; TODO:
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; calculate irq line
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; ahciHBA->ghc |= AHCI_GHC_IE;
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; IDT::RegisterInterruptHandler(irq, InterruptHandler);
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; ahciHBA->is = 0xffffffff;
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xor ebx, ebx
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.detect_drives:
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cmp ebx, AHCI_MAX_PORTS
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jae .end_detect_drives
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; if port with index ebx is not implemented then go to next
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mov ecx, [esi + HBA_MEM.pi]
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bt ecx, ebx
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jnc .continue_detect_drives
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mov edi, ebx
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shl edi, BSF sizeof.HBA_PORT
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add edi, HBA_MEM.ports
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add edi, esi
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; now edi - base of HBA_MEM.ports[ebx]
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DEBUGF 1, "K: AHCI: port %d, ssts = %x\n", ebx, [edi + HBA_PORT.sata_status]
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mov ecx, [edi + HBA_PORT.sata_status]
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shr ecx, 8
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and ecx, 0x0F
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cmp ecx, AHCI_HBA_PORT_IPM_ACTIVE
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jne .continue_detect_drives
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mov ecx, [edi + HBA_PORT.sata_status]
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and ecx, AHCI_HBA_PxSSTS_DET
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cmp ecx, AHCI_HBA_PxSSTS_DET_PRESENT
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jne .continue_detect_drives
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DEBUGF 1, "K: AHCI: found drive at port %d, signature = %x\n", ebx, [edi + HBA_PORT.signature]
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mov ecx, ebx
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shl ecx, BSF sizeof.PORT_DATA
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add ecx, port_data_arr
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stdcall ahci_port_rebase, edi, ebx, ecx
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.continue_detect_drives:
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inc ebx
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jmp .detect_drives
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.end_detect_drives:
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|
||
ret
|
||
; -------------------------------------------------
|
||
|
||
; Start command engine
|
||
; in: eax - address of HBA_PORT structure
|
||
ahci_start_cmd:
|
||
.wait_cr: ; Wait until CR (bit15) is cleared
|
||
bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
|
||
jc .wait_cr
|
||
|
||
; Set FRE (bit4) and ST (bit0)
|
||
bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE
|
||
bts [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST
|
||
; maybe here call ahci flush cmd ? TODO (see seakernel)
|
||
ret
|
||
|
||
; Stop command engine
|
||
; in: eax - address of HBA_PORT structure
|
||
ahci_stop_cmd:
|
||
btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_ST ; Clear ST (bit0)
|
||
btr [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FRE ; Clear FRE (bit4)
|
||
.wait_fr_cr: ; Wait until FR (bit14), CR (bit15) are cleared
|
||
bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_FR
|
||
jc .wait_fr_cr
|
||
bt [eax + HBA_PORT.command], bit_AHCI_HBA_PxCMD_CR
|
||
jc .wait_fr_cr
|
||
|
||
ret
|
||
|
||
; The commands may not take effect until the command
|
||
; register is read again by software, because reasons.
|
||
; in: eax - address of HBA_PORT structure
|
||
; out: eax - command register value
|
||
ahci_flush_cmd:
|
||
mov eax, [eax + HBA_PORT.command]
|
||
ret
|
||
|
||
; Send command to port
|
||
; in: eax - address of HBA_PORT structure
|
||
; ebx - index of command slot
|
||
ahci_send_cmd:
|
||
push ecx
|
||
mov [eax + HBA_PORT.interrupt_status], 0xFFFFFFFF
|
||
|
||
mov cl, bl
|
||
mov [eax + HBA_PORT.command_issue], 1
|
||
shl [eax + HBA_PORT.command_issue], cl
|
||
|
||
call ahci_flush_cmd
|
||
pop ecx
|
||
ret
|
||
|
||
; ---------------------------------------------------------------------------
|
||
; TODO: check correctness
|
||
; in: port - address of HBA_PORT structure
|
||
; portno - port index (0..31)
|
||
; pdata - address of PORT_DATA structure
|
||
proc ahci_port_rebase stdcall, port: dword, portno: dword, pdata: dword
|
||
locals
|
||
phys_page1 dd ?
|
||
virt_page1 dd ?
|
||
phys_page23 dd ?
|
||
virt_page23 dd ?
|
||
tmp dd ?
|
||
endl
|
||
|
||
pushad
|
||
|
||
DEBUGF 1, "Rebasing port %u\n", [portno]
|
||
|
||
mov eax, [port]
|
||
call ahci_stop_cmd
|
||
|
||
; Command list entry size = 32
|
||
; Command list entry maxim count = 32
|
||
; Command list maxim size = 32*32 = 1K per port
|
||
call alloc_page
|
||
mov [phys_page1], eax
|
||
|
||
stdcall map_io_mem, eax, 4096, PG_NOCACHE + PG_SWR ; map to virt memory so we can work with it
|
||
mov [virt_page1], eax
|
||
|
||
mov esi, [port]
|
||
mov ebx, [phys_page1]
|
||
mov [esi + HBA_PORT.command_list_base_l], ebx ; set the command list base
|
||
mov [esi + HBA_PORT.command_list_base_h], 0 ; zero upper 32 bits of addr cause we are 32 bit os
|
||
|
||
mov edi, [pdata]
|
||
mov ebx, [virt_page1]
|
||
mov [edi + PORT_DATA.clb], ebx ; set pdata->clb
|
||
|
||
mov eax, [port]
|
||
mov [edi + PORT_DATA.port], eax ; set pdata->port
|
||
|
||
stdcall _memset, ebx, 0, 1024 ; zero out the command list
|
||
|
||
; FIS entry size = 256 bytes per port
|
||
mov eax, [phys_page1]
|
||
add eax, 1024
|
||
mov [esi + HBA_PORT.fis_base_l], eax
|
||
mov [esi + HBA_PORT.fis_base_h], 0
|
||
|
||
mov eax, [virt_page1]
|
||
add eax, 1024
|
||
mov [edi + PORT_DATA.fb], eax ; set pdata->fb
|
||
stdcall _memset, eax, 0, 256 ; zero out
|
||
|
||
stdcall alloc_pages, 2
|
||
mov [phys_page23], eax
|
||
stdcall map_io_mem, eax, 2*4096, PG_NOCACHE + PG_SWR
|
||
mov [virt_page23], eax
|
||
|
||
; Command table size = 256*32 = 8K per port
|
||
mov edx, [edi + PORT_DATA.clb] ; cmdheader array base
|
||
xor ecx, ecx
|
||
|
||
.for1:
|
||
cmp ecx, 32
|
||
jae .for1_end
|
||
|
||
mov ebx, ecx
|
||
shl ebx, BSF sizeof.HBA_CMD_HDR
|
||
add ebx, edx ; ebx = cmdheader[ecx]
|
||
|
||
mov [ebx + HBA_CMD_HDR.prdtl], 8 ; 8 prdt entries per command table
|
||
|
||
; 256 bytes per command table, 64+16+48+16*8
|
||
|
||
push edx
|
||
|
||
; cmdheader[ecx].ctba = phys_page23 + ecx*256
|
||
mov [ebx + HBA_CMD_HDR.ctba], ecx
|
||
shl [ebx + HBA_CMD_HDR.ctba], BSF 256 ; *= 256
|
||
mov eax, [ebx + HBA_CMD_HDR.ctba]
|
||
mov edx, [phys_page23]
|
||
add [ebx + HBA_CMD_HDR.ctba], edx
|
||
|
||
add eax, [virt_page23]
|
||
mov [tmp], eax ; tmp = virt_page23 + ecx*256
|
||
lea eax, [ecx*4 + edi + PORT_DATA.ctba_arr] ; eax = pdata->ctba_arr[ecx]
|
||
mov edx, [tmp]
|
||
mov [eax], edx ; pdata->ctba_arr[ecx] = virt_page23 + ecx*256
|
||
|
||
pop edx
|
||
|
||
mov [ebx + HBA_CMD_HDR.ctbau], 0
|
||
stdcall _memset, [eax], 0, 256 ; zero out
|
||
|
||
inc ecx
|
||
jmp .for1
|
||
.for1_end:
|
||
|
||
mov eax, [port]
|
||
call ahci_start_cmd
|
||
|
||
DEBUGF 1, "End rebasing port %u\n", [portno]
|
||
popad
|
||
ret
|
||
endp
|
||
|
||
; ----------------------------------------------------------- ; TODO check
|
||
; Find a free command list slot
|
||
; in: eax - address of HBA_PORT structure
|
||
; out: eax - if not found -1, else slot index
|
||
ahci_find_cmdslot:
|
||
push ebx ecx edx esi
|
||
; If not set in SACT and CI, the slot is free
|
||
mov ebx, [eax + HBA_PORT.sata_active]
|
||
or ebx, [eax + HBA_PORT.command_issue] ; ebx = slots
|
||
|
||
mov esi, [ahci_controller + AHCI_DATA.abar]
|
||
mov edx, [esi + HBA_MEM.cap]
|
||
shr edx, 8
|
||
and edx, 0xf
|
||
DEBUGF 1, "Number of Command Slots on each port = %u\n", edx
|
||
xor ecx, ecx
|
||
.for1:
|
||
cmp ecx, edx
|
||
jae .for1_end
|
||
|
||
; if ((slots&1) == 0) return i;
|
||
bt ebx, 0
|
||
jc .cont1
|
||
|
||
mov eax, ecx
|
||
jmp .ret
|
||
|
||
.cont1:
|
||
shr ebx, 1
|
||
inc ecx
|
||
jmp .for1
|
||
.for1_end:
|
||
DEBUGF 1, "Cannot find free command list entry\n"
|
||
mov eax, -1
|
||
.ret:
|
||
pop esi edx ecx ebx
|
||
ret
|
||
|
||
|
||
proc _memset stdcall, dest:dword, val:byte, cnt:dword ; doesnt clobber any registers
|
||
;DEBUGF DBG_INFO, "memset(%x, %u, %u)\n", [dest], [val], [cnt]
|
||
push eax ecx edi
|
||
mov edi, dword [dest]
|
||
mov al, byte [val]
|
||
mov ecx, dword [cnt]
|
||
rep stosb
|
||
pop edi ecx eax
|
||
ret
|
||
endp
|