forked from KolibriOS/kolibrios
1167 lines
30 KiB
NASM
1167 lines
30 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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format MS COFF
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DEBUG equ 1
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include 'proc32.inc'
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include 'imports.inc'
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API_VERSION equ 0x01000100
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USE_COM_IRQ equ 0 ;make irq 3 and irq 4 available for PCI devices
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IRQ_REMAP equ 0
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IRQ_LINE equ 0
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;irq 0,1,2,8,12,13 ¥¤®áâã¯ë
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; FEDCBA9876543210
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VALID_IRQ equ 1100111011111000b
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ATTCH_IRQ equ 0000111010100000b
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if USE_COM_IRQ
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ATTCH_IRQ equ 0000111010111000b
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end if
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CPU_FREQ equ 2600d
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BIT0 EQU 0x00000001
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BIT1 EQU 0x00000002
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BIT5 EQU 0x00000020
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BIT10 EQU 0x00000400
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VID_Creative equ 0x1102
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CTRL_CT0200 equ 0x0006 ; Dell OEM version (EMU10K1X)
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CODEC_MASTER_VOL_REG equ 0x02
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CODEC_AUX_VOL equ 0x04 ;
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CODEC_PCM_OUT_REG equ 0x18 ; PCM output volume
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CODEC_EXT_AUDIO_REG equ 0x28 ; extended audio
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CODEC_EXT_AUDIO_CTRL_REG equ 0x2a ; extended audio control
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CODEC_PCM_FRONT_DACRATE_REG equ 0x2c ; PCM out sample rate
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CODEC_PCM_SURND_DACRATE_REG equ 0x2e ; surround sound sample rate
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CODEC_PCM_LFE_DACRATE_REG equ 0x30 ; LFE sample rate
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;EMU10K1(X) host controller registers set
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;; common offsets
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;; some definitions were borrowed from emu10k1 driver as they seem to be the same
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;;**********************************************************************************************;;
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;; PCI function 0 registers, address = <val> + PCIBASE0 ;;
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;;**********************************************************************************************;;
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PTR equ 0x00 ;; Indexed register set pointer register ;;
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;; NOTE: The CHANNELNUM and ADDRESS words can ;;
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;; be modified independently of each other. ;;
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DATA equ 0x04 ;; Indexed register set data register ;;
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IPR equ 0x08 ;; Global interrupt pending register ;;
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;; Clear pending interrupts by writing a 1 to ;;
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;; the relevant bits and zero to the other bits ;;
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IPR_MIDITRANSBUFEMPTY equ 0x00000001 ;; MIDI UART transmit buffer empty ;;
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IPR_MIDIRECVBUFEMPTY equ 0x00000002 ;; MIDI UART receive buffer empty ;;
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IPR_CH_0_LOOP equ 0x00000800 ;; Channel 0 loop ;;
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IPR_CH_0_HALF_LOOP equ 0x00000100 ;; Channel 0 half loop ;;
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IPR_CAP_0_LOOP equ 0x00080000 ;; Channel capture loop ;;
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IPR_CAP_0_HALF_LOOP equ 0x00010000 ;; Channel capture half loop ;;
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INTE equ 0x0c ;; Interrupt enable register ;;
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INTE_MIDITXENABLE equ 0x00000001 ;; Enable MIDI transmit-buffer-empty interrupts ;;
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INTE_MIDIRXENABLE equ 0x00000002 ;; Enable MIDI receive-buffer-empty interrupts ;;
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INTE_CH_0_LOOP equ 0x00000800 ;; Channel 0 loop ;;
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INTE_CH_0_HALF_LOOP equ 0x00000100 ;; Channel 0 half loop ;;
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INTE_CAP_0_LOOP equ 0x00080000 ;; Channel capture loop ;;
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INTE_CAP_0_HALF_LOOP equ 0x00010000 ;; Channel capture half loop ;;
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HCFG equ 0x14 ;; Hardware config register ;;
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HCFG_LOCKSOUNDCACHE equ 0x00000008 ;; 1 = Cancel bustmaster accesses to soundcache ;;
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;; NOTE: This should generally never be used. ;;
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HCFG_AUDIOENABLE equ 0x00000001 ;; 0 = CODECs transmit zero-valued samples ;;
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;; Should be set to 1 when the EMU10K1 is ;;
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;; completely initialized. ;;
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GPIO equ 0x18 ;; Defaults: 00001080-Analog, 00001000-SPDIF. ;;
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AC97DATA equ 0x1c ;; AC97 register set data register (16 bit) ;;
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AC97ADDRESS equ 0x1e ;; AC97 register set address register (8 bit) ;;
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;;******************************************************************************************************;;
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;; Emu10k1x pointer-offset register set, accessed through the PTR and DATA registers ;;
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;;******************************************************************************************************;;
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PLAYBACK_LIST_ADDR equ 0x00 ;; Base DMA address of a list of pointers to each period/size ;;
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;; One list entry: 4 bytes for DMA address,
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;; 4 bytes for period_size << 16.
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;; One list entry is 8 bytes long.
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;; One list entry for each period in the buffer.
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;;
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PLAYBACK_LIST_SIZE equ 0x01 ;; Size of list in bytes << 19. E.g. 8 periods -> 0x00380000 ;;
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PLAYBACK_LIST_PTR equ 0x02 ;; Pointer to the current period being played ;;
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PLAYBACK_DMA_ADDR equ 0x04 ;; Playback DMA addresss ;;
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PLAYBACK_PERIOD_SIZE equ 0x05 ;; Playback period size ;;
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PLAYBACK_POINTER equ 0x06 ;; Playback period pointer. Sample currently in DAC ;;
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PLAYBACK_UNKNOWN1 equ 0x07
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PLAYBACK_UNKNOWN2 equ 0x08
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;; Only one capture channel supported ;;
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CAPTURE_DMA_ADDR equ 0x10 ;; Capture DMA address ;;
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CAPTURE_BUFFER_SIZE equ 0x11 ;; Capture buffer size ;;
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CAPTURE_POINTER equ 0x12 ;; Capture buffer pointer. Sample currently in ADC ;;
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CAPTURE_UNKNOWN equ 0x13
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;; From 0x20 - 0x3f, last samples played on each channel ;;
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TRIGGER_CHANNEL equ 0x40 ;; Trigger channel playback ;;
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TRIGGER_CHANNEL_0 equ 0x00000001 ;; Trigger channel 0 ;;
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TRIGGER_CHANNEL_1 equ 0x00000002 ;; Trigger channel 1 ;;
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TRIGGER_CHANNEL_2 equ 0x00000004 ;; Trigger channel 2 ;;
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TRIGGER_CAPTURE equ 0x00000100 ;; Trigger capture channel ;;
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ROUTING equ 0x41 ;; Setup sound routing ? ;;
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ROUTING_FRONT_LEFT equ 0x00000001
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ROUTING_FRONT_RIGHT equ 0x00000002
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ROUTING_REAR_LEFT equ 0x00000004
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ROUTING_REAR_RIGHT equ 0x00000008
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ROUTING_CENTER_LFE equ 0x00010000
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SPCS0 equ 0x42 ;; SPDIF output Channel Status 0 register ;;
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SPCS1 equ 0x43 ;; SPDIF output Channel Status 1 register ;;
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SPCS2 equ 0x44 ;; SPDIF output Channel Status 2 register ;;
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SPCS_CLKACCYMASK equ 0x30000000 ;; Clock accuracy ;;
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SPCS_CLKACCY_1000PPM equ 0x00000000 ;; 1000 parts per million ;;
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SPCS_CLKACCY_50PPM equ 0x10000000 ;; 50 parts per million ;;
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SPCS_CLKACCY_VARIABLE equ 0x20000000 ;; Variable accuracy ;;
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SPCS_SAMPLERATEMASK equ 0x0f000000 ;; Sample rate ;;
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SPCS_SAMPLERATE_44 equ 0x00000000 ;; 44.1kHz sample rate ;;
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SPCS_SAMPLERATE_48 equ 0x02000000 ;; 48kHz sample rate ;;
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SPCS_SAMPLERATE_32 equ 0x03000000 ;; 32kHz sample rate ;;
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SPCS_CHANNELNUMMASK equ 0x00f00000 ;; Channel number ;;
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SPCS_CHANNELNUM_UNSPEC equ 0x00000000 ;; Unspecified channel number ;;
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SPCS_CHANNELNUM_LEFT equ 0x00100000 ;; Left channel ;;
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SPCS_CHANNELNUM_RIGHT equ 0x00200000 ;; Right channel ;;
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SPCS_SOURCENUMMASK equ 0x000f0000 ;; Source number ;;
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SPCS_SOURCENUM_UNSPEC equ 0x00000000 ;; Unspecified source number ;;
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SPCS_GENERATIONSTATUS equ 0x00008000 ;; Originality flag (see IEC-958 spec) ;;
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SPCS_CATEGORYCODEMASK equ 0x00007f00 ;; Category code (see IEC-958 spec) ;;
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SPCS_MODEMASK equ 0x000000c0 ;; Mode (see IEC-958 spec) ;;
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SPCS_EMPHASISMASK equ 0x00000038 ;; Emphasis ;;
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SPCS_EMPHASIS_NONE equ 0x00000000 ;; No emphasis ;;
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SPCS_EMPHASIS_50_15 equ 0x00000008 ;; 50/15 usec 2 channel ;;
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SPCS_COPYRIGHT equ 0x00000004 ;; Copyright asserted flag -- do not modify ;;
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SPCS_NOTAUDIODATA equ 0x00000002 ;; 0 = Digital audio, 1 = not audio ;;
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SPCS_PROFESSIONAL equ 0x00000001 ;; 0 = Consumer (IEC-958), 1 = pro (AES3-1992) ;;
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SPDIF_SELECT equ 0x45 ;; Enables SPDIF or Analogue outputs 0-Analogue, 0x700-SPDIF ;;
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;; This is the MPU port on the card ;;
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MUDATA equ 0x47
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MUCMD equ 0x48
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MUSTAT equ MUCMD
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;; From 0x50 - 0x5f, last samples captured ;;
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SRV_GETVERSION equ 0
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DEV_PLAY equ 1
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DEV_STOP equ 2
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DEV_CALLBACK equ 3
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DEV_SET_BUFF equ 4
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DEV_NOTIFY equ 5
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DEV_SET_MASTERVOL equ 6
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DEV_GET_MASTERVOL equ 7
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DEV_GET_INFO equ 8
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struc AC_CNTRL ;AC controller base class
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{ .bus dd ?
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.devfn dd ?
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.vendor dd ?
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.dev_id dd ?
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.pci_cmd dd ?
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.pci_stat dd ?
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.codec_io_base dd ?
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.codec_mem_base dd ?
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.ctrl_io_base dd ?
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.ctrl_mem_base dd ?
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.cfg_reg dd ?
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.int_line dd ?
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.vendor_ids dd ? ;vendor id string
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.ctrl_ids dd ? ;hub id string
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.buffer dd ?
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.notify_pos dd ?
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.notify_task dd ?
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.lvi_reg dd ?
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.ctrl_setup dd ?
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.user_callback dd ?
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.codec_read16 dd ?
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.codec_write16 dd ?
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.ctrl_read8 dd ?
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.ctrl_read16 dd ?
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.ctrl_read32 dd ?
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.ctrl_write8 dd ?
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.ctrl_write16 dd ?
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.ctrl_write32 dd ?
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}
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struc CODEC ;Audio Chip base class
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{
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.chip_id dd ?
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.flags dd ?
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.status dd ?
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.ac_vendor_ids dd ? ;ac vendor id string
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.chip_ids dd ? ;chip model string
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.shadow_flag dd ?
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dd ?
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.regs dw ? ; codec registers
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.reg_master_vol dw ? ;0x02
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.reg_aux_out_vol dw ? ;0x04
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.reg_mone_vol dw ? ;0x06
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.reg_master_tone dw ? ;0x08
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.reg_beep_vol dw ? ;0x0A
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.reg_phone_vol dw ? ;0x0C
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.reg_mic_vol dw ? ;0x0E
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.reg_line_in_vol dw ? ;0x10
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.reg_cd_vol dw ? ;0x12
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.reg_video_vol dw ? ;0x14
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.reg_aux_in_vol dw ? ;0x16
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.reg_pcm_out_vol dw ? ;0x18
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.reg_rec_select dw ? ;0x1A
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.reg_rec_gain dw ? ;0x1C
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.reg_rec_gain_mic dw ? ;0x1E
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.reg_gen dw ? ;0x20
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.reg_3d_ctrl dw ? ;0X22
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.reg_page dw ? ;0X24
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.reg_powerdown dw ? ;0x26
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.reg_ext_audio dw ? ;0x28
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.reg_ext_st dw ? ;0x2a
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.reg_pcm_front_rate dw ? ;0x2c
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.reg_pcm_surr_rate dw ? ;0x2e
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.reg_lfe_rate dw ? ;0x30
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.reg_pcm_in_rate dw ? ;0x32
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dw ? ;0x34
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.reg_cent_lfe_vol dw ? ;0x36
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.reg_surr_vol dw ? ;0x38
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.reg_spdif_ctrl dw ? ;0x3A
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dw ? ;0x3C
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dw ? ;0x3E
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dw ? ;0x40
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dw ? ;0x42
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dw ? ;0x44
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dw ? ;0x46
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dw ? ;0x48
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dw ? ;0x4A
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dw ? ;0x4C
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dw ? ;0x4E
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dw ? ;0x50
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dw ? ;0x52
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dw ? ;0x54
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dw ? ;0x56
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dw ? ;0x58
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dw ? ;0x5A
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dw ? ;0x5C
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dw ? ;0x5E
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.reg_page_0 dw ? ;0x60
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.reg_page_1 dw ? ;0x62
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.reg_page_2 dw ? ;0x64
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.reg_page_3 dw ? ;0x66
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.reg_page_4 dw ? ;0x68
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.reg_page_5 dw ? ;0x6A
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.reg_page_6 dw ? ;0x6C
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.reg_page_7 dw ? ;0x6E
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dw ? ;0x70
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dw ? ;0x72
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dw ? ;0x74
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dw ? ;0x76
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dw ? ;0x78
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dw ? ;0x7A
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.reg_vendor_id_1 dw ? ;0x7C
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.reg_vendor_id_2 dw ? ;0x7E
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.reset dd ? ;virual
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.set_master_vol dd ?
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}
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struc CTRL_INFO
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{ .pci_cmd dd ?
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.irq dd ?
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.glob_cntrl dd ?
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.glob_sta dd ?
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.codec_io_base dd ?
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.ctrl_io_base dd ?
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.codec_mem_base dd ?
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.ctrl_mem_base dd ?
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.codec_id dd ?
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}
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struc IOCTL
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{ .handle dd ?
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.io_code dd ?
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.input dd ?
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.inp_size dd ?
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.output dd ?
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.out_size dd ?
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}
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virtual at 0
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IOCTL IOCTL
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end virtual
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EVENT_NOTIFY equ 0x00000200
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public START
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public service_proc
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public version
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section '.flat' code readable align 16
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proc START stdcall, state:dword
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cmp [state], 1
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jne .stop
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if DEBUG
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mov esi, msgInit
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call SysMsgBoardStr
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end if
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call detect_controller
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test eax, eax
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jz .fail
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if DEBUG
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mov esi,[ctrl.vendor_ids]
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call SysMsgBoardStr
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mov esi, [ctrl.ctrl_ids]
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call SysMsgBoardStr
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end if
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call init_controller
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test eax, eax
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jz .fail
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call init_codec
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test eax, eax
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jz .fail
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call setup_codec
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mov esi, msgPrimBuff
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call SysMsgBoardStr
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call create_primary_buff
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mov esi, msgDone
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call SysMsgBoardStr
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if IRQ_REMAP
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pushf
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cli
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mov ebx, [ctrl.int_line]
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in al, 0xA1
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mov ah, al
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in al, 0x21
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test ebx, ebx
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jz .skip
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bts ax, bx ;mask old line
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.skip:
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bts ax, IRQ_LINE ;mask new ine
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out 0x21, al
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mov al, ah
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out 0xA1, al
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stdcall PciWrite8, 0, 0xF8, 0x61, IRQ_LINE ;remap IRQ
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mov dx, 0x4d0 ;8259 ELCR1
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in al, dx
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bts ax, IRQ_LINE
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out dx, al ;set level-triggered mode
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mov [ctrl.int_line], IRQ_LINE
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popf
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mov esi, msgRemap
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call SysMsgBoardStr
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end if
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mov eax, VALID_IRQ
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mov ebx, [ctrl.int_line]
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mov esi, msgInvIRQ
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bt eax, ebx
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jnc .fail_msg
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mov eax, ATTCH_IRQ
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mov esi, msgAttchIRQ
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bt eax, ebx
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jnc .fail_msg
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stdcall AttachIntHandler, ebx, ac97_irq, dword 0
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stdcall create
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.reg:
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stdcall RegService, sz_sound_srv, service_proc
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ret
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.fail:
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if DEBUG
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mov esi, msgFail
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call SysMsgBoardStr
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end if
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xor eax, eax
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ret
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.fail_msg:
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call SysMsgBoardStr
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xor eax, eax
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ret
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.stop:
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call stop
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xor eax, eax
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ret
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endp
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handle equ IOCTL.handle
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io_code equ IOCTL.io_code
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input equ IOCTL.input
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inp_size equ IOCTL.inp_size
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output equ IOCTL.output
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out_size equ IOCTL.out_size
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align 4
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proc service_proc stdcall, ioctl:dword
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mov edi, [ioctl]
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mov eax, [edi+io_code]
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cmp eax, SRV_GETVERSION
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jne @F
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mov eax, [edi+output]
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cmp [edi+out_size], 4
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jne .fail
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mov [eax], dword API_VERSION
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xor eax, eax
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ret
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@@:
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cmp eax, DEV_PLAY
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jne @F
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if DEBUG
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mov esi, msgPlay
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call SysMsgBoardStr
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end if
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call play
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ret
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@@:
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cmp eax, DEV_STOP
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jne @F
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if DEBUG
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mov esi, msgStop
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call SysMsgBoardStr
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end if
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call stop
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ret
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@@:
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cmp eax, DEV_CALLBACK
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jne @F
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mov ebx, [edi+input]
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stdcall set_callback, [ebx]
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ret
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@@:
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cmp eax, DEV_SET_MASTERVOL
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jne @F
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mov eax, [edi+input]
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mov eax, [eax]
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call set_master_vol ;eax= vol
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ret
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@@:
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cmp eax, DEV_GET_MASTERVOL
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jne @F
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mov ebx, [edi+output]
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stdcall get_master_vol, ebx
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ret
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@@:
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cmp eax, DEV_GET_INFO
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jne @F
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mov ebx, [edi+output]
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stdcall get_dev_info, ebx
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ret
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@@:
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.fail:
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or eax, -1
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ret
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endp
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restore handle
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restore io_code
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restore input
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restore inp_size
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restore output
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restore out_size
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align 4
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proc ac97_irq
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locals
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status dd 0
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endl
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; status = inl(chip->port + IPR);
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mov edx, IPR
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call [ctrl.ctrl_read32]
|
|
test eax, eax
|
|
jz @f
|
|
|
|
mov dword [status], eax
|
|
|
|
mov ebx, dword [buff_list]
|
|
cmp [ctrl.user_callback], 0
|
|
je @f
|
|
stdcall [ctrl.user_callback], ebx
|
|
@@:
|
|
mov eax, dword [status] ;; ack ;;
|
|
mov edx, IPR
|
|
call [ctrl.ctrl_write32]
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc create_primary_buff
|
|
|
|
stdcall KernelAlloc, 0x10000
|
|
mov [ctrl.buffer], eax
|
|
|
|
mov edi, eax
|
|
mov ecx, 0x10000/4
|
|
xor eax, eax
|
|
cld
|
|
rep stosd
|
|
|
|
mov eax, [ctrl.buffer]
|
|
call GetPgAddr
|
|
|
|
mov edi, pcmout_bdl
|
|
stosd
|
|
mov eax, 0x4000000
|
|
stosd
|
|
|
|
mov edi, buff_list
|
|
mov eax, [ctrl.buffer]
|
|
stosd ;1.]
|
|
|
|
mov eax, [ctrl.buffer]
|
|
call GetPgAddr
|
|
|
|
stdcall ptr_write, PLAYBACK_POINTER, 0, 0
|
|
stdcall ptr_write, PLAYBACK_UNKNOWN1, 0, 0
|
|
stdcall ptr_write, PLAYBACK_UNKNOWN2, 0, 0
|
|
stdcall ptr_write, PLAYBACK_DMA_ADDR, 0, eax
|
|
|
|
mov eax, pcmout_bdl
|
|
mov ebx, eax
|
|
call GetPgAddr
|
|
and ebx, 0xFFF
|
|
add eax, ebx
|
|
|
|
stdcall ptr_write, PLAYBACK_LIST_ADDR, 0, eax
|
|
stdcall ptr_write, PLAYBACK_LIST_SIZE, 0, 0
|
|
stdcall ptr_write, PLAYBACK_LIST_PTR, 0, 0
|
|
|
|
;mov eax, 0x00004000
|
|
;shl eax, 16
|
|
stdcall ptr_write, PLAYBACK_PERIOD_SIZE, 0, 0x40000000;eax
|
|
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc detect_controller
|
|
locals
|
|
last_bus dd ?
|
|
bus dd ?
|
|
devfn dd ?
|
|
endl
|
|
|
|
xor eax, eax
|
|
mov [bus], eax
|
|
inc eax
|
|
call PciApi
|
|
cmp eax, -1
|
|
je .err
|
|
|
|
mov [last_bus], eax
|
|
|
|
.next_bus:
|
|
and [devfn], 0
|
|
.next_dev:
|
|
stdcall PciRead32, [bus], [devfn], dword 0
|
|
test eax, eax
|
|
jz .next
|
|
cmp eax, -1
|
|
je .next
|
|
|
|
mov edi, devices
|
|
@@:
|
|
mov ebx, [edi]
|
|
test ebx, ebx
|
|
jz .next
|
|
|
|
cmp eax, ebx
|
|
je .found
|
|
add edi, 12
|
|
jmp @B
|
|
.next:
|
|
inc [devfn]
|
|
cmp [devfn], 256
|
|
jb .next_dev
|
|
mov eax, [bus]
|
|
inc eax
|
|
mov [bus], eax
|
|
cmp eax, [last_bus]
|
|
jna .next_bus
|
|
xor eax, eax
|
|
ret
|
|
.found:
|
|
mov ebx, [bus]
|
|
mov [ctrl.bus], ebx
|
|
|
|
mov ecx, [devfn]
|
|
mov [ctrl.devfn], ecx
|
|
|
|
mov edx, eax
|
|
and edx, 0xFFFF
|
|
mov [ctrl.vendor], edx
|
|
shr eax, 16
|
|
mov [ctrl.dev_id], eax
|
|
|
|
mov ebx, [edi+4]
|
|
mov [ctrl.ctrl_ids], ebx
|
|
mov esi, [edi+8]
|
|
mov [ctrl.ctrl_setup], esi
|
|
|
|
cmp edx, VID_Creative
|
|
jne @F
|
|
mov [ctrl.vendor_ids], msg_Creative
|
|
ret
|
|
@@:
|
|
|
|
.err:
|
|
xor eax, eax
|
|
mov [ctrl.vendor_ids], eax ;something wrong ?
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc init_controller
|
|
|
|
stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 0x2C
|
|
mov esi, msgPciSubsys
|
|
call SysMsgBoardStr
|
|
call dword2str
|
|
call SysMsgBoardStr
|
|
|
|
stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 4
|
|
mov ebx, eax
|
|
and eax, 0xFFFF
|
|
mov [ctrl.pci_cmd], eax
|
|
shr ebx, 16
|
|
mov [ctrl.pci_stat], ebx
|
|
|
|
mov esi, msgPciCmd
|
|
call SysMsgBoardStr
|
|
call dword2str
|
|
call SysMsgBoardStr
|
|
|
|
mov esi, msgPciStat
|
|
call SysMsgBoardStr
|
|
mov eax, [ctrl.pci_stat]
|
|
call dword2str
|
|
call SysMsgBoardStr
|
|
|
|
mov esi, msgCtrlIsaIo
|
|
call SysMsgBoardStr
|
|
stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 0x10
|
|
call dword2str
|
|
call SysMsgBoardStr
|
|
|
|
and eax, 0xFFC0
|
|
mov [ctrl.ctrl_io_base], eax
|
|
|
|
.default:
|
|
stdcall PciRead32, [ctrl.bus], [ctrl.devfn], dword 0x3C
|
|
and eax, 0xFF
|
|
@@:
|
|
mov [ctrl.int_line], eax
|
|
|
|
call [ctrl.ctrl_setup]
|
|
xor eax, eax
|
|
inc eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc set_Creative
|
|
mov [ctrl.codec_read16], codec_io_r16 ;virtual
|
|
mov [ctrl.codec_write16], codec_io_w16 ;virtual
|
|
|
|
mov [ctrl.ctrl_read8 ], ctrl_io_r8 ;virtual
|
|
mov [ctrl.ctrl_read16], ctrl_io_r16 ;virtual
|
|
mov [ctrl.ctrl_read32], ctrl_io_r32 ;virtual
|
|
|
|
mov [ctrl.ctrl_write8 ], ctrl_io_w8 ;virtual
|
|
mov [ctrl.ctrl_write16], ctrl_io_w16 ;virtual
|
|
mov [ctrl.ctrl_write32], ctrl_io_w32 ;virtual
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc init_codec
|
|
call reset_codec
|
|
test eax, eax
|
|
jz .err
|
|
call detect_codec
|
|
xor eax, eax
|
|
inc eax
|
|
ret
|
|
.err:
|
|
xor eax, eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc reset_codec
|
|
locals
|
|
counter dd ?
|
|
endl
|
|
|
|
if DEBUG
|
|
mov esi, msgCold
|
|
call SysMsgBoardStr
|
|
end if
|
|
|
|
mov eax, 100000 ; wait 100 ms ;400000 ; wait 400 ms
|
|
call StallExec
|
|
|
|
stdcall ptr_read, TRIGGER_CHANNEL, 0
|
|
|
|
mov [counter], 16 ; total 20*100 ms = 2s
|
|
.wait:
|
|
stdcall codec_read, dword 0x26
|
|
test eax, 1
|
|
jnz .ok
|
|
|
|
mov eax, 100000 ; wait 100 ms
|
|
call StallExec
|
|
|
|
dec [counter]
|
|
jnz .wait
|
|
|
|
if DEBUG
|
|
mov esi, msgCRFail
|
|
call SysMsgBoardStr
|
|
end if
|
|
|
|
.fail:
|
|
stc
|
|
ret
|
|
.ok:
|
|
|
|
|
|
xor eax, eax
|
|
inc eax
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
play:
|
|
mov eax, INTE_CH_0_LOOP
|
|
stdcall intr_enable, eax
|
|
|
|
stdcall ptr_read, TRIGGER_CHANNEL, 0
|
|
mov ebx, TRIGGER_CHANNEL_0
|
|
or eax, ebx
|
|
stdcall ptr_write, TRIGGER_CHANNEL, 0, eax
|
|
|
|
xor eax, eax
|
|
ret
|
|
|
|
align 4
|
|
stop:
|
|
mov eax, INTE_CH_0_LOOP or INTE_CH_0_HALF_LOOP
|
|
stdcall intr_disable, eax
|
|
|
|
stdcall ptr_read, TRIGGER_CHANNEL, 0
|
|
mov ebx, TRIGGER_CHANNEL_0
|
|
xor ebx, -1
|
|
or eax, ebx
|
|
stdcall ptr_write, TRIGGER_CHANNEL, 0, eax
|
|
xor eax, eax
|
|
ret
|
|
|
|
align 4
|
|
proc get_dev_info stdcall, p_info:dword
|
|
virtual at esi
|
|
CTRL_INFO CTRL_INFO
|
|
end virtual
|
|
|
|
mov esi, [p_info]
|
|
mov eax, [ctrl.int_line]
|
|
mov ecx, [ctrl.ctrl_io_base]
|
|
mov [CTRL_INFO.irq], eax
|
|
mov [CTRL_INFO.ctrl_io_base], ecx
|
|
mov eax, [codec.chip_id]
|
|
mov [CTRL_INFO.codec_id], eax
|
|
mov ebx, [ctrl.pci_cmd]
|
|
mov [CTRL_INFO.pci_cmd], ebx
|
|
|
|
xor eax, eax
|
|
mov [CTRL_INFO.codec_io_base], eax
|
|
mov [CTRL_INFO.codec_mem_base], eax
|
|
mov [CTRL_INFO.ctrl_mem_base], eax
|
|
mov [CTRL_INFO.glob_cntrl], eax
|
|
mov [CTRL_INFO.glob_sta], eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc set_callback stdcall, handler:dword
|
|
mov eax, [handler]
|
|
mov [ctrl.user_callback], eax
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc create stdcall
|
|
stdcall PciRead16, [ctrl.bus], [ctrl.devfn], dword 4
|
|
test eax, 4 ; test master bit
|
|
jnz @f
|
|
or eax, 4
|
|
stdcall PciWrite16, [ctrl.bus], [ctrl.devfn], dword 4, eax ; set master bit
|
|
@@:
|
|
|
|
xor eax, eax
|
|
mov edx, INTE
|
|
call [ctrl.ctrl_write32]
|
|
|
|
stdcall ptr_write, SPCS0, 0, \
|
|
SPCS_CLKACCY_1000PPM or SPCS_SAMPLERATE_48 or \
|
|
SPCS_CHANNELNUM_LEFT or SPCS_SOURCENUM_UNSPEC or \
|
|
SPCS_GENERATIONSTATUS or 0x00001200 or \
|
|
0x00000000 or SPCS_EMPHASIS_NONE or SPCS_COPYRIGHT
|
|
stdcall ptr_write, SPCS1, 0, \
|
|
SPCS_CLKACCY_1000PPM or SPCS_SAMPLERATE_48 or \
|
|
SPCS_CHANNELNUM_LEFT or SPCS_SOURCENUM_UNSPEC or \
|
|
SPCS_GENERATIONSTATUS or 0x00001200 or \
|
|
0x00000000 or SPCS_EMPHASIS_NONE or SPCS_COPYRIGHT
|
|
stdcall ptr_write, SPCS2, 0, \
|
|
SPCS_CLKACCY_1000PPM or SPCS_SAMPLERATE_48 or \
|
|
SPCS_CHANNELNUM_LEFT or SPCS_SOURCENUM_UNSPEC or \
|
|
SPCS_GENERATIONSTATUS or 0x00001200 or \
|
|
0x00000000 or SPCS_EMPHASIS_NONE or SPCS_COPYRIGHT
|
|
|
|
stdcall ptr_write, SPDIF_SELECT, 0, 0x700 ; disable SPDIF
|
|
stdcall ptr_write, ROUTING, 0, 0x1003F ; routing
|
|
stdcall gpio_write, 0x1080 ; analog mode
|
|
|
|
mov eax, dword HCFG_LOCKSOUNDCACHE or HCFG_AUDIOENABLE
|
|
mov edx, HCFG
|
|
call [ctrl.ctrl_write32]
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc codec_read stdcall, reg:dword
|
|
stdcall ac97_read, dword [reg]
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc codec_write stdcall, reg:dword
|
|
stdcall ac97_write, dword [reg], eax
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc ac97_read stdcall, reg:dword
|
|
push edx
|
|
mov eax, dword [reg]
|
|
mov edx, AC97ADDRESS
|
|
call [ctrl.ctrl_write8]
|
|
|
|
mov edx, AC97DATA
|
|
call [ctrl.ctrl_read16]
|
|
and eax, 0xFFFF
|
|
pop edx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ac97_write stdcall, reg:dword, val:dword
|
|
push eax edx
|
|
mov eax, dword [reg]
|
|
mov edx, AC97ADDRESS
|
|
call [ctrl.ctrl_write8]
|
|
|
|
mov eax, dword [val]
|
|
mov edx, AC97DATA
|
|
call [ctrl.ctrl_write16]
|
|
pop edx eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ptr_read stdcall, reg:dword, chn:dword
|
|
push edx
|
|
mov eax, dword [reg]
|
|
shl eax, 16
|
|
or eax, dword [chn]
|
|
|
|
mov edx, PTR
|
|
call [ctrl.ctrl_write32]
|
|
|
|
mov edx, DATA
|
|
call [ctrl.ctrl_read32]
|
|
pop edx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ptr_write stdcall, reg:dword, chn:dword, data:dword
|
|
push eax edx
|
|
mov eax, dword [reg]
|
|
shl eax, 16
|
|
or eax, dword [chn]
|
|
|
|
mov edx, PTR
|
|
call [ctrl.ctrl_write32]
|
|
|
|
mov eax, dword [data]
|
|
mov edx, DATA
|
|
call [ctrl.ctrl_write32]
|
|
pop edx eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc intr_enable stdcall, intrenb:dword
|
|
push edx
|
|
mov edx, INTE
|
|
call [ctrl.ctrl_read32]
|
|
|
|
or eax, dword [intrenb]
|
|
mov edx, INTE
|
|
call [ctrl.ctrl_write32]
|
|
pop edx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc intr_disable stdcall, intrenb:dword
|
|
push eax ebx edx
|
|
mov edx, INTE
|
|
call [ctrl.ctrl_read32]
|
|
|
|
mov ebx, dword [intrenb]
|
|
xor ebx, -1
|
|
and eax, ebx
|
|
mov edx, INTE
|
|
call [ctrl.ctrl_write32]
|
|
pop edx ebx eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc gpio_write stdcall, value:dword
|
|
push eax edx
|
|
mov eax, dword [value]
|
|
mov edx, GPIO
|
|
call [ctrl.ctrl_write32]
|
|
pop edx eax
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
proc StallExec
|
|
push ecx
|
|
push edx
|
|
push ebx
|
|
push eax
|
|
|
|
mov ecx, CPU_FREQ
|
|
mul ecx
|
|
mov ebx, eax ;low
|
|
mov ecx, edx ;high
|
|
rdtsc
|
|
add ebx, eax
|
|
adc ecx, edx
|
|
@@:
|
|
rdtsc
|
|
sub eax, ebx
|
|
sbb edx, ecx
|
|
js @B
|
|
|
|
pop eax
|
|
pop ebx
|
|
pop edx
|
|
pop ecx
|
|
ret
|
|
endp
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
; CONTROLLER IO functions
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
align 4
|
|
proc codec_io_r16 ;Not used.
|
|
;mov edx, [ctrl.ctrl_io_base]
|
|
;in eax, dx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc codec_io_w16 ;Not used.
|
|
;mov edx, [ctrl.ctrl_io_base]
|
|
;out dx, eax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ctrl_io_r8
|
|
add edx, [ctrl.ctrl_io_base]
|
|
in al, dx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ctrl_io_r16
|
|
add edx, [ctrl.ctrl_io_base]
|
|
in ax, dx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ctrl_io_r32
|
|
add edx, [ctrl.ctrl_io_base]
|
|
in eax, dx
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ctrl_io_w8
|
|
add edx, [ctrl.ctrl_io_base]
|
|
out dx, al
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ctrl_io_w16
|
|
add edx, [ctrl.ctrl_io_base]
|
|
out dx, ax
|
|
ret
|
|
endp
|
|
|
|
align 4
|
|
proc ctrl_io_w32
|
|
add edx, [ctrl.ctrl_io_base]
|
|
out dx, eax
|
|
ret
|
|
endp
|
|
|
|
|
|
align 4
|
|
dword2str:
|
|
push eax ebx ecx
|
|
mov esi, hex_buff
|
|
mov ecx, -8
|
|
@@:
|
|
rol eax, 4
|
|
mov ebx, eax
|
|
and ebx, 0x0F
|
|
mov bl, [ebx+hexletters]
|
|
mov [8+esi+ecx], bl
|
|
inc ecx
|
|
jnz @B
|
|
pop ecx ebx eax
|
|
ret
|
|
|
|
hexletters db '0123456789ABCDEF'
|
|
hex_buff db 8 dup(0),13,10,0
|
|
|
|
|
|
include "codec.inc"
|
|
|
|
align 4
|
|
devices dd (CTRL_CT0200 shl 16)+VID_Creative,msg_CT_EMU10K1X,set_Creative
|
|
dd 0 ;terminator
|
|
|
|
|
|
version dd (5 shl 16) or (API_VERSION and 0xFFFF)
|
|
|
|
msg_CT_EMU10K1X db 'SB Live! Dell OEM', 13,10, 0
|
|
msg_Creative db 'Creative ', 0
|
|
|
|
szKernel db 'KERNEL', 0
|
|
sz_sound_srv db 'SOUND',0
|
|
|
|
msgInit db 'detect hardware...',13,10,0
|
|
msgFail db 'device not found',13,10,0
|
|
msgAttchIRQ db 'IRQ line not supported', 13,10, 0
|
|
msgInvIRQ db 'IRQ line not assigned or invalid', 13,10, 0
|
|
msgPlay db 'start play', 13,10,0
|
|
msgStop db 'stop play', 13,10,0
|
|
msgIRQ db 'AC97 IRQ', 13,10,0
|
|
;msgInitCtrl db 'init controller',13,10,0
|
|
;msgInitCodec db 'init codec',13,10,0
|
|
msgPrimBuff db 'create primary buffer ...',0
|
|
msgDone db 'done',13,10,0
|
|
msgRemap db 'Remap IRQ',13,10,0
|
|
;msgReg db 'set service handler',13,10,0
|
|
;msgOk db 'service installed',13,10,0
|
|
msgCold db 'cold reset',13,10,0
|
|
;msgWarm db 'warm reset',13,10,0
|
|
;msgWRFail db 'warm reset failed',13,10,0
|
|
msgCRFail db 'cold reset failed',13,10,0
|
|
;msgCFail db 'codec not ready',13,10,0
|
|
;msgCInvalid db 'codec is not valid',13,10,0 ;Asper
|
|
;msgResetOk db 'reset complete',13,10,0
|
|
;msgStatus db 'global status ',0
|
|
;msgControl db 'global control ',0
|
|
msgPciCmd db 'PCI command ',0
|
|
msgPciStat db 'PCI status ',0
|
|
msgPciSubsys db 'PCI subsystem ',0
|
|
msgCtrlIsaIo db 'controller io base ',0
|
|
;msgMixIsaIo db 'codec io base ',0
|
|
;msgCtrlMMIo db 'controller mmio base ',0
|
|
;msgMixMMIo db 'codec mmio base ',0
|
|
;msgIrqMap db 'AC97 irq map as ',0
|
|
|
|
section '.data' data readable writable align 16
|
|
|
|
pcmout_bdl rq 32
|
|
buff_list rd 32
|
|
|
|
codec CODEC
|
|
ctrl AC_CNTRL
|