forked from KolibriOS/kolibrios
301 lines
7.0 KiB
C
301 lines
7.0 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <linux/i2c.h>
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//#include <linux/slab.h>
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#include "drmP.h"
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#include "drm.h"
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#include "drm_crtc.h"
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#include "drm_crtc_helper.h"
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#include "intel_drv.h"
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//#include "i915_drm.h"
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#include "i915_drv.h"
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#include "drm_dp_helper.h"
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#define DP_LINK_STATUS_SIZE 6
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#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
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#define DP_LINK_CONFIGURATION_SIZE 9
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struct intel_dp {
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struct intel_encoder base;
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uint32_t output_reg;
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uint32_t DP;
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uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
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bool has_audio;
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int force_audio;
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uint32_t color_range;
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int dpms_mode;
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uint8_t link_bw;
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uint8_t lane_count;
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uint8_t dpcd[8];
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struct i2c_adapter adapter;
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struct i2c_algo_dp_aux_data algo;
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bool is_pch_edp;
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uint8_t train_set[4];
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uint8_t link_status[DP_LINK_STATUS_SIZE];
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};
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/**
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* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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* @intel_dp: DP struct
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*
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* If a CPU or PCH DP output is attached to an eDP panel, this function
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* will return true, and false otherwise.
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*/
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static bool is_edp(struct intel_dp *intel_dp)
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{
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return intel_dp->base.type == INTEL_OUTPUT_EDP;
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}
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/**
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* is_pch_edp - is the port on the PCH and attached to an eDP panel?
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* @intel_dp: DP struct
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*
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* Returns true if the given DP struct corresponds to a PCH DP port attached
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* to an eDP panel, false otherwise. Helpful for determining whether we
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* may need FDI resources for a given DP output or not.
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*/
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static bool is_pch_edp(struct intel_dp *intel_dp)
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{
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return intel_dp->is_pch_edp;
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}
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static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct intel_dp, base.base);
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}
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/**
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* intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
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* @encoder: DRM encoder
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*
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* Return true if @encoder corresponds to a PCH attached eDP panel. Needed
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* by intel_display.c.
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*/
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bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
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{
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struct intel_dp *intel_dp;
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if (!encoder)
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return false;
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intel_dp = enc_to_intel_dp(encoder);
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return is_pch_edp(intel_dp);
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}
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void
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intel_edp_link_config (struct intel_encoder *intel_encoder,
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int *lane_num, int *link_bw)
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{
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struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
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*lane_num = intel_dp->lane_count;
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if (intel_dp->link_bw == DP_LINK_BW_1_62)
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*link_bw = 162000;
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else if (intel_dp->link_bw == DP_LINK_BW_2_7)
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*link_bw = 270000;
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}
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struct intel_dp_m_n {
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uint32_t tu;
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uint32_t gmch_m;
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uint32_t gmch_n;
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uint32_t link_m;
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uint32_t link_n;
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};
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static void
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intel_reduce_ratio(uint32_t *num, uint32_t *den)
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{
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while (*num > 0xffffff || *den > 0xffffff) {
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*num >>= 1;
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*den >>= 1;
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}
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}
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static void
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intel_dp_compute_m_n(int bpp,
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int nlanes,
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int pixel_clock,
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int link_clock,
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struct intel_dp_m_n *m_n)
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{
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m_n->tu = 64;
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m_n->gmch_m = (pixel_clock * bpp) >> 3;
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m_n->gmch_n = link_clock * nlanes;
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intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
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m_n->link_m = pixel_clock;
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m_n->link_n = link_clock;
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intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
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}
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void
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intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_encoder *encoder;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int lane_count = 4;
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struct intel_dp_m_n m_n;
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int pipe = intel_crtc->pipe;
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/*
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* Find the lane count in the intel_encoder private
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*/
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list_for_each_entry(encoder, &mode_config->encoder_list, head) {
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struct intel_dp *intel_dp;
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if (encoder->crtc != crtc)
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continue;
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intel_dp = enc_to_intel_dp(encoder);
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if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
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lane_count = intel_dp->lane_count;
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break;
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} else if (is_edp(intel_dp)) {
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lane_count = dev_priv->edp.lanes;
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break;
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}
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}
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/*
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* Compute the GMCH and Link ratios. The '3' here is
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* the number of bytes_per_pixel post-LUT, which we always
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* set up for 8-bits of R/G/B, or 3 bytes total.
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*/
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intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
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mode->clock, adjusted_mode->clock, &m_n);
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if (HAS_PCH_SPLIT(dev)) {
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I915_WRITE(TRANSDATA_M1(pipe),
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((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
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m_n.gmch_m);
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I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
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I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
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I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
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} else {
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I915_WRITE(PIPE_GMCH_DATA_M(pipe),
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((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
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m_n.gmch_m);
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I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
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I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
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I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
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}
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}
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/* Return which DP Port should be selected for Transcoder DP control */
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int
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intel_trans_dp_port_sel (struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_encoder *encoder;
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list_for_each_entry(encoder, &mode_config->encoder_list, head) {
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struct intel_dp *intel_dp;
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if (encoder->crtc != crtc)
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continue;
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intel_dp = enc_to_intel_dp(encoder);
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if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
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return intel_dp->output_reg;
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}
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return -1;
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}
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