forked from KolibriOS/kolibrios
1184 lines
35 KiB
C
1184 lines
35 KiB
C
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#include <ddk.h>
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#include <linux/errno.h>
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#include <mutex.h>
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#include <pci.h>
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#include <syscall.h>
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LIST_HEAD(pci_root_buses);
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#define IO_SPACE_LIMIT 0xffff
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#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
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#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
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#define CARDBUS_RESERVE_BUSNR 3
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static int pcibios_assign_all_busses(void)
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{
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return 0;
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};
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/**
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* pci_ari_enabled - query ARI forwarding status
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* @bus: the PCI bus
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*
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* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
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*/
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static inline int pci_ari_enabled(struct pci_bus *bus)
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{
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return bus->self && bus->self->ari_enabled;
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}
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/*
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* Translate the low bits of the PCI base
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* to the resource type
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*/
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static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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{
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if (flags & PCI_BASE_ADDRESS_SPACE_IO)
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return IORESOURCE_IO;
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if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
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return IORESOURCE_MEM | IORESOURCE_PREFETCH;
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return IORESOURCE_MEM;
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}
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static u64 pci_size(u64 base, u64 maxbase, u64 mask)
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{
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u64 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
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{
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if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
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return pci_bar_io;
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}
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res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
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if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
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return pci_bar_mem64;
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return pci_bar_mem32;
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}
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/**
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* pci_read_base - read a PCI BAR
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* @dev: the PCI device
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* @type: type of the BAR
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* @res: resource buffer to be filled in
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* @pos: BAR position in the config space
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*
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* Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
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*/
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int pos)
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{
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u32 l, sz, mask;
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u16 orig_cmd;
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mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
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if (!dev->mmio_always_on) {
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pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
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pci_write_config_word(dev, PCI_COMMAND,
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orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
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}
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res->name = pci_name(dev);
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pci_read_config_dword(dev, pos, &l);
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pci_write_config_dword(dev, pos, l | mask);
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pci_read_config_dword(dev, pos, &sz);
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pci_write_config_dword(dev, pos, l);
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if (!dev->mmio_always_on)
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pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
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/*
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* All bits set in sz means the device isn't working properly.
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* If the BAR isn't implemented, all bits must be 0. If it's a
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* memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
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* 1 must be clear.
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*/
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if (!sz || sz == 0xffffffff)
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goto fail;
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/*
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* I don't know how l can have all bits set. Copied from old code.
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* Maybe it fixes a bug on some ancient platform.
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*/
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if (l == 0xffffffff)
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l = 0;
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if (type == pci_bar_unknown) {
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type = decode_bar(res, l);
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res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
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if (type == pci_bar_io) {
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l &= PCI_BASE_ADDRESS_IO_MASK;
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mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
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} else {
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l &= PCI_BASE_ADDRESS_MEM_MASK;
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mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
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}
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} else {
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res->flags |= (l & IORESOURCE_ROM_ENABLE);
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l &= PCI_ROM_ADDRESS_MASK;
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mask = (u32)PCI_ROM_ADDRESS_MASK;
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}
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if (type == pci_bar_mem64) {
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u64 l64 = l;
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u64 sz64 = sz;
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u64 mask64 = mask | (u64)~0 << 32;
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pci_read_config_dword(dev, pos + 4, &l);
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pci_write_config_dword(dev, pos + 4, ~0);
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pci_read_config_dword(dev, pos + 4, &sz);
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pci_write_config_dword(dev, pos + 4, l);
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l64 |= ((u64)l << 32);
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sz64 |= ((u64)sz << 32);
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sz64 = pci_size(l64, sz64, mask64);
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if (!sz64)
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goto fail;
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if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
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dbgprintf("%s reg %x: can't handle 64-bit BAR\n",
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__FUNCTION__, pos);
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goto fail;
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}
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res->flags |= IORESOURCE_MEM_64;
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if ((sizeof(resource_size_t) < 8) && l) {
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/* Address above 32-bit boundary; disable the BAR */
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pci_write_config_dword(dev, pos, 0);
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pci_write_config_dword(dev, pos + 4, 0);
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res->start = 0;
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res->end = sz64;
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} else {
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res->start = l64;
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res->end = l64 + sz64;
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dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
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}
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} else {
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sz = pci_size(l, sz, mask);
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if (!sz)
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goto fail;
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res->start = l;
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res->end = l + sz;
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dbgprintf("%s reg %x: %pR\n", __FUNCTION__, pos, res);
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}
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out:
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return (type == pci_bar_mem64) ? 1 : 0;
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fail:
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res->flags = 0;
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goto out;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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unsigned int pos, reg;
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for (pos = 0; pos < howmany; pos++) {
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struct resource *res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
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}
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if (rom) {
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struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
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dev->rom_base_reg = rom;
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res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
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IORESOURCE_SIZEALIGN;
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__pci_read_base(dev, pci_bar_mem32, res, rom);
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}
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}
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#if 0
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void pci_read_bridge_bases(struct pci_bus *child)
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{
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struct pci_dev *dev = child->self;
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struct resource *res;
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int i;
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if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
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return;
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dbgprintf("PCI bridge to [bus %02x-%02x]%s\n",
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child->secondary, child->subordinate,
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dev->transparent ? " (subtractive decode)" : "");
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pci_bus_remove_resources(child);
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for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
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child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
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pci_read_bridge_io(child);
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pci_read_bridge_mmio(child);
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pci_read_bridge_mmio_pref(child);
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if (dev->transparent) {
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pci_bus_for_each_resource(child->parent, res, i) {
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if (res) {
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pci_bus_add_resource(child, res,
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PCI_SUBTRACTIVE_DECODE);
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dbgprintf(" bridge window %pR (subtractive decode)\n", res);
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}
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}
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}
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}
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#endif
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static struct pci_bus * pci_alloc_bus(void)
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{
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struct pci_bus *b;
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b = kzalloc(sizeof(*b), GFP_KERNEL);
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if (b) {
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INIT_LIST_HEAD(&b->node);
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INIT_LIST_HEAD(&b->children);
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INIT_LIST_HEAD(&b->devices);
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INIT_LIST_HEAD(&b->slots);
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INIT_LIST_HEAD(&b->resources);
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// b->max_bus_speed = PCI_SPEED_UNKNOWN;
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// b->cur_bus_speed = PCI_SPEED_UNKNOWN;
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}
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return b;
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}
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#if 0
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static unsigned char pcix_bus_speed[] = {
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PCI_SPEED_UNKNOWN, /* 0 */
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PCI_SPEED_66MHz_PCIX, /* 1 */
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PCI_SPEED_100MHz_PCIX, /* 2 */
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PCI_SPEED_133MHz_PCIX, /* 3 */
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PCI_SPEED_UNKNOWN, /* 4 */
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PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
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PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
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PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
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PCI_SPEED_UNKNOWN, /* 8 */
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PCI_SPEED_66MHz_PCIX_266, /* 9 */
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PCI_SPEED_100MHz_PCIX_266, /* A */
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PCI_SPEED_133MHz_PCIX_266, /* B */
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PCI_SPEED_UNKNOWN, /* C */
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PCI_SPEED_66MHz_PCIX_533, /* D */
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PCI_SPEED_100MHz_PCIX_533, /* E */
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PCI_SPEED_133MHz_PCIX_533 /* F */
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};
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static unsigned char pcie_link_speed[] = {
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PCI_SPEED_UNKNOWN, /* 0 */
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PCIE_SPEED_2_5GT, /* 1 */
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PCIE_SPEED_5_0GT, /* 2 */
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PCIE_SPEED_8_0GT, /* 3 */
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PCI_SPEED_UNKNOWN, /* 4 */
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PCI_SPEED_UNKNOWN, /* 5 */
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PCI_SPEED_UNKNOWN, /* 6 */
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PCI_SPEED_UNKNOWN, /* 7 */
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PCI_SPEED_UNKNOWN, /* 8 */
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PCI_SPEED_UNKNOWN, /* 9 */
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PCI_SPEED_UNKNOWN, /* A */
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PCI_SPEED_UNKNOWN, /* B */
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PCI_SPEED_UNKNOWN, /* C */
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PCI_SPEED_UNKNOWN, /* D */
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PCI_SPEED_UNKNOWN, /* E */
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PCI_SPEED_UNKNOWN /* F */
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};
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static void pci_set_bus_speed(struct pci_bus *bus)
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{
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struct pci_dev *bridge = bus->self;
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int pos;
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pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
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if (!pos)
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pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
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if (pos) {
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u32 agpstat, agpcmd;
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pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
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bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
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pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
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bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
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}
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pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
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if (pos) {
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u16 status;
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enum pci_bus_speed max;
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pci_read_config_word(bridge, pos + 2, &status);
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if (status & 0x8000) {
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max = PCI_SPEED_133MHz_PCIX_533;
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} else if (status & 0x4000) {
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max = PCI_SPEED_133MHz_PCIX_266;
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} else if (status & 0x0002) {
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if (((status >> 12) & 0x3) == 2) {
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max = PCI_SPEED_133MHz_PCIX_ECC;
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} else {
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max = PCI_SPEED_133MHz_PCIX;
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}
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} else {
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max = PCI_SPEED_66MHz_PCIX;
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}
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bus->max_bus_speed = max;
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bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
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return;
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}
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pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
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if (pos) {
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u32 linkcap;
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u16 linksta;
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pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
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bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
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pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
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pcie_update_link_speed(bus, linksta);
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}
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}
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#endif
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static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
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struct pci_dev *bridge, int busnr)
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{
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struct pci_bus *child;
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int i;
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/*
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* Allocate a new bus, and inherit stuff from the parent..
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*/
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child = pci_alloc_bus();
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if (!child)
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return NULL;
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child->parent = parent;
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child->ops = parent->ops;
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child->sysdata = parent->sysdata;
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child->bus_flags = parent->bus_flags;
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/* initialize some portions of the bus device, but don't register it
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* now as the parent is not properly set up yet. This device will get
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* registered later in pci_bus_add_devices()
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*/
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// child->dev.class = &pcibus_class;
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// dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
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/*
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* Set up the primary, secondary and subordinate
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* bus numbers.
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*/
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child->number = child->secondary = busnr;
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child->primary = parent->secondary;
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child->subordinate = 0xff;
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if (!bridge)
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return child;
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child->self = bridge;
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// child->bridge = get_device(&bridge->dev);
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// pci_set_bus_speed(child);
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/* Set up default resource pointers and names.. */
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for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
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child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
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child->resource[i]->name = child->name;
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}
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bridge->subordinate = child;
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return child;
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}
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struct pci_bus* pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
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{
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struct pci_bus *child;
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child = pci_alloc_child_bus(parent, dev, busnr);
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if (child) {
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// down_write(&pci_bus_sem);
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list_add_tail(&child->node, &parent->children);
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// up_write(&pci_bus_sem);
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}
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return child;
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}
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|
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static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
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{
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struct pci_bus *parent = child->parent;
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/* Attempts to fix that up are really dangerous unless
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we're going to re-assign all bus numbers. */
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if (!pcibios_assign_all_busses())
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return;
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while (parent->parent && parent->subordinate < max) {
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parent->subordinate = max;
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pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
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parent = parent->parent;
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}
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}
|
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|
|
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/*
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* If it's a bridge, configure it and scan the bus behind it.
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* For CardBus bridges, we don't scan behind as the devices will
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* be handled by the bridge driver itself.
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*
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* We need to process bridges in two passes -- first we scan those
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* already configured by the BIOS and after we are done with all of
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* them, we proceed to assigning numbers to the remaining buses in
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* order to avoid overlaps between old and new bus numbers.
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*/
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int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
|
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{
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struct pci_bus *child;
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int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
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u32 buses, i, j = 0;
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u16 bctl;
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u8 primary, secondary, subordinate;
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int broken = 0;
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pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
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primary = buses & 0xFF;
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secondary = (buses >> 8) & 0xFF;
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subordinate = (buses >> 16) & 0xFF;
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|
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dbgprintf("scanning [bus %02x-%02x] behind bridge, pass %d\n",
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secondary, subordinate, pass);
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|
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/* Check if setup is sensible at all */
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if (!pass &&
|
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(primary != bus->number || secondary <= bus->number)) {
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dbgprintf("bus configuration invalid, reconfiguring\n");
|
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broken = 1;
|
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}
|
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|
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/* Disable MasterAbortMode during probing to avoid reporting
|
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of bus errors (in some architectures) */
|
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
|
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
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bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
|
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|
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if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
|
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!is_cardbus && !broken) {
|
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unsigned int cmax;
|
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/*
|
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* Bus already configured by firmware, process it in the first
|
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* pass and just note the configuration.
|
|
*/
|
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if (pass)
|
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goto out;
|
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|
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/*
|
|
* If we already got to this bus through a different bridge,
|
|
* don't re-add it. This can happen with the i450NX chipset.
|
|
*
|
|
* However, we continue to descend down the hierarchy and
|
|
* scan remaining child buses.
|
|
*/
|
|
child = pci_find_bus(pci_domain_nr(bus), secondary);
|
|
if (!child) {
|
|
child = pci_add_new_bus(bus, dev, secondary);
|
|
if (!child)
|
|
goto out;
|
|
child->primary = primary;
|
|
child->subordinate = subordinate;
|
|
child->bridge_ctl = bctl;
|
|
}
|
|
|
|
cmax = pci_scan_child_bus(child);
|
|
if (cmax > max)
|
|
max = cmax;
|
|
if (child->subordinate > max)
|
|
max = child->subordinate;
|
|
} else {
|
|
/*
|
|
* We need to assign a number to this bus which we always
|
|
* do in the second pass.
|
|
*/
|
|
if (!pass) {
|
|
if (pcibios_assign_all_busses() || broken)
|
|
/* Temporarily disable forwarding of the
|
|
configuration cycles on all bridges in
|
|
this bus segment to avoid possible
|
|
conflicts in the second pass between two
|
|
bridges programmed with overlapping
|
|
bus ranges. */
|
|
pci_write_config_dword(dev, PCI_PRIMARY_BUS,
|
|
buses & ~0xffffff);
|
|
goto out;
|
|
}
|
|
|
|
/* Clear errors */
|
|
pci_write_config_word(dev, PCI_STATUS, 0xffff);
|
|
|
|
/* Prevent assigning a bus number that already exists.
|
|
* This can happen when a bridge is hot-plugged */
|
|
if (pci_find_bus(pci_domain_nr(bus), max+1))
|
|
goto out;
|
|
child = pci_add_new_bus(bus, dev, ++max);
|
|
buses = (buses & 0xff000000)
|
|
| ((unsigned int)(child->primary) << 0)
|
|
| ((unsigned int)(child->secondary) << 8)
|
|
| ((unsigned int)(child->subordinate) << 16);
|
|
|
|
/*
|
|
* yenta.c forces a secondary latency timer of 176.
|
|
* Copy that behaviour here.
|
|
*/
|
|
if (is_cardbus) {
|
|
buses &= ~0xff000000;
|
|
buses |= CARDBUS_LATENCY_TIMER << 24;
|
|
}
|
|
|
|
/*
|
|
* We need to blast all three values with a single write.
|
|
*/
|
|
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
|
|
|
|
if (!is_cardbus) {
|
|
child->bridge_ctl = bctl;
|
|
/*
|
|
* Adjust subordinate busnr in parent buses.
|
|
* We do this before scanning for children because
|
|
* some devices may not be detected if the bios
|
|
* was lazy.
|
|
*/
|
|
pci_fixup_parent_subordinate_busnr(child, max);
|
|
/* Now we can scan all subordinate buses... */
|
|
max = pci_scan_child_bus(child);
|
|
/*
|
|
* now fix it up again since we have found
|
|
* the real value of max.
|
|
*/
|
|
pci_fixup_parent_subordinate_busnr(child, max);
|
|
} else {
|
|
/*
|
|
* For CardBus bridges, we leave 4 bus numbers
|
|
* as cards with a PCI-to-PCI bridge can be
|
|
* inserted later.
|
|
*/
|
|
for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
|
|
struct pci_bus *parent = bus;
|
|
if (pci_find_bus(pci_domain_nr(bus),
|
|
max+i+1))
|
|
break;
|
|
while (parent->parent) {
|
|
if ((!pcibios_assign_all_busses()) &&
|
|
(parent->subordinate > max) &&
|
|
(parent->subordinate <= max+i)) {
|
|
j = 1;
|
|
}
|
|
parent = parent->parent;
|
|
}
|
|
if (j) {
|
|
/*
|
|
* Often, there are two cardbus bridges
|
|
* -- try to leave one valid bus number
|
|
* for each one.
|
|
*/
|
|
i /= 2;
|
|
break;
|
|
}
|
|
}
|
|
max += i;
|
|
pci_fixup_parent_subordinate_busnr(child, max);
|
|
}
|
|
/*
|
|
* Set the subordinate bus number to its real value.
|
|
*/
|
|
child->subordinate = max;
|
|
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
|
|
}
|
|
|
|
vsprintf(child->name,
|
|
(is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
|
|
pci_domain_nr(bus), child->number);
|
|
|
|
/* Has only triggered on CardBus, fixup is in yenta_socket */
|
|
while (bus->parent) {
|
|
if ((child->subordinate > bus->subordinate) ||
|
|
(child->number > bus->subordinate) ||
|
|
(child->number < bus->number) ||
|
|
(child->subordinate < bus->number)) {
|
|
dbgprintf("[bus %02x-%02x] %s "
|
|
"hidden behind%s bridge %s [bus %02x-%02x]\n",
|
|
child->number, child->subordinate,
|
|
(bus->number > child->subordinate &&
|
|
bus->subordinate < child->number) ?
|
|
"wholly" : "partially",
|
|
bus->self->transparent ? " transparent" : "",
|
|
"FIX BRIDGE NAME",
|
|
bus->number, bus->subordinate);
|
|
}
|
|
bus = bus->parent;
|
|
}
|
|
|
|
out:
|
|
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
|
|
|
|
return max;
|
|
}
|
|
|
|
void set_pcie_port_type(struct pci_dev *pdev)
|
|
{
|
|
int pos;
|
|
u16 reg16;
|
|
|
|
pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
|
|
if (!pos)
|
|
return;
|
|
pdev->is_pcie = 1;
|
|
pdev->pcie_cap = pos;
|
|
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
|
|
pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
|
|
}
|
|
|
|
void set_pcie_hotplug_bridge(struct pci_dev *pdev)
|
|
{
|
|
int pos;
|
|
u16 reg16;
|
|
u32 reg32;
|
|
|
|
pos = pci_pcie_cap(pdev);
|
|
if (!pos)
|
|
return;
|
|
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
|
|
if (!(reg16 & PCI_EXP_FLAGS_SLOT))
|
|
return;
|
|
pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
|
|
if (reg32 & PCI_EXP_SLTCAP_HPC)
|
|
pdev->is_hotplug_bridge = 1;
|
|
}
|
|
|
|
/*
|
|
* Read interrupt line and base address registers.
|
|
* The architecture-dependent code can tweak these, of course.
|
|
*/
|
|
static void pci_read_irq(struct pci_dev *dev)
|
|
{
|
|
unsigned char irq;
|
|
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
|
|
dev->pin = irq;
|
|
if (irq)
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
|
|
dev->irq = irq;
|
|
}
|
|
|
|
|
|
/**
|
|
* pci_setup_device - fill in class and map information of a device
|
|
* @dev: the device structure to fill
|
|
*
|
|
* Initialize the device structure with information about the device's
|
|
* vendor,class,memory and IO-space addresses,IRQ lines etc.
|
|
* Called at initialisation of the PCI subsystem and by CardBus services.
|
|
* Returns 0 on success and negative if unknown type of device (not normal,
|
|
* bridge or CardBus).
|
|
*/
|
|
int pci_setup_device(struct pci_dev *dev)
|
|
{
|
|
u32 class;
|
|
u8 hdr_type;
|
|
struct pci_slot *slot;
|
|
int pos = 0;
|
|
|
|
if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
|
|
return -EIO;
|
|
|
|
dev->sysdata = dev->bus->sysdata;
|
|
// dev->dev.parent = dev->bus->bridge;
|
|
// dev->dev.bus = &pci_bus_type;
|
|
dev->hdr_type = hdr_type & 0x7f;
|
|
dev->multifunction = !!(hdr_type & 0x80);
|
|
dev->error_state = pci_channel_io_normal;
|
|
set_pcie_port_type(dev);
|
|
|
|
list_for_each_entry(slot, &dev->bus->slots, list)
|
|
if (PCI_SLOT(dev->devfn) == slot->number)
|
|
dev->slot = slot;
|
|
|
|
/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
|
|
set this higher, assuming the system even supports it. */
|
|
dev->dma_mask = 0xffffffff;
|
|
|
|
// dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
|
|
// dev->bus->number, PCI_SLOT(dev->devfn),
|
|
// PCI_FUNC(dev->devfn));
|
|
|
|
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
|
|
dev->revision = class & 0xff;
|
|
class >>= 8; /* upper 3 bytes */
|
|
dev->class = class;
|
|
class >>= 8;
|
|
|
|
dbgprintf("found [%04x:%04x] class %06x header type %02x\n",
|
|
dev->vendor, dev->device, class, dev->hdr_type);
|
|
|
|
/* need to have dev->class ready */
|
|
dev->cfg_size = pci_cfg_space_size(dev);
|
|
|
|
/* "Unknown power state" */
|
|
dev->current_state = PCI_UNKNOWN;
|
|
|
|
/* Early fixups, before probing the BARs */
|
|
// pci_fixup_device(pci_fixup_early, dev);
|
|
/* device class may be changed after fixup */
|
|
class = dev->class >> 8;
|
|
|
|
switch (dev->hdr_type) { /* header type */
|
|
case PCI_HEADER_TYPE_NORMAL: /* standard header */
|
|
if (class == PCI_CLASS_BRIDGE_PCI)
|
|
goto bad;
|
|
pci_read_irq(dev);
|
|
pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
|
|
pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
|
|
pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
|
|
|
|
/*
|
|
* Do the ugly legacy mode stuff here rather than broken chip
|
|
* quirk code. Legacy mode ATA controllers have fixed
|
|
* addresses. These are not always echoed in BAR0-3, and
|
|
* BAR0-3 in a few cases contain junk!
|
|
*/
|
|
if (class == PCI_CLASS_STORAGE_IDE) {
|
|
u8 progif;
|
|
pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
|
|
if ((progif & 1) == 0) {
|
|
dev->resource[0].start = 0x1F0;
|
|
dev->resource[0].end = 0x1F7;
|
|
dev->resource[0].flags = LEGACY_IO_RESOURCE;
|
|
dev->resource[1].start = 0x3F6;
|
|
dev->resource[1].end = 0x3F6;
|
|
dev->resource[1].flags = LEGACY_IO_RESOURCE;
|
|
}
|
|
if ((progif & 4) == 0) {
|
|
dev->resource[2].start = 0x170;
|
|
dev->resource[2].end = 0x177;
|
|
dev->resource[2].flags = LEGACY_IO_RESOURCE;
|
|
dev->resource[3].start = 0x376;
|
|
dev->resource[3].end = 0x376;
|
|
dev->resource[3].flags = LEGACY_IO_RESOURCE;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
|
|
if (class != PCI_CLASS_BRIDGE_PCI)
|
|
goto bad;
|
|
/* The PCI-to-PCI bridge spec requires that subtractive
|
|
decoding (i.e. transparent) bridge must have programming
|
|
interface code of 0x01. */
|
|
pci_read_irq(dev);
|
|
dev->transparent = ((dev->class & 0xff) == 1);
|
|
pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
|
|
set_pcie_hotplug_bridge(dev);
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
|
|
if (pos) {
|
|
pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
|
|
pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
|
|
}
|
|
break;
|
|
|
|
case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
|
|
if (class != PCI_CLASS_BRIDGE_CARDBUS)
|
|
goto bad;
|
|
pci_read_irq(dev);
|
|
pci_read_bases(dev, 1, 0);
|
|
pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
|
|
pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
|
|
break;
|
|
|
|
default: /* unknown header */
|
|
dbgprintf("unknown header type %02x, "
|
|
"ignoring device\n", dev->hdr_type);
|
|
return -EIO;
|
|
|
|
bad:
|
|
dbgprintf("ignoring class %02x (doesn't match header "
|
|
"type %02x)\n", class, dev->hdr_type);
|
|
dev->class = PCI_CLASS_NOT_DEFINED;
|
|
}
|
|
|
|
/* We found a fine healthy device, go go go... */
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
struct pci_dev *alloc_pci_dev(void)
|
|
{
|
|
struct pci_dev *dev;
|
|
|
|
dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
|
|
if (!dev)
|
|
return NULL;
|
|
|
|
INIT_LIST_HEAD(&dev->bus_list);
|
|
|
|
return dev;
|
|
}
|
|
|
|
/*
|
|
* Read the config data for a PCI device, sanity-check it
|
|
* and fill in the dev structure...
|
|
*/
|
|
static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
|
|
{
|
|
struct pci_dev *dev;
|
|
u32 l;
|
|
int timeout = 10;
|
|
|
|
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
|
|
return NULL;
|
|
|
|
/* some broken boards return 0 or ~0 if a slot is empty: */
|
|
if (l == 0xffffffff || l == 0x00000000 ||
|
|
l == 0x0000ffff || l == 0xffff0000)
|
|
return NULL;
|
|
|
|
/* Configuration request Retry Status */
|
|
while (l == 0xffff0001) {
|
|
delay(timeout/10);
|
|
timeout *= 2;
|
|
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
|
|
return NULL;
|
|
/* Card hasn't responded in 60 seconds? Must be stuck. */
|
|
if (timeout > 60 * 1000) {
|
|
printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
|
|
"responding\n", pci_domain_nr(bus),
|
|
bus->number, PCI_SLOT(devfn),
|
|
PCI_FUNC(devfn));
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
dev = alloc_pci_dev();
|
|
if (!dev)
|
|
return NULL;
|
|
|
|
dev->bus = bus;
|
|
dev->devfn = devfn;
|
|
dev->vendor = l & 0xffff;
|
|
dev->device = (l >> 16) & 0xffff;
|
|
|
|
if (pci_setup_device(dev)) {
|
|
kfree(dev);
|
|
return NULL;
|
|
}
|
|
|
|
return dev;
|
|
}
|
|
|
|
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
|
|
{
|
|
// device_initialize(&dev->dev);
|
|
// dev->dev.release = pci_release_dev;
|
|
// pci_dev_get(dev);
|
|
|
|
// dev->dev.dma_mask = &dev->dma_mask;
|
|
// dev->dev.dma_parms = &dev->dma_parms;
|
|
// dev->dev.coherent_dma_mask = 0xffffffffull;
|
|
|
|
// pci_set_dma_max_seg_size(dev, 65536);
|
|
// pci_set_dma_seg_boundary(dev, 0xffffffff);
|
|
|
|
/* Fix up broken headers */
|
|
// pci_fixup_device(pci_fixup_header, dev);
|
|
|
|
/* Clear the state_saved flag. */
|
|
dev->state_saved = false;
|
|
|
|
/* Initialize various capabilities */
|
|
// pci_init_capabilities(dev);
|
|
|
|
/*
|
|
* Add the device to our list of discovered devices
|
|
* and the bus list for fixup functions, etc.
|
|
*/
|
|
// down_write(&pci_bus_sem);
|
|
list_add_tail(&dev->bus_list, &bus->devices);
|
|
// up_write(&pci_bus_sem);
|
|
}
|
|
|
|
struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn)
|
|
{
|
|
struct pci_dev *dev;
|
|
|
|
dev = pci_get_slot(bus, devfn);
|
|
if (dev) {
|
|
// pci_dev_put(dev);
|
|
return dev;
|
|
}
|
|
|
|
dev = pci_scan_device(bus, devfn);
|
|
if (!dev)
|
|
return NULL;
|
|
|
|
pci_device_add(dev, bus);
|
|
|
|
return dev;
|
|
}
|
|
|
|
static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
|
|
{
|
|
u16 cap;
|
|
unsigned pos, next_fn;
|
|
|
|
if (!dev)
|
|
return 0;
|
|
|
|
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
|
|
if (!pos)
|
|
return 0;
|
|
pci_read_config_word(dev, pos + 4, &cap);
|
|
next_fn = cap >> 8;
|
|
if (next_fn <= fn)
|
|
return 0;
|
|
return next_fn;
|
|
}
|
|
|
|
static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
|
|
{
|
|
return (fn + 1) % 8;
|
|
}
|
|
|
|
static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int only_one_child(struct pci_bus *bus)
|
|
{
|
|
struct pci_dev *parent = bus->self;
|
|
if (!parent || !pci_is_pcie(parent))
|
|
return 0;
|
|
if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* pci_scan_slot - scan a PCI slot on a bus for devices.
|
|
* @bus: PCI bus to scan
|
|
* @devfn: slot number to scan (must have zero function.)
|
|
*
|
|
* Scan a PCI slot on the specified PCI bus for devices, adding
|
|
* discovered devices to the @bus->devices list. New devices
|
|
* will not have is_added set.
|
|
*
|
|
* Returns the number of new devices found.
|
|
*/
|
|
int pci_scan_slot(struct pci_bus *bus, int devfn)
|
|
{
|
|
unsigned fn, nr = 0;
|
|
struct pci_dev *dev;
|
|
unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
|
|
|
|
if (only_one_child(bus) && (devfn > 0))
|
|
return 0; /* Already scanned the entire slot */
|
|
|
|
dev = pci_scan_single_device(bus, devfn);
|
|
if (!dev)
|
|
return 0;
|
|
if (!dev->is_added)
|
|
nr++;
|
|
|
|
if (pci_ari_enabled(bus))
|
|
next_fn = next_ari_fn;
|
|
else if (dev->multifunction)
|
|
next_fn = next_trad_fn;
|
|
|
|
for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
|
|
dev = pci_scan_single_device(bus, devfn + fn);
|
|
if (dev) {
|
|
if (!dev->is_added)
|
|
nr++;
|
|
dev->multifunction = 1;
|
|
}
|
|
}
|
|
|
|
/* only one slot has pcie device */
|
|
// if (bus->self && nr)
|
|
// pcie_aspm_init_link_state(bus->self);
|
|
|
|
return nr;
|
|
}
|
|
|
|
|
|
unsigned int pci_scan_child_bus(struct pci_bus *bus)
|
|
{
|
|
unsigned int devfn, pass, max = bus->secondary;
|
|
struct pci_dev *dev;
|
|
|
|
dbgprintf("scanning bus\n");
|
|
|
|
/* Go find them, Rover! */
|
|
for (devfn = 0; devfn < 0x100; devfn += 8)
|
|
pci_scan_slot(bus, devfn);
|
|
|
|
/* Reserve buses for SR-IOV capability. */
|
|
max += pci_iov_bus_range(bus);
|
|
|
|
/*
|
|
* After performing arch-dependent fixup of the bus, look behind
|
|
* all PCI-to-PCI bridges on this bus.
|
|
*/
|
|
if (!bus->is_added) {
|
|
dbgprintf("fixups for bus\n");
|
|
// pcibios_fixup_bus(bus);
|
|
if (pci_is_root_bus(bus))
|
|
bus->is_added = 1;
|
|
}
|
|
|
|
for (pass=0; pass < 2; pass++)
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
|
|
dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
|
|
max = pci_scan_bridge(bus, dev, max, pass);
|
|
}
|
|
|
|
/*
|
|
* We've scanned the bus and so we know all about what's on
|
|
* the other side of any bridges that may be on this bus plus
|
|
* any devices.
|
|
*
|
|
* Return how far we've got finding sub-buses.
|
|
*/
|
|
dbgprintf("bus scan returning with max=%02x\n", max);
|
|
return max;
|
|
}
|
|
|
|
/**
|
|
* pci_cfg_space_size - get the configuration space size of the PCI device.
|
|
* @dev: PCI device
|
|
*
|
|
* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
|
|
* have 4096 bytes. Even if the device is capable, that doesn't mean we can
|
|
* access it. Maybe we don't have a way to generate extended config space
|
|
* accesses, or the device is behind a reverse Express bridge. So we try
|
|
* reading the dword at 0x100 which must either be 0 or a valid extended
|
|
* capability header.
|
|
*/
|
|
int pci_cfg_space_size_ext(struct pci_dev *dev)
|
|
{
|
|
u32 status;
|
|
int pos = PCI_CFG_SPACE_SIZE;
|
|
|
|
if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
|
|
goto fail;
|
|
if (status == 0xffffffff)
|
|
goto fail;
|
|
|
|
return PCI_CFG_SPACE_EXP_SIZE;
|
|
|
|
fail:
|
|
return PCI_CFG_SPACE_SIZE;
|
|
}
|
|
|
|
int pci_cfg_space_size(struct pci_dev *dev)
|
|
{
|
|
int pos;
|
|
u32 status;
|
|
u16 class;
|
|
|
|
class = dev->class >> 8;
|
|
if (class == PCI_CLASS_BRIDGE_HOST)
|
|
return pci_cfg_space_size_ext(dev);
|
|
|
|
pos = pci_pcie_cap(dev);
|
|
if (!pos) {
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
if (!pos)
|
|
goto fail;
|
|
|
|
pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
|
|
if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
|
|
goto fail;
|
|
}
|
|
|
|
return pci_cfg_space_size_ext(dev);
|
|
|
|
fail:
|
|
return PCI_CFG_SPACE_SIZE;
|
|
}
|
|
|
|
|
|
|
|
struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata)
|
|
{
|
|
int error;
|
|
struct pci_bus *b, *b2;
|
|
|
|
b = pci_alloc_bus();
|
|
if (!b)
|
|
return NULL;
|
|
|
|
b->sysdata = sysdata;
|
|
b->ops = ops;
|
|
|
|
b2 = pci_find_bus(pci_domain_nr(b), bus);
|
|
if (b2) {
|
|
/* If we already got to this bus through a different bridge, ignore it */
|
|
dbgprintf("bus already known\n");
|
|
goto err_out;
|
|
}
|
|
|
|
// down_write(&pci_bus_sem);
|
|
list_add_tail(&b->node, &pci_root_buses);
|
|
// up_write(&pci_bus_sem);
|
|
|
|
b->number = b->secondary = bus;
|
|
b->resource[0] = &ioport_resource;
|
|
b->resource[1] = &iomem_resource;
|
|
|
|
return b;
|
|
|
|
err_out:
|
|
kfree(b);
|
|
return NULL;
|
|
}
|
|
|