forked from KolibriOS/kolibrios
ddk: update includes
git-svn-id: svn://kolibrios.org@2161 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
b5c6549818
commit
bc63e41160
@ -44,6 +44,7 @@
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#endif /* __alpha__ */
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <errno-base.h>
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#include <linux/kref.h>
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#include <linux/spinlock.h>
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@ -205,6 +205,8 @@ struct drm_display_info {
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enum subpixel_order subpixel_order;
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u32 color_formats;
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u8 cea_rev;
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char *raw_edid; /* if any */
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};
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@ -802,6 +804,7 @@ extern struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev,
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extern int drm_add_modes_noedid(struct drm_connector *connector,
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int hdisplay, int vdisplay);
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extern int drm_edid_header_is_valid(const u8 *raw_edid);
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extern bool drm_edid_is_valid(struct edid *edid);
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struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
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int hsize, int vsize, int fresh);
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@ -182,6 +182,7 @@
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{0x1002, 0x6750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6758, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6759, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x675F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6761, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6762, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
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@ -192,6 +193,7 @@
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{0x1002, 0x6767, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6768, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6770, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6778, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
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{0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
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@ -911,6 +911,7 @@ struct drm_radeon_cs {
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#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
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#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
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#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
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#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */
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struct drm_radeon_info {
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uint32_t request;
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@ -43,8 +43,8 @@
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*/
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struct mutex {
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/* 1: unlocked, 0: locked, negative: locked, possible waiters */
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atomic_t count;
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struct list_head wait_list;
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atomic_t count;
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};
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/*
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@ -58,8 +58,9 @@ struct mutex_waiter {
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#define __MUTEX_INITIALIZER(lockname) \
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{ .count = ATOMIC_INIT(1) \
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, .wait_list = LIST_HEAD_INIT(lockname.wait_list) }
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{ .wait_list = LIST_HEAD_INIT(lockname.wait_list), \
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.count = ATOMIC_INIT(1) \
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}
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#define DEFINE_MUTEX(mutexname) \
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struct mutex mutexname = __MUTEX_INITIALIZER(mutexname)
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@ -19,8 +19,13 @@
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#include <types.h>
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#include <list.h>
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#include <linux/pci_regs.h> /* The pci register defines */
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#include <ioport.h>
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#define PCI_CFG_SPACE_SIZE 256
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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#define PCI_ANY_ID (~0)
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@ -151,164 +156,6 @@
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#define PCI_CLASS_OTHERS 0xff
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/*
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_VENDOR_ID 0x000 /* 16 bits */
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#define PCI_DEVICE_ID 0x002 /* 16 bits */
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#define PCI_COMMAND 0x004 /* 16 bits */
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#define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */
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#define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */
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#define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */
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#define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */
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#define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */
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#define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */
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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
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#define PCI_STATUS 0x006 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */
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#define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
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#define PCI_REVISION_ID 0x08 /* Revision ID */
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f /* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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* Decoded size can be determined by writing a value of
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* 0xffffffff to the register, and reading it back. Only
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* 1 bits are decoded.
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*/
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
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#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
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#define PCI_BASE_ADDRESS_SPACE_IO 0x01
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#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
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#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
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#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
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#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
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#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
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#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
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#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
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#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
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/* bit 1 is reserved if address_space = 1 */
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#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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/* Header type 0 (normal devices) */
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#define PCI_CARDBUS_CIS 0x28
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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#define PCI_SUBSYSTEM_ID 0x2e
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
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#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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#define PCI_CB_SUBSYSTEM_ID 0x42
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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#define PCI_CB_CAPABILITY_LIST 0x14
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/* Capability lists */
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#define PCI_CAP_LIST_ID 0 /* Capability ID */
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#define PCI_CAP_ID_PM 0x01 /* Power Management */
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#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
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#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
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#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
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#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
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#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
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#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
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#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
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#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */
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#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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/* AGP registers */
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#define PCI_AGP_VERSION 2 /* BCD version number */
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#define PCI_AGP_RFU 3 /* Rest of capability flags */
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#define PCI_AGP_STATUS 4 /* Status register */
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#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
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#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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#define PCI_AGP_COMMAND 8 /* Control register */
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#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
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#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
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#define PCI_AGP_SIZEOF 12
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#define PCI_MAP_REG_START 0x10
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#define PCI_MAP_REG_END 0x28
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#define PCI_MAP_ROM_REG 0x30
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#define PCI_MAP_MEMORY 0x00000000
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#define PCI_MAP_IO 0x00000001
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#define PCI_MAP_MEMORY_TYPE 0x00000007
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#define PCI_MAP_IO_TYPE 0x00000003
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#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
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#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
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#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
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#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
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#define PCI_MAP_MEMORY_CACHABLE 0x00000008
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#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
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#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
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#define PCI_MAP_IO_ATTR_MASK 0x00000003
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@ -347,6 +194,14 @@
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#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
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#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8)
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/*
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* The PCI interface treats multi-function devices as independent
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* devices. The slot/function address of each device is encoded
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* in a single byte as follows:
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*
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* 7:3 = slot
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* 2:0 = function
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*/
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#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
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#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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#define PCI_FUNC(devfn) ((devfn) & 0x07)
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@ -361,124 +216,139 @@ pciTag(int busnum, int devnum, int funcnum)
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return(PCI_MAKE_TAG(busnum,devnum,funcnum));
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}
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struct resource
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{
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resource_size_t start;
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resource_size_t end;
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// const char *name;
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unsigned long flags;
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// struct resource *parent, *sibling, *child;
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/* pci_slot represents a physical slot */
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struct pci_slot {
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struct pci_bus *bus; /* The bus this slot is on */
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struct list_head list; /* node in list of slots on this bus */
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struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
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unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
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};
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/*
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* IO resources have these defined flags.
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*/
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#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */
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#define IORESOURCE_IO 0x00000100 /* Resource type */
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#define IORESOURCE_MEM 0x00000200
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#define IORESOURCE_IRQ 0x00000400
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#define IORESOURCE_DMA 0x00000800
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#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
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#define IORESOURCE_READONLY 0x00002000
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#define IORESOURCE_CACHEABLE 0x00004000
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#define IORESOURCE_RANGELENGTH 0x00008000
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#define IORESOURCE_SHADOWABLE 0x00010000
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#define IORESOURCE_BUS_HAS_VGA 0x00080000
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#define IORESOURCE_DISABLED 0x10000000
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#define IORESOURCE_UNSET 0x20000000
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#define IORESOURCE_AUTO 0x40000000
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#define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */
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/* ISA PnP IRQ specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_IRQ_HIGHEDGE (1<<0)
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#define IORESOURCE_IRQ_LOWEDGE (1<<1)
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#define IORESOURCE_IRQ_HIGHLEVEL (1<<2)
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#define IORESOURCE_IRQ_LOWLEVEL (1<<3)
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#define IORESOURCE_IRQ_SHAREABLE (1<<4)
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/* ISA PnP DMA specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_DMA_TYPE_MASK (3<<0)
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#define IORESOURCE_DMA_8BIT (0<<0)
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#define IORESOURCE_DMA_8AND16BIT (1<<0)
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#define IORESOURCE_DMA_16BIT (2<<0)
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#define IORESOURCE_DMA_MASTER (1<<2)
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#define IORESOURCE_DMA_BYTE (1<<3)
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#define IORESOURCE_DMA_WORD (1<<4)
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#define IORESOURCE_DMA_SPEED_MASK (3<<6)
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#define IORESOURCE_DMA_COMPATIBLE (0<<6)
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#define IORESOURCE_DMA_TYPEA (1<<6)
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#define IORESOURCE_DMA_TYPEB (2<<6)
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#define IORESOURCE_DMA_TYPEF (3<<6)
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/* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */
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#define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */
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#define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */
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#define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */
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#define IORESOURCE_MEM_TYPE_MASK (3<<3)
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#define IORESOURCE_MEM_8BIT (0<<3)
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#define IORESOURCE_MEM_16BIT (1<<3)
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#define IORESOURCE_MEM_8AND16BIT (2<<3)
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#define IORESOURCE_MEM_32BIT (3<<3)
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#define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */
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#define IORESOURCE_MEM_EXPANSIONROM (1<<6)
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/* PCI ROM control bits (IORESOURCE_BITS) */
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#define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
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#define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */
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#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */
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#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */
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/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
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#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
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/* File state for mmap()s on /proc/bus/pci/X/Y */
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enum pci_mmap_state {
|
||||
pci_mmap_io,
|
||||
pci_mmap_mem
|
||||
};
|
||||
|
||||
/* This defines the direction arg to the DMA mapping routines. */
|
||||
#define PCI_DMA_BIDIRECTIONAL 0
|
||||
#define PCI_DMA_TODEVICE 1
|
||||
#define PCI_DMA_FROMDEVICE 2
|
||||
#define PCI_DMA_NONE 3
|
||||
|
||||
/*
|
||||
* For PCI devices, the region numbers are assigned this way:
|
||||
*
|
||||
* 0-5 standard PCI regions
|
||||
* 6 expansion ROM
|
||||
* 7-10 bridges: address space assigned to buses behind the bridge
|
||||
*/
|
||||
enum {
|
||||
/* #0-5: standard PCI resources */
|
||||
PCI_STD_RESOURCES,
|
||||
PCI_STD_RESOURCE_END = 5,
|
||||
|
||||
#define PCI_ROM_RESOURCE 6
|
||||
#define PCI_BRIDGE_RESOURCES 7
|
||||
#define PCI_NUM_RESOURCES 11
|
||||
/* #6: expansion ROM resource */
|
||||
PCI_ROM_RESOURCE,
|
||||
|
||||
#ifndef PCI_BUS_NUM_RESOURCES
|
||||
#define PCI_BUS_NUM_RESOURCES 8
|
||||
/* device specific resources */
|
||||
#ifdef CONFIG_PCI_IOV
|
||||
PCI_IOV_RESOURCES,
|
||||
PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
|
||||
#endif
|
||||
|
||||
#define DEVICE_COUNT_RESOURCE 12
|
||||
/* resources assigned to buses behind the bridge */
|
||||
#define PCI_BRIDGE_RESOURCE_NUM 4
|
||||
|
||||
PCI_BRIDGE_RESOURCES,
|
||||
PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
|
||||
PCI_BRIDGE_RESOURCE_NUM - 1,
|
||||
|
||||
/* total resources associated with a PCI device */
|
||||
PCI_NUM_RESOURCES,
|
||||
|
||||
/* preserve this for compatibility */
|
||||
DEVICE_COUNT_RESOURCE
|
||||
};
|
||||
|
||||
typedef int __bitwise pci_power_t;
|
||||
|
||||
#define PCI_D0 ((pci_power_t __force) 0)
|
||||
#define PCI_D1 ((pci_power_t __force) 1)
|
||||
#define PCI_D2 ((pci_power_t __force) 2)
|
||||
#define PCI_D3hot ((pci_power_t __force) 3)
|
||||
#define PCI_D3cold ((pci_power_t __force) 4)
|
||||
#define PCI_UNKNOWN ((pci_power_t __force) 5)
|
||||
#define PCI_POWER_ERROR ((pci_power_t __force) -1)
|
||||
/** The pci_channel state describes connectivity between the CPU and
|
||||
* the pci device. If some PCI bus between here and the pci device
|
||||
* has crashed or locked up, this info is reflected here.
|
||||
*/
|
||||
typedef unsigned int __bitwise pci_channel_state_t;
|
||||
|
||||
enum pci_channel_state {
|
||||
/* I/O channel is in normal state */
|
||||
pci_channel_io_normal = (__force pci_channel_state_t) 1,
|
||||
|
||||
/* I/O to channel is blocked */
|
||||
pci_channel_io_frozen = (__force pci_channel_state_t) 2,
|
||||
|
||||
/* PCI card is dead */
|
||||
pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
|
||||
};
|
||||
typedef unsigned short __bitwise pci_bus_flags_t;
|
||||
enum pci_bus_flags {
|
||||
PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
|
||||
PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
|
||||
};
|
||||
|
||||
/* Based on the PCI Hotplug Spec, but some values are made up by us */
|
||||
enum pci_bus_speed {
|
||||
PCI_SPEED_33MHz = 0x00,
|
||||
PCI_SPEED_66MHz = 0x01,
|
||||
PCI_SPEED_66MHz_PCIX = 0x02,
|
||||
PCI_SPEED_100MHz_PCIX = 0x03,
|
||||
PCI_SPEED_133MHz_PCIX = 0x04,
|
||||
PCI_SPEED_66MHz_PCIX_ECC = 0x05,
|
||||
PCI_SPEED_100MHz_PCIX_ECC = 0x06,
|
||||
PCI_SPEED_133MHz_PCIX_ECC = 0x07,
|
||||
PCI_SPEED_66MHz_PCIX_266 = 0x09,
|
||||
PCI_SPEED_100MHz_PCIX_266 = 0x0a,
|
||||
PCI_SPEED_133MHz_PCIX_266 = 0x0b,
|
||||
AGP_UNKNOWN = 0x0c,
|
||||
AGP_1X = 0x0d,
|
||||
AGP_2X = 0x0e,
|
||||
AGP_4X = 0x0f,
|
||||
AGP_8X = 0x10,
|
||||
PCI_SPEED_66MHz_PCIX_533 = 0x11,
|
||||
PCI_SPEED_100MHz_PCIX_533 = 0x12,
|
||||
PCI_SPEED_133MHz_PCIX_533 = 0x13,
|
||||
PCIE_SPEED_2_5GT = 0x14,
|
||||
PCIE_SPEED_5_0GT = 0x15,
|
||||
PCIE_SPEED_8_0GT = 0x16,
|
||||
PCI_SPEED_UNKNOWN = 0xff,
|
||||
};
|
||||
|
||||
/*
|
||||
* The pci_dev structure is used to describe PCI devices.
|
||||
*/
|
||||
struct pci_dev {
|
||||
// struct list_head bus_list; /* node in per-bus list */
|
||||
// struct pci_bus *bus; /* bus this device is on */
|
||||
// struct pci_bus *subordinate; /* bus this device bridges to */
|
||||
struct list_head bus_list; /* node in per-bus list */
|
||||
struct pci_bus *bus; /* bus this device is on */
|
||||
struct pci_bus *subordinate; /* bus this device bridges to */
|
||||
|
||||
// void *sysdata; /* hook for sys-specific extension */
|
||||
void *sysdata; /* hook for sys-specific extension */
|
||||
// struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
|
||||
// struct pci_slot *slot; /* Physical slot this device is in */
|
||||
u32_t bus;
|
||||
u32_t devfn; /* encoded device & function index */
|
||||
u16_t vendor;
|
||||
u16_t device;
|
||||
u16_t subsystem_vendor;
|
||||
u16_t subsystem_device;
|
||||
u32_t class; /* 3 bytes: (base,sub,prog-if) */
|
||||
uint8_t revision; /* PCI revision, low byte of class word */
|
||||
uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */
|
||||
uint8_t pcie_type; /* PCI-E device/port type */
|
||||
uint8_t rom_base_reg; /* which config register controls the ROM */
|
||||
uint8_t pin; /* which interrupt pin this device uses */
|
||||
struct pci_slot *slot; /* Physical slot this device is in */
|
||||
u32_t busnr;
|
||||
unsigned int devfn; /* encoded device & function index */
|
||||
unsigned short vendor;
|
||||
unsigned short device;
|
||||
unsigned short subsystem_vendor;
|
||||
unsigned short subsystem_device;
|
||||
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
|
||||
u8 revision; /* PCI revision, low byte of class word */
|
||||
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
|
||||
u8 pcie_cap; /* PCI-E capability offset */
|
||||
u8 pcie_type; /* PCI-E device/port type */
|
||||
u8 rom_base_reg; /* which config register controls the ROM */
|
||||
u8 pin; /* which interrupt pin this device uses */
|
||||
|
||||
// struct pci_driver *driver; /* which driver has allocated this device */
|
||||
uint64_t dma_mask; /* Mask of the bits of bus address this
|
||||
@ -489,21 +359,27 @@ struct pci_dev {
|
||||
|
||||
// struct device_dma_parameters dma_parms;
|
||||
|
||||
// pci_power_t current_state; /* Current operating state. In ACPI-speak,
|
||||
// this is D0-D3, D0 being fully functional,
|
||||
// and D3 being off. */
|
||||
// int pm_cap; /* PM capability offset in the
|
||||
// configuration space */
|
||||
pci_power_t current_state; /* Current operating state. In ACPI-speak,
|
||||
this is D0-D3, D0 being fully functional,
|
||||
and D3 being off. */
|
||||
int pm_cap; /* PM capability offset in the
|
||||
configuration space */
|
||||
unsigned int pme_support:5; /* Bitmask of states from which PME#
|
||||
can be generated */
|
||||
unsigned int pme_interrupt:1;
|
||||
unsigned int d1_support:1; /* Low power state D1 is supported */
|
||||
unsigned int d2_support:1; /* Low power state D2 is supported */
|
||||
unsigned int no_d1d2:1; /* Only allow D0 and D3 */
|
||||
unsigned int mmio_always_on:1; /* disallow turning off io/mem
|
||||
decoding during bar sizing */
|
||||
unsigned int wakeup_prepared:1;
|
||||
unsigned int d3_delay; /* D3->D0 transition time in ms */
|
||||
|
||||
// pci_channel_state_t error_state; /* current connectivity state */
|
||||
|
||||
pci_channel_state_t error_state; /* current connectivity state */
|
||||
struct device dev; /* Generic device interface */
|
||||
|
||||
// int cfg_size; /* Size of configuration space */
|
||||
struct acpi_device *acpi_dev;
|
||||
int cfg_size; /* Size of configuration space */
|
||||
|
||||
/*
|
||||
* Instead of touching interrupt line and base address registers
|
||||
@ -511,6 +387,7 @@ struct pci_dev {
|
||||
*/
|
||||
unsigned int irq;
|
||||
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
|
||||
resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
|
||||
|
||||
/* These fields are used by common fixups */
|
||||
unsigned int transparent:1; /* Transparent PCI bridge */
|
||||
@ -524,12 +401,16 @@ struct pci_dev {
|
||||
unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
|
||||
unsigned int msi_enabled:1;
|
||||
unsigned int msix_enabled:1;
|
||||
unsigned int ari_enabled:1; /* ARI forwarding */
|
||||
unsigned int ari_enabled:1; /* ARI forwarding */
|
||||
unsigned int is_managed:1;
|
||||
unsigned int is_pcie:1;
|
||||
unsigned int is_pcie:1; /* Obsolete. Will be removed.
|
||||
Use pci_is_pcie() instead */
|
||||
unsigned int needs_freset:1; /* Dev requires fundamental reset */
|
||||
unsigned int state_saved:1;
|
||||
unsigned int is_physfn:1;
|
||||
unsigned int is_virtfn:1;
|
||||
unsigned int reset_fn:1;
|
||||
unsigned int is_hotplug_bridge:1;
|
||||
// pci_dev_flags_t dev_flags;
|
||||
// atomic_t enable_cnt; /* pci_enable_device has been called */
|
||||
|
||||
@ -553,6 +434,187 @@ struct pci_dev {
|
||||
pci_resource_start((dev), (bar)) + 1))
|
||||
|
||||
|
||||
struct pci_bus {
|
||||
struct list_head node; /* node in list of buses */
|
||||
struct pci_bus *parent; /* parent bus this bridge is on */
|
||||
struct list_head children; /* list of child buses */
|
||||
struct list_head devices; /* list of devices on this bus */
|
||||
struct pci_dev *self; /* bridge device as seen by parent */
|
||||
struct list_head slots; /* list of slots on this bus */
|
||||
struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
|
||||
struct list_head resources; /* address space routed to this bus */
|
||||
|
||||
struct pci_ops *ops; /* configuration access functions */
|
||||
void *sysdata; /* hook for sys-specific extension */
|
||||
struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
|
||||
|
||||
unsigned char number; /* bus number */
|
||||
unsigned char primary; /* number of primary bridge */
|
||||
unsigned char secondary; /* number of secondary bridge */
|
||||
unsigned char subordinate; /* max number of subordinate buses */
|
||||
unsigned char max_bus_speed; /* enum pci_bus_speed */
|
||||
unsigned char cur_bus_speed; /* enum pci_bus_speed */
|
||||
|
||||
char name[48];
|
||||
|
||||
unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
|
||||
pci_bus_flags_t bus_flags; /* Inherited by child busses */
|
||||
struct device *bridge;
|
||||
struct device dev;
|
||||
struct bin_attribute *legacy_io; /* legacy I/O for this bus */
|
||||
struct bin_attribute *legacy_mem; /* legacy mem */
|
||||
unsigned int is_added:1;
|
||||
};
|
||||
|
||||
|
||||
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
|
||||
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
|
||||
#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
|
||||
#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
|
||||
#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
|
||||
|
||||
|
||||
/* Low-level architecture-dependent routines */
|
||||
|
||||
struct pci_sysdata {
|
||||
int domain; /* PCI domain */
|
||||
int node; /* NUMA node */
|
||||
};
|
||||
|
||||
|
||||
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
|
||||
#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
|
||||
|
||||
/*
|
||||
* Returns true if the pci bus is root (behind host-pci bridge),
|
||||
* false otherwise
|
||||
*/
|
||||
static inline bool pci_is_root_bus(struct pci_bus *pbus)
|
||||
{
|
||||
return !(pbus->parent);
|
||||
}
|
||||
|
||||
struct pci_bus *
|
||||
pci_find_next_bus(const struct pci_bus *from);
|
||||
|
||||
|
||||
/*
|
||||
* Error values that may be returned by PCI functions.
|
||||
*/
|
||||
#define PCIBIOS_SUCCESSFUL 0x00
|
||||
#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
|
||||
#define PCIBIOS_BAD_VENDOR_ID 0x83
|
||||
#define PCIBIOS_DEVICE_NOT_FOUND 0x86
|
||||
#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
|
||||
#define PCIBIOS_SET_FAILED 0x88
|
||||
#define PCIBIOS_BUFFER_TOO_SMALL 0x89
|
||||
|
||||
/* Low-level architecture-dependent routines */
|
||||
|
||||
struct pci_ops {
|
||||
int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
|
||||
int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
|
||||
};
|
||||
|
||||
|
||||
enum pci_bar_type {
|
||||
pci_bar_unknown, /* Standard PCI BAR probe */
|
||||
pci_bar_io, /* An io port BAR */
|
||||
pci_bar_mem32, /* A 32-bit memory BAR */
|
||||
pci_bar_mem64, /* A 64-bit memory BAR */
|
||||
};
|
||||
|
||||
/*
|
||||
* PCI domain support. Sometimes called PCI segment (eg by ACPI),
|
||||
* a PCI domain is defined to be a set of PCI busses which share
|
||||
* configuration space.
|
||||
*/
|
||||
#ifdef CONFIG_PCI_DOMAINS
|
||||
extern int pci_domains_supported;
|
||||
#else
|
||||
enum { pci_domains_supported = 0 };
|
||||
static inline int pci_domain_nr(struct pci_bus *bus)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int pci_proc_domain(struct pci_bus *bus)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_PCI_DOMAINS */
|
||||
|
||||
/**
|
||||
* pci_pcie_cap - get the saved PCIe capability offset
|
||||
* @dev: PCI device
|
||||
*
|
||||
* PCIe capability offset is calculated at PCI device initialization
|
||||
* time and saved in the data structure. This function returns saved
|
||||
* PCIe capability offset. Using this instead of pci_find_capability()
|
||||
* reduces unnecessary search in the PCI configuration space. If you
|
||||
* need to calculate PCIe capability offset from raw device for some
|
||||
* reasons, please use pci_find_capability() instead.
|
||||
*/
|
||||
static inline int pci_pcie_cap(struct pci_dev *dev)
|
||||
{
|
||||
return dev->pcie_cap;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_is_pcie - check if the PCI device is PCI Express capable
|
||||
* @dev: PCI device
|
||||
*
|
||||
* Retrun true if the PCI device is PCI Express capable, false otherwise.
|
||||
*/
|
||||
static inline bool pci_is_pcie(struct pci_dev *dev)
|
||||
{
|
||||
return !!pci_pcie_cap(dev);
|
||||
}
|
||||
|
||||
static inline int pci_iov_init(struct pci_dev *dev)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline void pci_iov_release(struct pci_dev *dev)
|
||||
|
||||
{}
|
||||
|
||||
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
|
||||
enum pci_bar_type *type)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void pci_restore_iov_state(struct pci_dev *dev)
|
||||
{
|
||||
}
|
||||
static inline int pci_iov_bus_range(struct pci_bus *bus)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int pci_enable_ats(struct pci_dev *dev, int ps)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline void pci_disable_ats(struct pci_dev *dev)
|
||||
{
|
||||
}
|
||||
static inline int pci_ats_queue_depth(struct pci_dev *dev)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int pci_ats_enabled(struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pci_setup_device(struct pci_dev *dev);
|
||||
int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
|
||||
struct resource *res, unsigned int reg);
|
||||
int pci_resource_bar(struct pci_dev *dev, int resno,
|
||||
enum pci_bar_type *type);
|
||||
int pci_bus_add_child(struct pci_bus *bus);
|
||||
unsigned int pci_scan_child_bus(struct pci_bus *bus);
|
||||
|
||||
|
||||
typedef struct
|
||||
|
||||
@ -431,4 +431,6 @@ static inline void __SysMsgBoardStr(char *text)
|
||||
::"S" (text));
|
||||
};
|
||||
|
||||
#define rmb() asm volatile("lfence":::"memory")
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user