forked from KolibriOS/kolibrios
404 lines
11 KiB
C
404 lines
11 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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#include "r100d.h"
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#include "r420d.h"
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#include "r420_reg_safe.h"
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static void r420_set_reg_safe(struct radeon_device *rdev)
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{
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rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
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rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
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}
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int r420_mc_init(struct radeon_device *rdev)
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{
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int r;
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/* Setup GPU memory space */
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rdev->mc.vram_location = 0xFFFFFFFFUL;
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rdev->mc.gtt_location = 0xFFFFFFFFUL;
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if (rdev->flags & RADEON_IS_AGP) {
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r = radeon_agp_init(rdev);
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if (r) {
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radeon_agp_disable(rdev);
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} else {
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rdev->mc.gtt_location = rdev->mc.agp_base;
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}
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}
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r = radeon_mc_setup(rdev);
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if (r) {
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return r;
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}
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return 0;
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}
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void r420_pipes_init(struct radeon_device *rdev)
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{
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unsigned tmp;
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unsigned gb_pipe_select;
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unsigned num_pipes;
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/* GA_ENHANCE workaround TCL deadlock issue */
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WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
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/* add idle wait as per freedesktop.org bug 24041 */
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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/* get max number of pipes */
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gb_pipe_select = RREG32(0x402C);
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num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
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rdev->num_gb_pipes = num_pipes;
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tmp = 0;
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switch (num_pipes) {
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default:
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/* force to 1 pipe */
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num_pipes = 1;
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case 1:
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tmp = (0 << 1);
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break;
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case 2:
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tmp = (3 << 1);
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break;
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case 3:
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tmp = (6 << 1);
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break;
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case 4:
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tmp = (7 << 1);
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break;
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}
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WREG32(0x42C8, (1 << num_pipes) - 1);
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/* Sub pixel 1/12 so we can have 4K rendering according to doc */
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tmp |= (1 << 4) | (1 << 0);
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WREG32(0x4018, tmp);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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tmp = RREG32(0x170C);
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WREG32(0x170C, tmp | (1 << 31));
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WREG32(R300_RB2D_DSTCACHE_MODE,
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RREG32(R300_RB2D_DSTCACHE_MODE) |
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R300_DC_AUTOFLUSH_ENABLE |
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R300_DC_DC_DISABLE_IGNORE_PE);
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if (r100_gui_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait GUI idle while "
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"programming pipes. Bad things might happen.\n");
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}
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if (rdev->family == CHIP_RV530) {
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tmp = RREG32(RV530_GB_PIPE_SELECT2);
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if ((tmp & 3) == 3)
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rdev->num_z_pipes = 2;
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else
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rdev->num_z_pipes = 1;
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} else
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rdev->num_z_pipes = 1;
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DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
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rdev->num_gb_pipes, rdev->num_z_pipes);
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}
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u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
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{
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u32 r;
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WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
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r = RREG32(R_0001FC_MC_IND_DATA);
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return r;
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}
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void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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{
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WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
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S_0001F8_MC_IND_WR_EN(1));
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WREG32(R_0001FC_MC_IND_DATA, v);
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}
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static void r420_debugfs(struct radeon_device *rdev)
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{
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if (r100_debugfs_rbbm_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for RBBM !\n");
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}
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if (r420_debugfs_pipes_info_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for pipes !\n");
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}
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}
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static void r420_clock_resume(struct radeon_device *rdev)
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{
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u32 sclk_cntl;
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if (radeon_dynclks != -1 && radeon_dynclks)
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radeon_atom_set_clock_gating(rdev, 1);
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sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
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sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
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if (rdev->family == CHIP_R420)
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sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
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WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
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}
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static void r420_cp_errata_init(struct radeon_device *rdev)
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{
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/* RV410 and R420 can lock up if CP DMA to host memory happens
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* while the 2D engine is busy.
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*
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* The proper workaround is to queue a RESYNC at the beginning
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* of the CP init, apparently.
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*/
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radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
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radeon_ring_lock(rdev, 8);
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radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
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radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
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radeon_ring_write(rdev, 0xDEADBEEF);
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radeon_ring_unlock_commit(rdev);
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}
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static void r420_cp_errata_fini(struct radeon_device *rdev)
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{
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/* Catch the RESYNC we dispatched all the way back,
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* at the very beginning of the CP init.
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*/
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radeon_ring_lock(rdev, 8);
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radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
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radeon_ring_unlock_commit(rdev);
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radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
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}
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static int r420_startup(struct radeon_device *rdev)
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{
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int r;
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/* set common regs */
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r100_set_common_regs(rdev);
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/* program mc */
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r300_mc_program(rdev);
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/* Resume clock */
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r420_clock_resume(rdev);
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/* Initialize GART (initialize after TTM so we can allocate
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* memory through TTM but finalize after TTM) */
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_enable(rdev);
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if (r)
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return r;
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}
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if (rdev->flags & RADEON_IS_PCI) {
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r = r100_pci_gart_enable(rdev);
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if (r)
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return r;
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}
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r420_pipes_init(rdev);
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/* Enable IRQ */
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// r100_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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// r = r100_cp_init(rdev, 1024 * 1024);
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// if (r) {
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// dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
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// return r;
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// }
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// r = r100_wb_init(rdev);
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// if (r) {
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// dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
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// }
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// r = r100_ib_init(rdev);
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// if (r) {
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// dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
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// return r;
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// }
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return 0;
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}
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int r420_resume(struct radeon_device *rdev)
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{
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/* Make sur GART are not working */
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_disable(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_disable(rdev);
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/* Resume clock before doing reset */
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r420_clock_resume(rdev);
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* check if cards are posted or not */
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if (rdev->is_atom_bios) {
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atom_asic_init(rdev->mode_info.atom_context);
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} else {
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radeon_combios_asic_init(rdev->ddev);
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}
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/* Resume clock after posting */
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r420_clock_resume(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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return r420_startup(rdev);
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}
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int r420_init(struct radeon_device *rdev)
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{
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int r;
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/* Initialize scratch registers */
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radeon_scratch_init(rdev);
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/* Initialize surface registers */
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radeon_surface_init(rdev);
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/* TODO: disable VGA need to use VGA request */
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/* BIOS*/
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if (!radeon_get_bios(rdev)) {
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if (ASIC_IS_AVIVO(rdev))
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return -EINVAL;
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}
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if (rdev->is_atom_bios) {
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r = radeon_atombios_init(rdev);
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if (r) {
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return r;
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}
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} else {
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r = radeon_combios_init(rdev);
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if (r) {
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return r;
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}
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}
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/* Reset gpu before posting otherwise ATOM will enter infinite loop */
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if (radeon_gpu_reset(rdev)) {
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dev_warn(rdev->dev,
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"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
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RREG32(R_000E40_RBBM_STATUS),
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RREG32(R_0007C0_CP_STAT));
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}
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/* check if cards are posted or not */
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if (radeon_boot_test_post_card(rdev) == false)
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return -EINVAL;
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/* Initialize clocks */
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radeon_get_clock_info(rdev->ddev);
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/* Initialize power management */
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radeon_pm_init(rdev);
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/* Get vram informations */
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r300_vram_info(rdev);
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/* Initialize memory controller (also test AGP) */
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r = r420_mc_init(rdev);
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if (r) {
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return r;
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}
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r420_debugfs(rdev);
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/* Fence driver */
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// r = radeon_fence_driver_init(rdev);
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// if (r) {
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// return r;
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// }
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// r = radeon_irq_kms_init(rdev);
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// if (r) {
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// return r;
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// }
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/* Memory manager */
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r = radeon_bo_init(rdev);
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if (r) {
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return r;
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}
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if (rdev->family == CHIP_R420)
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r100_enable_bm(rdev);
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if (rdev->flags & RADEON_IS_PCIE) {
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r = rv370_pcie_gart_init(rdev);
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if (r)
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return r;
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}
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if (rdev->flags & RADEON_IS_PCI) {
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r = r100_pci_gart_init(rdev);
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if (r)
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return r;
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}
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r420_set_reg_safe(rdev);
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rdev->accel_working = true;
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r = r420_startup(rdev);
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if (r) {
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/* Somethings want wront with the accel init stop accel */
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dev_err(rdev->dev, "Disabling GPU acceleration\n");
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// r420_suspend(rdev);
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// r100_cp_fini(rdev);
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// r100_wb_fini(rdev);
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// r100_ib_fini(rdev);
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if (rdev->flags & RADEON_IS_PCIE)
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rv370_pcie_gart_fini(rdev);
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if (rdev->flags & RADEON_IS_PCI)
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r100_pci_gart_fini(rdev);
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// radeon_agp_fini(rdev);
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rdev->accel_working = false;
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}
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return 0;
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t tmp;
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tmp = RREG32(R400_GB_PIPE_SELECT);
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seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
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tmp = RREG32(R300_GB_TILE_CONFIG);
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seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
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tmp = RREG32(R300_DST_PIPE_CONFIG);
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seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
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return 0;
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}
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static struct drm_info_list r420_pipes_info_list[] = {
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{"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
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};
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#endif
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int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
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#else
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return 0;
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#endif
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}
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