forked from KolibriOS/kolibrios
578 lines
14 KiB
C
578 lines
14 KiB
C
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#include <assert.h>
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#include <stdlib.h>
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#include <memory.h>
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#include <intel_bufmgr.h>
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//#include "xf86.h"
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#include "uxa/intel.h"
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#include "i830_reg.h"
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#include "i965_reg.h"
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/* bring in brw structs */
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#include "brw_defines.h"
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#include "brw_structs.h"
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#include "i915_pciids.h"
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#include <pixlib2.h>
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#include <kos32sys.h>
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#define PictOpClear 0
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#define PictOpSrc 1
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#define PictOpDst 2
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#define PictOpOver 3
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#define PictOpOverReverse 4
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#define PictOpIn 5
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#define PictOpInReverse 6
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#define PictOpOut 7
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#define PictOpOutReverse 8
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#define PictOpAtop 9
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#define PictOpAtopReverse 10
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#define PictOpXor 11
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#define PictOpAdd 12
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#define PictOpSaturate 13
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#define PictOpMaximum 13
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static int tls_mask;
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intel_screen_private *driverPrivate;
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__LOCK_INIT_RECURSIVE(, __uxa_lock);
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#define DBG printf
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typedef struct
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{
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struct list entry;
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uint32_t width;
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uint32_t height;
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void *data;
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uint32_t pitch;
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drm_intel_bo *bo;
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uint32_t bo_size;
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uint32_t flags;
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}surface_t;
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#define to_surface(x) (surface_t*)((x)->handle)
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struct _Pixmap fb_pixmap;
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struct list sf_list;
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int uxa_update_fb(struct intel_screen_private *intel);
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int sna_create_mask()
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{
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return 0;
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};
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static void i830_done_composite(PixmapPtr dest)
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{
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intel_screen_private *intel = intel_get_screen_private();
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if (intel->vertex_flush)
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intel->vertex_flush(intel);
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// intel_debug_flush(scrn);
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}
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int sna_bitmap_from_handle(bitmap_t *bitmap, uint32_t handle)
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{
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struct intel_screen_private *intel = intel_get_screen_private();
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drm_intel_bo *bo;
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surface_t *sf;
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unsigned int size;
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bitmap->handle = 0;
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__lock_acquire_recursive(__uxa_lock);
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list_for_each_entry(sf, &sf_list, entry)
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{
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if (sf->bo->handle == handle)
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{
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bitmap->handle = (uint32_t)sf;
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break;
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}
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}
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__lock_release_recursive(__uxa_lock);
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if(bitmap->handle)
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return 0;
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sf = malloc(sizeof(*sf));
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if(sf == NULL)
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goto err_1;
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size = bitmap->pitch * bitmap->height;
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bo = bo_create_from_gem_handle(intel->bufmgr, size, handle);
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sf->width = bitmap->width;
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sf->height = bitmap->height;
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sf->data = NULL;
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sf->pitch = bitmap->pitch;
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sf->bo = bo;
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sf->bo_size = size;
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sf->flags = bitmap->flags;
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bitmap->handle = (uint32_t)sf;
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return 0;
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err_1:
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return -1;
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};
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void sna_set_bo_handle(bitmap_t *bitmap, int handle)
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{
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sna_bitmap_from_handle(bitmap, handle);
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};
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int sna_blit_tex(bitmap_t *bitmap, bool scale, int dst_x, int dst_y,
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int w, int h, int src_x, int src_y)
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{
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// DBG("%s\n", __FUNCTION__);
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struct _Pixmap pixSrc, pixMask;
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struct intel_pixmap privSrc;
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struct _Picture pictSrc, pictDst;
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struct intel_screen_private *intel = intel_get_screen_private();
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surface_t *sf = to_surface(bitmap);
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int winx, winy;
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char proc_info[1024];
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get_proc_info(proc_info);
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winx = *(uint32_t*)(proc_info+34);
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winy = *(uint32_t*)(proc_info+38);
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memset(&pixSrc, 0, sizeof(pixSrc));
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memset(&pixMask, 0, sizeof(pixMask));
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memset(&privSrc, 0, sizeof(pixSrc));
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memset(&pictSrc, 0, sizeof(pictSrc));
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memset(&pictDst, 0, sizeof(pictDst));
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pixSrc.drawable.bitsPerPixel = 32;
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pixSrc.drawable.width = sf->width;
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pixSrc.drawable.height = sf->height;
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pixSrc.devKind = sf->pitch;
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pixSrc.private = &privSrc;
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list_init(&privSrc.batch);
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privSrc.bo = sf->bo;
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privSrc.stride = sf->pitch;
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privSrc.tiling = I915_TILING_X;
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pictSrc.format = PICT_x8r8g8b8;
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pictSrc.filter = PictFilterNearest;
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pictSrc.repeatType = RepeatNone;
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pictDst.format = PICT_a8r8g8b8;
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pictDst.filter = PictFilterNearest;
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pictDst.repeatType = RepeatNone;
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uxa_update_fb(intel);
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i965_prepare_composite(PictOpSrc, &pictSrc, NULL, &pictDst,
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&pixSrc, NULL, &fb_pixmap);
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i965_composite(&fb_pixmap, src_x, src_y, 0, 0,
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dst_x+winx, dst_y+winy, w, h);
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i830_done_composite(&fb_pixmap);
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intel_batch_submit();
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// DBG("%s done\n", __FUNCTION__);
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return 0;
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};
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int uxa_init_fb(struct intel_screen_private *intel)
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{
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struct drm_i915_fb_info fb;
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static struct intel_pixmap ipix;
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int ret;
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memset(&fb, 0, sizeof(fb));
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ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb);
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if( ret != 0 )
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return ret;
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intel->front_buffer = intel_bo_gem_create_from_name(intel->bufmgr,"frontbuffer", fb.name);
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if(intel->front_buffer == NULL)
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return -1;
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ipix.bo = intel->front_buffer;
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list_init(&ipix.batch);
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ipix.stride = fb.pitch;
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ipix.tiling = fb.tiling;
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ipix.pinned = PIN_SCANOUT;
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printf("create frontbuffer name %d bo %x\n", fb.name, ipix.bo);
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printf("size %d, offset %d handle %d\n",ipix.bo->size, ipix.bo->offset, ipix.bo->handle);
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fb_pixmap.drawable.bitsPerPixel = 32;
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fb_pixmap.drawable.width = fb.width;
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fb_pixmap.drawable.height = fb.height;
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fb_pixmap.devKind = fb.pitch;
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fb_pixmap.private = &ipix;
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return 0;
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}
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int uxa_update_fb(struct intel_screen_private *intel)
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{
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struct drm_i915_fb_info fb;
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struct intel_pixmap *ipix;
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size_t size;
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int ret;
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// DBG("%s\n", __FUNCTION__);
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ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb);
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if( ret != 0 )
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return ret;
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ipix = (struct intel_pixmap*)fb_pixmap.private;
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list_init(&ipix->batch);
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ipix->stride = fb.pitch;
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ipix->tiling = fb.tiling;
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fb_pixmap.drawable.width = fb.width;
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fb_pixmap.drawable.height = fb.height;
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fb_pixmap.devKind = fb.pitch;
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return 0;
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};
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int uxa_init(uint32_t service)
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{
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static struct pci_device device;
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struct intel_screen_private *intel = intel_get_screen_private();
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ioctl_t io;
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int caps = 0;
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DBG("%s\n", __FUNCTION__);
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__lock_acquire_recursive(__uxa_lock);
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if(intel)
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goto done;
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io.handle = service;
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io.io_code = SRV_GET_PCI_INFO;
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io.input = &device;
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io.inp_size = sizeof(device);
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io.output = NULL;
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io.out_size = 0;
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if (call_service(&io)!=0)
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goto err1;
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intel = (intel_screen_private*)malloc(sizeof(*intel));
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if (intel == NULL)
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goto err1;
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list_init(&sf_list);
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driverPrivate = intel;
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memset(intel, 0, sizeof(*intel));
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// sna->cpu_features = sna_cpu_detect();
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intel->PciInfo = &device;
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intel->info = intel_detect_chipset(intel->PciInfo);
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intel->scrn = service;
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intel->bufmgr = intel_bufmgr_gem_init(service, 8192);
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if(intel->bufmgr == NULL)
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{
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printf("Memory manager initialization failed\n");
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goto err1;
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};
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list_init(&intel->batch_pixmaps);
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if ((INTEL_INFO(intel)->gen == 060)) {
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intel->wa_scratch_bo =
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drm_intel_bo_alloc(intel->bufmgr, "wa scratch",
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4096, 4096);
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}
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if( uxa_init_fb(intel) != 0)
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goto err1;
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intel_batch_init();
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if (INTEL_INFO(intel)->gen >= 040)
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gen4_render_state_init();
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if (!intel_uxa_init()) {
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printf("Hardware acceleration initialization failed\n");
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goto err1;
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}
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tls_mask = tls_alloc();
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// printf("tls mask %x\n", tls_mask);
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done:
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// caps = sna_device->render.caps;
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err1:
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__lock_release_recursive(__uxa_lock);
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LEAVE();
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return caps;
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}
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static void
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gen6_context_switch(intel_screen_private *intel,
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int new_mode)
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{
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intel_batch_submit(intel->scrn);
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}
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static void
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gen5_context_switch(intel_screen_private *intel,
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int new_mode)
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{
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/* Ironlake has a limitation that a 3D or Media command can't
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* be the first command after a BLT, unless it's
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* non-pipelined. Instead of trying to track it and emit a
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* command at the right time, we just emit a dummy
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* non-pipelined 3D instruction after each blit.
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*/
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if (new_mode == I915_EXEC_BLT) {
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OUT_BATCH(MI_FLUSH |
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MI_STATE_INSTRUCTION_CACHE_FLUSH |
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MI_INHIBIT_RENDER_CACHE_FLUSH);
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} else {
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OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
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OUT_BATCH(0);
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}
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}
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static void
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gen4_context_switch(intel_screen_private *intel,
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int new_mode)
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{
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if (new_mode == I915_EXEC_BLT) {
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OUT_BATCH(MI_FLUSH |
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MI_STATE_INSTRUCTION_CACHE_FLUSH |
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MI_INHIBIT_RENDER_CACHE_FLUSH);
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}
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}
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static void
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intel_limits_init(intel_screen_private *intel)
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{
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/* Limits are described in the BLT engine chapter under Graphics Data Size
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* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
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* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
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*
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* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
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*
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* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
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* i965 limits 3D surface to 4kB-aligned offset if tiled.
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* i965 limits 3D surfaces to w,h of ?,8192.
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* i965 limits 3D surface to pitch of 1B - 128kB.
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* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
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* i965 limits 3D surface pitch alignment to 512B if tiled.
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* i965 limits 3D destination drawing rect to w,h of 8192,8192.
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*
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* i915 limits 3D textures to 4B-aligned offset if un-tiled.
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* i915 limits 3D textures to ~4kB-aligned offset if tiled.
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* i915 limits 3D textures to width,height of 2048,2048.
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* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
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* i915 limits 3D destination to ~4kB-aligned offset if tiled.
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* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
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* i915 limits 3D destination to pitch 64B-aligned if used with depth.
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* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
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* i915 limits 3D destination to POT aligned pitch if tiled.
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* i915 limits 3D destination drawing rect to w,h of 2048,2048.
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*
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* i845 limits 3D textures to 4B-aligned offset if un-tiled.
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* i845 limits 3D textures to ~4kB-aligned offset if tiled.
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* i845 limits 3D textures to width,height of 2048,2048.
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* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
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* i845 limits 3D destination to 4B-aligned offset if un-tiled.
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* i845 limits 3D destination to ~4kB-aligned offset if tiled.
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* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
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* i845 limits 3D destination drawing rect to w,h of 2048,2048.
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*
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* For the tiled issues, the only tiled buffer we draw to should be
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* the front, which will have an appropriate pitch/offset already set up,
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* so UXA doesn't need to worry.
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*/
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if (INTEL_INFO(intel)->gen >= 040) {
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intel->accel_pixmap_offset_alignment = 4 * 2;
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intel->accel_max_x = 8192;
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intel->accel_max_y = 8192;
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} else {
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intel->accel_pixmap_offset_alignment = 4;
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intel->accel_max_x = 2048;
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intel->accel_max_y = 2048;
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}
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}
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Bool intel_uxa_init()
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{
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intel_screen_private *intel = intel_get_screen_private();
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intel_limits_init(intel);
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intel->prim_offset = 0;
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intel->vertex_count = 0;
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intel->vertex_offset = 0;
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intel->vertex_used = 0;
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intel->floats_per_vertex = 0;
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intel->last_floats_per_vertex = 0;
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intel->vertex_bo = NULL;
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intel->surface_used = 0;
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intel->surface_reloc = 0;
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/*
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intel->uxa_driver->check_composite = i965_check_composite;
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intel->uxa_driver->check_composite_texture = i965_check_composite_texture;
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intel->uxa_driver->prepare_composite = i965_prepare_composite;
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intel->uxa_driver->composite = i965_composite;
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intel->uxa_driver->done_composite = i830_done_composite;
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*/
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intel->vertex_flush = i965_vertex_flush;
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intel->batch_flush = i965_batch_flush;
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intel->batch_commit_notify = i965_batch_commit_notify;
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if (IS_GEN4(intel)) {
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intel->context_switch = gen4_context_switch;
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} else if (IS_GEN5(intel)) {
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intel->context_switch = gen5_context_switch;
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} else {
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intel->context_switch = gen6_context_switch;
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}
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return TRUE;
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}
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static const struct intel_device_info intel_generic_info = {
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.gen = -1,
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};
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static const struct intel_device_info intel_i915_info = {
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.gen = 030,
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};
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static const struct intel_device_info intel_i945_info = {
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.gen = 031,
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};
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static const struct intel_device_info intel_g33_info = {
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.gen = 033,
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};
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static const struct intel_device_info intel_i965_info = {
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.gen = 040,
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};
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static const struct intel_device_info intel_g4x_info = {
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.gen = 045,
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};
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static const struct intel_device_info intel_ironlake_info = {
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.gen = 050,
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};
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static const struct intel_device_info intel_sandybridge_info = {
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.gen = 060,
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};
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static const struct intel_device_info intel_ivybridge_info = {
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.gen = 070,
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};
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static const struct intel_device_info intel_valleyview_info = {
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.gen = 071,
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};
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static const struct intel_device_info intel_haswell_info = {
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.gen = 075,
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};
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#define INTEL_DEVICE_MATCH(d,i) \
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{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) }
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static const struct pci_id_match intel_device_match[] = {
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INTEL_I915G_IDS(&intel_i915_info),
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INTEL_I915GM_IDS(&intel_i915_info),
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INTEL_I945G_IDS(&intel_i945_info),
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INTEL_I945GM_IDS(&intel_i945_info),
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INTEL_G33_IDS(&intel_g33_info),
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INTEL_PINEVIEW_IDS(&intel_g33_info),
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INTEL_I965G_IDS(&intel_i965_info),
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INTEL_I965GM_IDS(&intel_i965_info),
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INTEL_G45_IDS(&intel_g4x_info),
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INTEL_GM45_IDS(&intel_g4x_info),
|
|
|
|
INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
|
|
INTEL_IRONLAKE_M_IDS(&intel_ironlake_info),
|
|
|
|
INTEL_SNB_D_IDS(&intel_sandybridge_info),
|
|
INTEL_SNB_M_IDS(&intel_sandybridge_info),
|
|
|
|
INTEL_IVB_D_IDS(&intel_ivybridge_info),
|
|
INTEL_IVB_M_IDS(&intel_ivybridge_info),
|
|
|
|
INTEL_HSW_D_IDS(&intel_haswell_info),
|
|
INTEL_HSW_M_IDS(&intel_haswell_info),
|
|
|
|
INTEL_VLV_D_IDS(&intel_valleyview_info),
|
|
INTEL_VLV_M_IDS(&intel_valleyview_info),
|
|
|
|
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
|
|
|
|
{ 0, 0, 0 },
|
|
};
|
|
|
|
const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list)
|
|
{
|
|
while(list->device_id)
|
|
{
|
|
if(dev==list->device_id)
|
|
return list;
|
|
list++;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
|
|
const struct intel_device_info *
|
|
intel_detect_chipset(struct pci_device *pci)
|
|
{
|
|
const struct pci_id_match *ent = NULL;
|
|
|
|
ent = PciDevMatch(pci->device_id, intel_device_match);
|
|
|
|
if(ent != NULL)
|
|
return (const struct intel_device_info*)ent->match_data;
|
|
else
|
|
return &intel_generic_info;
|
|
}
|
|
|