forked from KolibriOS/kolibrios
444 lines
11 KiB
C
444 lines
11 KiB
C
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <string.h>
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#include "intel.h"
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#include "i965_reg.h"
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#include "brw_defines.h"
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#include "brw_structs.h"
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void
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gen6_upload_invariant_states(intel_screen_private *intel)
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{
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Bool ivb = INTEL_INFO(intel)->gen >= 070;
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OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2));
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OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
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BRW_PIPE_CONTROL_WC_FLUSH |
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BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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BRW_PIPE_CONTROL_NOWRITE);
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OUT_BATCH(0); /* write address */
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OUT_BATCH(0); /* write data */
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OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
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OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2));
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OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
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GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
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OUT_BATCH(0);
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if (ivb)
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
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OUT_BATCH(1);
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/* Set system instruction pointer */
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OUT_BATCH(BRW_STATE_SIP | 0);
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OUT_BATCH(0);
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}
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void
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gen6_upload_viewport_state_pointers(intel_screen_private *intel,
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drm_intel_bo *cc_vp_bo)
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{
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OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
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GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
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(4 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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}
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void
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gen7_upload_viewport_state_pointers(intel_screen_private *intel,
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drm_intel_bo *cc_vp_bo)
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{
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OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2));
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OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2));
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OUT_BATCH(0);
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}
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void
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gen6_upload_urb(intel_screen_private *intel)
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{
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OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
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OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
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(24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
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OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) |
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(0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */
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}
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/*
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* URB layout on GEN7
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* ----------------------------------------
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* | PS Push Constants (8KB) | VS entries |
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* ----------------------------------------
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*/
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void
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gen7_upload_urb(intel_screen_private *intel)
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{
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unsigned int num_urb_entries = 32;
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if (IS_HSW(intel))
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num_urb_entries = 64;
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OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
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OUT_BATCH(8); /* in 1KBs */
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OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
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OUT_BATCH(
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(num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) |
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(2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
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(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
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OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
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(2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
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}
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void
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gen6_upload_cc_state_pointers(intel_screen_private *intel,
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drm_intel_bo *blend_bo,
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drm_intel_bo *cc_bo,
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drm_intel_bo *depth_stencil_bo,
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uint32_t blend_offset)
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{
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OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
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if (blend_bo)
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OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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blend_offset | 1);
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else
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OUT_BATCH(0);
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if (depth_stencil_bo)
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OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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else
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OUT_BATCH(0);
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if (cc_bo)
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OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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else
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OUT_BATCH(0);
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}
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void
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gen7_upload_cc_state_pointers(intel_screen_private *intel,
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drm_intel_bo *blend_bo,
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drm_intel_bo *cc_bo,
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drm_intel_bo *depth_stencil_bo,
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uint32_t blend_offset)
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{
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OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2));
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if (blend_bo)
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OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
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blend_offset | 1);
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else
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2));
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if (cc_bo)
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OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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else
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2));
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if (depth_stencil_bo)
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OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
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else
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OUT_BATCH(0);
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}
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void
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gen6_upload_sampler_state_pointers(intel_screen_private *intel,
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drm_intel_bo *sampler_bo)
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{
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OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
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GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
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(4 - 2));
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OUT_BATCH(0); /* VS */
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OUT_BATCH(0); /* GS */
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OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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}
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void
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gen7_upload_sampler_state_pointers(intel_screen_private *intel,
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drm_intel_bo *sampler_bo)
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{
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OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2));
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OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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}
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void
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gen7_upload_bypass_states(intel_screen_private *intel)
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{
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/* bypass GS */
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
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OUT_BATCH(0); /* without GS kernel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2));
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OUT_BATCH(0);
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/* disable HS */
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OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
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OUT_BATCH(0);
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/* Disable TE */
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OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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/* Disable DS */
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OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2));
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OUT_BATCH(0);
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/* Disable STREAMOUT */
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OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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void
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gen6_upload_vs_state(intel_screen_private *intel)
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{
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Bool ivb = INTEL_INFO(intel)->gen >= 070;
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/* disable VS constant buffer */
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | ((ivb ? 7 : 5) - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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if (ivb) {
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
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OUT_BATCH(0); /* without VS kernel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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}
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void
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gen6_upload_gs_state(intel_screen_private *intel)
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{
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/* disable GS constant buffer */
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
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OUT_BATCH(0); /* without GS kernel */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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}
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void
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gen6_upload_clip_state(intel_screen_private *intel)
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{
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OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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OUT_BATCH(0);
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}
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void
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gen6_upload_sf_state(intel_screen_private *intel,
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int num_sf_outputs,
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int read_offset)
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{
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OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
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OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) |
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(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) |
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(read_offset << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT));
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
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OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* DW9 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* DW14 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* DW19 */
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}
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void
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gen7_upload_sf_state(intel_screen_private *intel,
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int num_sf_outputs,
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int read_offset)
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{
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OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2));
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OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) |
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(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) |
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(read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* DW4 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0); /* DW9 */
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
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OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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void
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gen6_upload_binding_table(intel_screen_private *intel,
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uint32_t ps_binding_table_offset)
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{
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/* Binding table pointers */
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OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
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GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
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(4 - 2));
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OUT_BATCH(0); /* VS */
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OUT_BATCH(0); /* GS */
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/* Only the PS uses the binding table */
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OUT_BATCH(ps_binding_table_offset);
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}
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void
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gen7_upload_binding_table(intel_screen_private *intel,
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uint32_t ps_binding_table_offset)
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{
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OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2));
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OUT_BATCH(ps_binding_table_offset);
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}
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void
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gen6_upload_depth_buffer_state(intel_screen_private *intel)
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{
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OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
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OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
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(BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2));
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OUT_BATCH(0);
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}
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void
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gen7_upload_depth_buffer_state(intel_screen_private *intel)
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{
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OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
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OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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