forked from KolibriOS/kolibrios
849 lines
26 KiB
PHP
849 lines
26 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2011. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; PCNET32.INC ;;
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;; ;;
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;; Ethernet driver for Menuet OS ;;
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;; ;;
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;; - Version 1.0 31 July 2004: ;;
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;; Initial release ;;
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;; ;;
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;; - Version 1.01 29 March 2008: ;;
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;; Adapted to work with kolibrios flat kernel ;;
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;; Debug info is updated, and now uses DEBUGF macro ;;
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;; by hidnplayr@kolibrios.org ;;
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;; ;;
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;; This driver is based on the PCNet32 driver from ;;
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;; the etherboot 5.0.6 project. The copyright statement is ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;; remaining parts Copyright 2004 Jarek Pelczar, ;;
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;; jpelczar@interia.pl ;;
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;; ;;
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;; See file COPYING for details ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision$
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PCNET32_PORT_AUI equ 0x00
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PCNET32_PORT_10BT equ 0x01
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PCNET32_PORT_GPSI equ 0x02
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PCNET32_PORT_MII equ 0x03
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PCNET32_PORT_PORTSEL equ 0x03
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PCNET32_PORT_ASEL equ 0x04
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PCNET32_PORT_100 equ 0x40
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PCNET32_PORT_FD equ 0x80
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PCNET32_DMA_MASK equ 0xffffffff
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PCNET32_LOG_TX_BUFFERS equ 1
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PCNET32_LOG_RX_BUFFERS equ 2
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PCNET32_TX_RING_SIZE equ (1 shl PCNET32_LOG_TX_BUFFERS)
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PCNET32_TX_RING_MOD_MASK equ (PCNET32_TX_RING_SIZE-1)
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PCNET32_TX_RING_LEN_BITS equ 0
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PCNET32_RX_RING_SIZE equ (1 shl PCNET32_LOG_RX_BUFFERS)
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PCNET32_RX_RING_MOD_MASK equ (PCNET32_RX_RING_SIZE-1)
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PCNET32_RX_RING_LEN_BITS equ (PCNET32_LOG_RX_BUFFERS shl 4)
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PCNET32_PKT_BUF_SZ equ 1544
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PCNET32_PKT_BUF_SZ_NEG equ 0xf9f8
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pcnet32_txb equ (eth_data_start)
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pcnet32_rxb equ ((pcnet32_txb+(PCNET32_PKT_BUF_SZ*PCNET32_TX_RING_SIZE)+0xf) and 0xfffffff0)
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pcnet32_tx_ring equ ((pcnet32_rxb+(PCNET32_PKT_BUF_SZ*PCNET32_RX_RING_SIZE)+0xf) and 0xfffffff0)
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pcnet32_rx_ring equ ((pcnet32_tx_ring+(16*PCNET32_TX_RING_SIZE)+0xf) and 0xfffffff0)
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virtual at ((pcnet32_rx_ring+(16*PCNET32_RX_RING_SIZE)+0xf) and 0xfffffff0)
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pcnet32_private:
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.mode dw ?
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.tlen_rlen dw ?
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.phys_addr db ?,?,?,?,?,?
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.reserved dw ?
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.filter dd ?,?
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.rx_ring dd ?
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.tx_ring dd ?
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.cur_rx dd ?
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.cur_tx dd ?
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.dirty_rx dd ?
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.dirty_tx dd ?
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.tx_full db ?
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.options dd ?
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.full_duplex db ?
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.chip_version dd ?
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.mii db ?
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.ltint db ?
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.dxsuflo db ?
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.fset db ?
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.fdx db ?
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end virtual
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virtual at 0
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pcnet32_rx_head:
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.base dd ?
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.buf_length dw ?
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.status dw ?
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.msg_length dd ?
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.reserved dd ?
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end virtual
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virtual at 0
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pcnet32_tx_head:
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.base dd ?
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.length dw ?
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.status dw ?
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.misc dd ?
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.reserved dd ?
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end virtual
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uglobal
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pcnet32_access:
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.read_csr dd ?
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.write_csr dd ?
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.read_bcr dd ?
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.write_bcr dd ?
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.read_rap dd ?
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.write_rap dd ?
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.reset dd ?
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endg
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iglobal
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pcnet32_options_mapping:
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dd PCNET32_PORT_ASEL ; 0 Auto-select
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dd PCNET32_PORT_AUI ; 1 BNC/AUI
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dd PCNET32_PORT_AUI ; 2 AUI/BNC
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dd PCNET32_PORT_ASEL ; 3 not supported
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dd PCNET32_PORT_10BT or PCNET32_PORT_FD ; 4 10baseT-FD
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dd PCNET32_PORT_ASEL ; 5 not supported
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dd PCNET32_PORT_ASEL ; 6 not supported
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dd PCNET32_PORT_ASEL ; 7 not supported
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dd PCNET32_PORT_ASEL ; 8 not supported
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dd PCNET32_PORT_MII ; 9 MII 10baseT
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dd PCNET32_PORT_MII or PCNET32_PORT_FD ; 10 MII 10baseT-FD
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dd PCNET32_PORT_MII ; 11 MII (autosel)
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dd PCNET32_PORT_10BT ; 12 10BaseT
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dd PCNET32_PORT_MII or PCNET32_PORT_100 ; 13 MII 100BaseTx
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dd PCNET32_PORT_MII or PCNET32_PORT_100 or PCNET32_PORT_FD ; 14 MII 100BaseTx-FD
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dd PCNET32_PORT_ASEL ; 15 not supported
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endg
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PCNET32_WIO_RDP equ 0x10
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PCNET32_WIO_RAP equ 0x12
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PCNET32_WIO_RESET equ 0x14
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PCNET32_WIO_BDP equ 0x16
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PCNET32_DWIO_RDP equ 0x10
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PCNET32_DWIO_RAP equ 0x14
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PCNET32_DWIO_RESET equ 0x18
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PCNET32_DWIO_BDP equ 0x1C
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PCNET32_TOTAL_SIZE equ 0x20
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; ebx - index
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; return:
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; eax - data
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pcnet32_wio_read_csr:
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push edx
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lea edx, [ebp+PCNET32_WIO_RAP]
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mov ax, bx
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out dx, ax
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lea edx, [ebp+PCNET32_WIO_RDP]
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in ax, dx
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and eax, 0xffff
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pop edx
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ret
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; eax - data
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; ebx - index
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pcnet32_wio_write_csr:
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push edx
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lea edx, [ebp+PCNET32_WIO_RAP]
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xchg eax, ebx
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out dx, ax
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xchg eax, ebx
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lea edx, [ebp+PCNET32_WIO_RDP]
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out dx, ax
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pop edx
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ret
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; ebx - index
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; return:
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; eax - data
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pcnet32_wio_read_bcr:
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push edx
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lea edx, [ebp+PCNET32_WIO_RAP]
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mov ax, bx
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out dx, ax
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lea edx, [ebp+PCNET32_WIO_BDP]
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in ax, dx
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and eax, 0xffff
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pop edx
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ret
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; eax - data
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; ebx - index
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pcnet32_wio_write_bcr:
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push edx
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lea edx, [ebp+PCNET32_WIO_RAP]
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xchg eax, ebx
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out dx, ax
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xchg eax, ebx
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lea edx, [ebp+PCNET32_WIO_BDP]
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out dx, ax
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pop edx
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ret
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pcnet32_wio_read_rap:
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push edx
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lea edx, [ebp+PCNET32_WIO_RAP]
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in ax, dx
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and eax, 0xffff
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pop edx
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ret
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; eax - val
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pcnet32_wio_write_rap:
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push edx
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lea edx, [ebp+PCNET32_WIO_RAP]
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out dx, ax
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pop edx
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ret
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pcnet32_wio_reset:
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push edx
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push eax
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lea edx, [ebp+PCNET32_WIO_RESET]
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in ax, dx
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pop eax
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pop edx
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ret
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pcnet32_wio_check:
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push edx
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mov ax, 88
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lea edx, [ebp+PCNET32_WIO_RAP]
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out dx, ax
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nop
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nop
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in ax, dx
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cmp ax, 88
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sete al
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pop edx
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ret
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iglobal
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pcnet32_wio:
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dd pcnet32_wio_read_csr
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dd pcnet32_wio_write_csr
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dd pcnet32_wio_read_bcr
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dd pcnet32_wio_write_bcr
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dd pcnet32_wio_read_rap
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dd pcnet32_wio_write_rap
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dd pcnet32_wio_reset
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endg
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; ebx - index
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; return:
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; eax - data
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pcnet32_dwio_read_csr:
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push edx
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lea edx, [ebp+PCNET32_DWIO_RAP]
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mov eax, ebx
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out dx, eax
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lea edx, [ebp+PCNET32_DWIO_RDP]
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in eax, dx
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and eax, 0xffff
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pop edx
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ret
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; ebx - index
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; eax - data
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pcnet32_dwio_write_csr:
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push edx
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lea edx, [ebp+PCNET32_DWIO_RAP]
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xchg eax, ebx
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out dx, eax
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lea edx, [ebp+PCNET32_DWIO_RDP]
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xchg eax, ebx
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out dx, eax
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pop edx
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ret
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; ebx - index
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; return:
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; eax - data
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pcnet32_dwio_read_bcr:
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push edx
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lea edx, [ebp+PCNET32_DWIO_RAP]
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mov eax, ebx
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out dx, eax
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lea edx, [ebp+PCNET32_DWIO_BDP]
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in eax, dx
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and eax, 0xffff
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pop edx
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ret
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; ebx - index
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; eax - data
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pcnet32_dwio_write_bcr:
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push edx
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lea edx, [ebp+PCNET32_DWIO_RAP]
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xchg eax, ebx
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out dx, eax
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lea edx, [ebp+PCNET32_DWIO_BDP]
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xchg eax, ebx
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out dx, eax
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pop edx
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ret
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pcnet32_dwio_read_rap:
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push edx
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lea edx, [ebp+PCNET32_DWIO_RAP]
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in eax, dx
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and eax, 0xffff
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pop edx
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ret
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; eax - val
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pcnet32_dwio_write_rap:
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push edx
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lea edx, [ebp+PCNET32_DWIO_RAP]
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out dx, eax
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pop edx
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ret
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pcnet32_dwio_reset:
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push edx
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push eax
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lea edx, [ebp+PCNET32_DWIO_RESET]
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in eax, dx
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pop eax
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pop edx
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ret
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pcnet32_dwio_check:
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push edx
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lea edx, [PCNET32_DWIO_RAP]
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mov eax, 88
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out dx, eax
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nop
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nop
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in eax, dx
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and eax, 0xffff
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cmp eax, 88
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sete al
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pop edx
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ret
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iglobal
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pcnet32_dwio:
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dd pcnet32_dwio_read_csr
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dd pcnet32_dwio_write_csr
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dd pcnet32_dwio_read_bcr
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dd pcnet32_dwio_write_bcr
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dd pcnet32_dwio_read_rap
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dd pcnet32_dwio_write_rap
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dd pcnet32_dwio_reset
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endg
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pcnet32_init_ring:
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mov [pcnet32_private.tx_full], 0
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mov [pcnet32_private.cur_rx], 0
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mov [pcnet32_private.cur_tx], 0
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mov [pcnet32_private.dirty_rx], 0
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mov [pcnet32_private.dirty_tx], 0
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mov edi, pcnet32_rx_ring
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mov ecx, PCNET32_RX_RING_SIZE
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mov ebx, pcnet32_rxb
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sub ebx, OS_BASE
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.rx_init:
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mov [edi+pcnet32_rx_head.base], ebx
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mov [edi+pcnet32_rx_head.buf_length], word PCNET32_PKT_BUF_SZ_NEG
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mov [edi+pcnet32_rx_head.status], word 0x8000
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add ebx, PCNET32_PKT_BUF_SZ
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; inc ebx
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add edi, 16
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loop .rx_init
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mov edi, pcnet32_tx_ring
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mov ecx, PCNET32_TX_RING_SIZE
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.tx_init:
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mov [edi+pcnet32_tx_head.base], dword 0
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mov [edi+pcnet32_tx_head.status], word 0
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add edi, 16
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loop .tx_init
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mov [pcnet32_private.tlen_rlen], (PCNET32_TX_RING_LEN_BITS or PCNET32_RX_RING_LEN_BITS)
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mov esi, node_addr
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mov edi, pcnet32_private.phys_addr
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cld
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movsd
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movsw
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mov eax, pcnet32_rx_ring
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sub eax, OS_BASE
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mov dword [pcnet32_private.rx_ring], eax
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mov eax, pcnet32_tx_ring
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sub eax, OS_BASE
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mov dword [pcnet32_private.tx_ring], eax
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ret
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pcnet32_reset:
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; Reset PCNET32
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mov ebp, [io_addr]
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call dword [pcnet32_access.reset]
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; set 32bit mode
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mov ebx, 20
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mov eax, 2
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call dword [pcnet32_access.write_bcr]
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; set/reset autoselect bit
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mov ebx, 2
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call dword [pcnet32_access.read_bcr]
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and eax, not 2
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test [pcnet32_private.options], PCNET32_PORT_ASEL
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jz .L1
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or eax, 2
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.L1:
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call dword [pcnet32_access.write_bcr]
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; Handle full duplex setting
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cmp byte [pcnet32_private.full_duplex], 0
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je .L2
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mov ebx, 9
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call dword [pcnet32_access.read_bcr]
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and eax, not 3
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test [pcnet32_private.options], PCNET32_PORT_FD
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jz .L3
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or eax, 1
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cmp [pcnet32_private.options], PCNET32_PORT_FD or PCNET32_PORT_AUI
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jne .L4
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or eax, 2
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jmp .L4
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.L3:
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test [pcnet32_private.options], PCNET32_PORT_ASEL
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jz .L4
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cmp [pcnet32_private.chip_version], 0x2627
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jne .L4
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or eax, 3
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.L4:
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mov ebx, 9
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call dword [pcnet32_access.write_bcr]
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.L2:
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; set/reset GPSI bit
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mov ebx, 124
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call dword [pcnet32_access.read_csr]
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mov ecx, [pcnet32_private.options]
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and ecx, PCNET32_PORT_PORTSEL
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cmp ecx, PCNET32_PORT_GPSI
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jne .L5
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or eax, 0x10
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.L5:
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call dword [pcnet32_access.write_csr]
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cmp [pcnet32_private.mii], 0
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je .L6
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test [pcnet32_private.options], PCNET32_PORT_ASEL
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jnz .L6
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mov ebx, 32
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call dword [pcnet32_access.read_bcr]
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and eax, not 0x38
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test [pcnet32_private.options], PCNET32_PORT_FD
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jz .L7
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or eax, 0x10
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.L7:
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test [pcnet32_private.options], PCNET32_PORT_100
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jz .L8
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or eax, 0x08
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.L8:
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call dword [pcnet32_access.write_bcr]
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jmp .L9
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.L6:
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test [pcnet32_private.options], PCNET32_PORT_ASEL
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jz .L9
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mov ebx, 32
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; DEBUGF 1," K : ASEL, enable auto-negotiation\n"
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call dword [pcnet32_access.read_bcr]
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and eax, not 0x98
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or eax, 0x20
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call dword [pcnet32_access.write_bcr]
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.L9:
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cmp [pcnet32_private.ltint], 0
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je .L10
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mov ebx, 5
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call dword [pcnet32_access.read_csr]
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or eax, (1 shl 14)
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call dword [pcnet32_access.write_csr]
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.L10:
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mov eax, [pcnet32_private.options]
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and eax, PCNET32_PORT_PORTSEL
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shl eax, 7
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mov [pcnet32_private.mode], ax
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mov [pcnet32_private.filter], dword 0xffffffff
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mov [pcnet32_private.filter+4], dword 0xffffffff
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call pcnet32_init_ring
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mov ebx, 1
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mov eax, pcnet32_private
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sub eax, OS_BASE
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and eax, 0xffff
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call dword [pcnet32_access.write_csr]
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mov eax, pcnet32_private
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sub eax, OS_BASE
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mov ebx, 2
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shr eax, 16
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call dword [pcnet32_access.write_csr]
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mov ebx, 4
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mov eax, 0x0915
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call dword [pcnet32_access.write_csr]
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mov ebx, 0
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mov eax, 1
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call dword [pcnet32_access.write_csr]
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mov ecx, 100
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.L11:
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xor ebx, ebx
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call dword [pcnet32_access.read_csr]
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test ax, 0x100
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jnz .L12
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loop .L11
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.L12:
|
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; DEBUGF 1," K : hardware reset\n"
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xor ebx, ebx
|
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mov eax, 0x0002
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call dword [pcnet32_access.write_csr]
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xor ebx, ebx
|
|
call dword [pcnet32_access.read_csr]
|
|
; DEBUGF 1," K : PCNET reset complete\n"
|
|
ret
|
|
|
|
|
|
|
|
pcnet32_adjust_pci_device:
|
|
;*******Get current setting************************
|
|
mov al, 2 ;read a word
|
|
mov bh, [pci_dev]
|
|
mov ah, [pci_bus]
|
|
mov bl, 0x04 ;from command Register
|
|
call pci_read_reg
|
|
;******see if its already set as bus master********
|
|
mov bx, ax
|
|
and bx, 5
|
|
cmp bx, 5
|
|
je pcnet32_adjust_pci_device_Latency
|
|
;******Make card a bus master*******
|
|
mov cx, ax ;value to write
|
|
mov bh, [pci_dev]
|
|
mov al, 2 ;write a word
|
|
or cx, 5
|
|
mov ah, [pci_bus]
|
|
mov bl, 0x04 ;to command register
|
|
call pci_write_reg
|
|
;******Check latency setting***********
|
|
pcnet32_adjust_pci_device_Latency:
|
|
;*******Get current latency setting************************
|
|
; mov al, 1 ;read a byte
|
|
; mov bh, [pci_dev]
|
|
; mov ah, [pci_bus]
|
|
; mov bl, 0x0D ;from Lantency Timer Register
|
|
; call pci_read_reg
|
|
;******see if its aat least 64 clocks********
|
|
; cmp ax,64
|
|
; jge pcnet32_adjust_pci_device_Done
|
|
;******Set latency to 32 clocks*******
|
|
; mov cx, 64 ;value to write
|
|
; mov bh, [pci_dev]
|
|
; mov al, 1 ;write a byte
|
|
; mov ah, [pci_bus]
|
|
; mov bl, 0x0D ;to Lantency Timer Register
|
|
; call pci_write_reg
|
|
;******Check latency setting***********
|
|
pcnet32_adjust_pci_device_Done:
|
|
ret
|
|
|
|
|
|
|
|
|
|
pcnet32_probe:
|
|
mov ebp, [io_addr]
|
|
call pcnet32_wio_reset
|
|
xor ebx, ebx
|
|
call pcnet32_wio_read_csr
|
|
cmp eax, 4
|
|
jne .try_dwio
|
|
call pcnet32_wio_check
|
|
and al, al
|
|
jz .try_dwio
|
|
; DEBUGF 1," K : Using WIO\n"
|
|
mov esi, pcnet32_wio
|
|
jmp .L1
|
|
.try_dwio:
|
|
call pcnet32_dwio_reset
|
|
xor ebx, ebx
|
|
call pcnet32_dwio_read_csr
|
|
cmp eax, 4
|
|
jne .no_dev
|
|
call pcnet32_dwio_check
|
|
and al, al
|
|
jz .no_dev
|
|
; DEBUGF 1," K : Using DWIO\n"
|
|
mov esi, pcnet32_dwio
|
|
jmp .L1
|
|
.no_dev:
|
|
DEBUGF 1," K : PCNET32 not found\n"
|
|
ret
|
|
.L1:
|
|
mov edi, pcnet32_access
|
|
mov ecx, 7
|
|
cld
|
|
rep movsd
|
|
mov ebx, 88
|
|
call dword [pcnet32_access.read_csr]
|
|
mov ecx, eax
|
|
mov ebx, 89
|
|
call dword [pcnet32_access.read_csr]
|
|
shl eax, 16
|
|
or eax, ecx
|
|
mov ecx, eax
|
|
and ecx, 0xfff
|
|
cmp ecx, 3
|
|
jne .no_dev
|
|
shr eax, 12
|
|
and eax, 0xffff
|
|
mov [pcnet32_private.chip_version], eax
|
|
; DEBUGF 1," K : PCNET32 chip version OK\n"
|
|
mov [pcnet32_private.fdx], 0
|
|
mov [pcnet32_private.mii], 0
|
|
mov [pcnet32_private.fset], 0
|
|
mov [pcnet32_private.dxsuflo], 0
|
|
mov [pcnet32_private.ltint], 0
|
|
mov eax, [pcnet32_private.chip_version]
|
|
cmp eax, 0x2420
|
|
je .L2
|
|
cmp eax, 0x2430
|
|
je .L3
|
|
cmp eax, 0x2621
|
|
je .L4
|
|
cmp eax, 0x2623
|
|
je .L5
|
|
cmp eax, 0x2624
|
|
je .L6
|
|
cmp eax, 0x2625
|
|
je .L7
|
|
cmp eax, 0x2626
|
|
je .L8
|
|
cmp eax, 0x2627
|
|
je .L9
|
|
DEBUGF 1," K : Invalid chip rev\n"
|
|
jmp .no_dev
|
|
.L2:
|
|
; DEBUGF 1," K : PCnet/PCI 79C970\n"
|
|
jmp .L10
|
|
.L3:
|
|
; DEBUGF 1," K : PCnet/PCI 79C970\n"
|
|
jmp .L10
|
|
.L4:
|
|
; DEBUGF 1," K : PCnet/PCI II 79C970A\n"
|
|
mov [pcnet32_private.fdx], 1
|
|
jmp .L10
|
|
.L5:
|
|
; DEBUGF 1," K : PCnet/FAST 79C971\n"
|
|
mov [pcnet32_private.fdx], 1
|
|
mov [pcnet32_private.mii], 1
|
|
mov [pcnet32_private.fset], 1
|
|
mov [pcnet32_private.ltint], 1
|
|
jmp .L10
|
|
.L6:
|
|
; DEBUGF 1," K : PCnet/FAST+ 79C972\n"
|
|
mov [pcnet32_private.fdx], 1
|
|
mov [pcnet32_private.mii], 1
|
|
mov [pcnet32_private.fset], 1
|
|
jmp .L10
|
|
.L7:
|
|
; DEBUGF 1," K : PCnet/FAST III 79C973\n"
|
|
mov [pcnet32_private.fdx], 1
|
|
mov [pcnet32_private.mii], 1
|
|
jmp .L10
|
|
.L8:
|
|
; DEBUGF 1," K : PCnet/Home 79C978\n"
|
|
mov [pcnet32_private.fdx], 1
|
|
mov ebx, 49
|
|
call dword [pcnet32_access.read_bcr]
|
|
call dword [pcnet32_access.write_bcr]
|
|
jmp .L10
|
|
.L9:
|
|
; DEBUGF 1," K : PCnet/FAST III 79C975\n"
|
|
mov [pcnet32_private.fdx], 1
|
|
mov [pcnet32_private.mii], 1
|
|
.L10:
|
|
cmp [pcnet32_private.fset], 1
|
|
jne .L11
|
|
mov ebx, 18
|
|
call dword [pcnet32_access.read_bcr]
|
|
or eax, 0x800
|
|
call dword [pcnet32_access.write_bcr]
|
|
mov ebx, 80
|
|
call dword [pcnet32_access.read_csr]
|
|
and eax, 0xc00
|
|
or eax, 0xc00
|
|
call dword [pcnet32_access.write_csr]
|
|
mov [pcnet32_private.dxsuflo], 1
|
|
mov [pcnet32_private.ltint], 1
|
|
.L11:
|
|
; read MAC
|
|
mov edi, node_addr
|
|
mov edx, ebp
|
|
mov ecx, 6
|
|
.Lmac:
|
|
in al, dx
|
|
stosb
|
|
inc edx
|
|
loop .Lmac
|
|
; DEBUGF 1," K : MAC read\n"
|
|
call pcnet32_adjust_pci_device
|
|
; DEBUGF 1," K : PCI done\n"
|
|
mov eax, PCNET32_PORT_ASEL
|
|
mov [pcnet32_private.options], eax
|
|
mov [pcnet32_private.mode], word 0x0003
|
|
mov [pcnet32_private.tlen_rlen], word (PCNET32_TX_RING_LEN_BITS or PCNET32_RX_RING_LEN_BITS)
|
|
mov esi, node_addr
|
|
mov edi, pcnet32_private.phys_addr
|
|
cld
|
|
movsd
|
|
movsw
|
|
mov [pcnet32_private.filter], dword 0
|
|
mov [pcnet32_private.filter+4], dword 0
|
|
mov eax, pcnet32_rx_ring
|
|
sub eax, OS_BASE
|
|
mov dword [pcnet32_private.rx_ring], eax
|
|
|
|
mov eax, pcnet32_tx_ring
|
|
sub eax, OS_BASE
|
|
mov dword [pcnet32_private.tx_ring], eax
|
|
; DEBUGF 1," K : Switching to 32\n"
|
|
mov ebx, 20
|
|
mov eax, 2
|
|
call dword [pcnet32_access.write_bcr]
|
|
mov ebx, 1
|
|
mov eax, ((pcnet32_private - OS_BASE) and 0xffff)
|
|
call dword [pcnet32_access.write_csr]
|
|
mov ebx, 2
|
|
mov eax, ((pcnet32_private - OS_BASE) shr 16) and 0xffff
|
|
call dword [pcnet32_access.write_csr]
|
|
mov ebx, 0
|
|
mov eax, 1
|
|
call dword [pcnet32_access.write_csr]
|
|
mov esi, 1
|
|
call delay_ms
|
|
call pcnet32_reset
|
|
mov eax, [pci_data]
|
|
mov [eth_status], eax
|
|
ret
|
|
|
|
|
|
|
|
pcnet32_poll:
|
|
xor ax, ax
|
|
mov [eth_rx_data_len], ax
|
|
mov eax, [pcnet32_private.cur_rx]
|
|
and eax, PCNET32_RX_RING_MOD_MASK
|
|
mov ebx, eax
|
|
imul esi, eax, PCNET32_PKT_BUF_SZ
|
|
add esi, pcnet32_rxb
|
|
shl ebx, 4
|
|
add ebx, pcnet32_rx_ring
|
|
mov cx, [ebx+pcnet32_rx_head.status]
|
|
test cx, 0x8000
|
|
jnz .L1
|
|
cmp ch, 3
|
|
jne .L1
|
|
mov ecx, [ebx+pcnet32_rx_head.msg_length]
|
|
and ecx, 0xfff
|
|
sub ecx, 4
|
|
mov [eth_rx_data_len], cx
|
|
; DEBUGF 1," K : PCNETRX: %ub\n",cx
|
|
push ecx
|
|
shr ecx, 2
|
|
mov edi, Ether_buffer
|
|
cld
|
|
rep movsd
|
|
pop ecx
|
|
and ecx, 3
|
|
rep movsb
|
|
mov [ebx+pcnet32_rx_head.buf_length], word PCNET32_PKT_BUF_SZ_NEG
|
|
or [ebx+pcnet32_rx_head.status], word 0x8000
|
|
inc [pcnet32_private.cur_rx]
|
|
.L1:
|
|
ret
|
|
|
|
|
|
|
|
|
|
; Pointer to 48 bit destination address in edi
|
|
; Type of packet in bx
|
|
; size of packet in ecx
|
|
; pointer to packet data in esi
|
|
pcnet32_xmit:
|
|
push edi
|
|
push esi
|
|
push ebx
|
|
push ecx
|
|
; DEBUGF 1," K : PCNETTX\n"
|
|
mov esi, edi
|
|
mov edi, [pcnet32_private.cur_tx]
|
|
imul edi, PCNET32_PKT_BUF_SZ
|
|
add edi, pcnet32_txb; edi=ptxb
|
|
mov eax, edi
|
|
cld ; copy MAC
|
|
movsd
|
|
movsw
|
|
mov esi, node_addr
|
|
cld
|
|
movsd
|
|
movsw
|
|
mov [edi], bx
|
|
add edi, 2
|
|
mov esi, [esp+8]
|
|
mov ecx, [esp]
|
|
push ecx
|
|
shr ecx, 2
|
|
cld
|
|
rep movsd
|
|
pop ecx
|
|
and ecx, 3
|
|
rep movsb
|
|
; mov ecx,[esp]
|
|
; add ecx,14 ; ETH_HLEN
|
|
; xor eax,eax
|
|
; pad to min length (60=ETH_ZLEN)
|
|
; cmp ecx,60
|
|
; jae .L1
|
|
; sub ecx,60
|
|
; cld
|
|
; rep stosb
|
|
;.L1:
|
|
mov edi, pcnet32_tx_ring+0; entry=0
|
|
mov ecx, [esp]
|
|
add ecx, 14
|
|
cmp cx, 60
|
|
jae .L1
|
|
mov cx, 60
|
|
.L1:
|
|
neg cx
|
|
mov [edi+pcnet32_tx_head.length], cx
|
|
mov [edi+pcnet32_tx_head.misc], dword 0
|
|
sub eax, OS_BASE
|
|
mov [edi+pcnet32_tx_head.base], eax
|
|
mov [edi+pcnet32_tx_head.status], word 0x8300
|
|
; trigger an immediate send poll
|
|
mov ebx, 0
|
|
mov eax, 0x0008; 0x0048
|
|
mov ebp, [io_addr]
|
|
call dword [pcnet32_access.write_csr]
|
|
mov dword [pcnet32_private.cur_tx], 0
|
|
; wait for TX to complete
|
|
mov ecx, [timer_ticks];[0xfdf0]
|
|
add ecx, 100
|
|
.L2:
|
|
mov ax, [edi+pcnet32_tx_head.status]
|
|
test ax, 0x8000
|
|
jz .L3
|
|
cmp ecx, [timer_ticks];[0xfdf0]
|
|
jb .L4
|
|
mov esi, 10
|
|
call delay_ms
|
|
jnz .L2
|
|
.L4:
|
|
DEBUGF 1," K : PCNET: Send timeout\n"
|
|
.L3:
|
|
mov dword [edi+pcnet32_tx_head.base], 0
|
|
pop ecx
|
|
pop ebx
|
|
pop esi
|
|
pop edi
|
|
ret
|