forked from KolibriOS/kolibrios
274 lines
7.9 KiB
C
274 lines
7.9 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon.h"
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#include "radeon_reg.h"
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/*
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* Common GART table functions.
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*/
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int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
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{
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void *ptr;
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ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
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&rdev->gart.table_addr);
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if (ptr == NULL) {
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return -ENOMEM;
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}
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#ifdef CONFIG_X86
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
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rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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set_memory_uc((unsigned long)ptr,
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rdev->gart.table_size >> PAGE_SHIFT);
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}
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#endif
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rdev->gart.table.ram.ptr = ptr;
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memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
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return 0;
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}
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void radeon_gart_table_ram_free(struct radeon_device *rdev)
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{
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if (rdev->gart.table.ram.ptr == NULL) {
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return;
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}
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#ifdef CONFIG_X86
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if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
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rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
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set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
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rdev->gart.table_size >> PAGE_SHIFT);
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}
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#endif
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// pci_free_consistent(rdev->pdev, rdev->gart.table_size,
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// (void *)rdev->gart.table.ram.ptr,
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// rdev->gart.table_addr);
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rdev->gart.table.ram.ptr = NULL;
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rdev->gart.table_addr = 0;
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}
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int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.table.vram.robj == NULL) {
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r = radeon_bo_create(rdev, NULL, rdev->gart.table_size,
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true, RADEON_GEM_DOMAIN_VRAM,
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&rdev->gart.table.vram.robj);
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if (r) {
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return r;
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}
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}
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return 0;
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}
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int radeon_gart_table_vram_pin(struct radeon_device *rdev)
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{
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uint64_t gpu_addr;
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int r;
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r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_pin(rdev->gart.table.vram.robj,
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RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
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if (r) {
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radeon_bo_unreserve(rdev->gart.table.vram.robj);
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return r;
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}
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r = radeon_bo_kmap(rdev->gart.table.vram.robj,
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(void **)&rdev->gart.table.vram.ptr);
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if (r)
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radeon_bo_unpin(rdev->gart.table.vram.robj);
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radeon_bo_unreserve(rdev->gart.table.vram.robj);
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rdev->gart.table_addr = gpu_addr;
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return r;
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}
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void radeon_gart_table_vram_free(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.table.vram.robj == NULL) {
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return;
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}
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r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
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if (likely(r == 0)) {
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radeon_bo_kunmap(rdev->gart.table.vram.robj);
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radeon_bo_unpin(rdev->gart.table.vram.robj);
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radeon_bo_unreserve(rdev->gart.table.vram.robj);
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}
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radeon_bo_unref(&rdev->gart.table.vram.robj);
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}
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/*
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* Common gart functions.
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*/
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void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
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int pages)
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{
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unsigned t;
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unsigned p;
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int i, j;
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u64 page_base;
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if (!rdev->gart.ready) {
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WARN(1, "trying to unbind memory to unitialized GART !\n");
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return;
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}
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t = offset / RADEON_GPU_PAGE_SIZE;
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p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
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for (i = 0; i < pages; i++, p++) {
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if (rdev->gart.pages[p]) {
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// pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
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// PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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rdev->gart.pages[p] = NULL;
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rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
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page_base = rdev->gart.pages_addr[p];
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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radeon_gart_set_page(rdev, t, page_base);
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page_base += RADEON_GPU_PAGE_SIZE;
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}
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}
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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}
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int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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int pages, u32_t *pagelist)
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{
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unsigned t;
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unsigned p;
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uint64_t page_base;
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int i, j;
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ENTER();
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dbgprintf("offset %x pages %x list %x\n",
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offset, pages, pagelist);
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if (!rdev->gart.ready) {
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DRM_ERROR("trying to bind memory to unitialized GART !\n");
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return -EINVAL;
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}
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t = offset / RADEON_GPU_PAGE_SIZE;
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p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
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for (i = 0; i < pages; i++, p++) {
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/* we need to support large memory configurations */
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/* assume that unbind have already been call on the range */
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rdev->gart.pages_addr[p] = pagelist[i] & ~4095;
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rdev->gart.pages[p] = pagelist[i];
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page_base = rdev->gart.pages_addr[p];
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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radeon_gart_set_page(rdev, t, page_base);
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page_base += RADEON_GPU_PAGE_SIZE;
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}
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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return 0;
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}
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void radeon_gart_restore(struct radeon_device *rdev)
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{
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int i, j, t;
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u64 page_base;
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for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
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page_base = rdev->gart.pages_addr[i];
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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radeon_gart_set_page(rdev, t, page_base);
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page_base += RADEON_GPU_PAGE_SIZE;
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}
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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}
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int radeon_gart_init(struct radeon_device *rdev)
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{
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int r, i;
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if (rdev->gart.pages) {
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return 0;
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}
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/* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
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if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
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DRM_ERROR("Page size is smaller than GPU page size!\n");
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return -EINVAL;
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}
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r = radeon_dummy_page_init(rdev);
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if (r)
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return r;
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/* Compute table size */
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rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
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rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
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DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
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rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
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/* Allocate pages table */
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rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
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GFP_KERNEL);
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if (rdev->gart.pages == NULL) {
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radeon_gart_fini(rdev);
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return -ENOMEM;
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}
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rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
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rdev->gart.num_cpu_pages, GFP_KERNEL);
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if (rdev->gart.pages_addr == NULL) {
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radeon_gart_fini(rdev);
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return -ENOMEM;
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}
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/* set GART entry to point to the dummy page by default */
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for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
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rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
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}
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return 0;
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}
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void radeon_gart_fini(struct radeon_device *rdev)
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{
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if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
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/* unbind pages */
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radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
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}
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rdev->gart.ready = false;
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kfree(rdev->gart.pages);
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kfree(rdev->gart.pages_addr);
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rdev->gart.pages = NULL;
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rdev->gart.pages_addr = NULL;
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}
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